Tapered Etching Patents (Class 438/40)
  • Patent number: 5814858
    Abstract: A vertical power MOSFET, which could be a trench-gated or planar double-diffused device, includes an N+ substrate and an overlying N-epitaxial layer. An N-type buried layer is formed in the epitaxial layer and overlaps the substrate, the buried layer having a dopant concentration which is greater than the dopant concentration of the epitaxial layer but less than the dopant concentration of the substrate. The ion implant which is used to create the buried layer is preferably performed after most of the high temperature operations in the fabrication process in order to minimize the diffusion of the buried layer. This controls the distance between the top edge of the buried layer and the drain-body junction of the MOSFET and allows the breakdown voltage and on-resistance of the MOSFET to be determined substantially without regard to the thickness of the epitaxial layer.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: September 29, 1998
    Assignee: Siliconix incorporated
    Inventor: Richard K. Williams
  • Patent number: 5814531
    Abstract: A semiconductor laser includes a patterned semiconductor substrate including a lower flat plane portion, an upper flat plane portion, and a stripe-shaped slant plane portion connecting the lower flat plane portion and the upper flat plane portion, an active layer formed on the semiconductor substrate, an upper cladding layer formed on the active layer, current blocking layers formed on portions of the cladding layer, the portions respectively corresponding to the lower flat plane portion to the upper flat plane portion; and a current channel region formed on a portion of the upper cladding layer corresponding to the slant plane portion. There are satisfied relations t1>t2 and tan.sup.-1 (2t1/W).ltoreq..theta.+.phi.<90.degree., where t2 is thickness of the flat plane portions of the upper cladding layer, t1 is thickness of the slant plane portion of the upper cladding layer, .theta.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: September 29, 1998
    Assignee: Fujitsu Limited
    Inventors: Chikashi Anayama, Hiroshi Sekiguchi, Makoto Kondo
  • Patent number: 5792674
    Abstract: Disclosed is a tapered thickness waveguide integrated semiconductor laser which has an active layer in which light emits and recombines; and an output tapered waveguide which facilitates an optical coupling to an optical fiber; wherein the active layer and the output tapered waveguide are monolithically integrated on a common substrate, and the output waveguide has a buried structure and the width and thickness of the output waveguide are smaller than those of the active layer. The active layer may be placed between two cladding layers each of which has a different conductivity type with each other, and the output tapered waveguide has a portion which contacts undoped cladding layer.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: August 11, 1998
    Assignee: NEC Corporation
    Inventor: Mitsuhiro Kitamura
  • Patent number: 5789275
    Abstract: The present invention relates to a method for fabricating a semiconductor laser diode in optical communication system, and the present invention uses both an oxide and a nitride pattern as an etch mask instead of the single oxide pattern in order to decrease the under cut of the edge of the oxide pattern.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: August 4, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Soo Won Lee, Gyu Seog Cho, Tae Jin Kim, Kyung Seok Oh
  • Patent number: 5786234
    Abstract: A method of fabricating a semiconductor laser includes successively epitaxially growing on a first conductivity type semiconductor substrate, a first conductivity type lower cladding layer, an active layer, a second conductivity type first upper cladding layer having a relatively high etching rate in an etchant, a second conductivity type etch stopping layer having a relatively low etching rate in the etchant, a second conductivity type second upper cladding layer, and a second conductivity type first contact layer; forming a stripe-shaped mask on the first contact layer; removing portions of the first contact layer and the second upper cladding layer in a first wet etching step to expose the etch stopping layer; removing portions of the second upper cladding layer in a second wet etching step to form a stripe-shaped ridge structure having a reverse mesa cross section without an intermediate construction; growing a first conductivity type current blocking layer contacting both sides of the ridge structure; an
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: July 28, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Nagai, Hitoshi Tada
  • Patent number: 5770474
    Abstract: A method of fabricating a laser diode with reverse mesa structure has the following processes. A buffer layer of a first conductivity type, an active layer, a clad layer of a second conductivity type and a high-concentration contact layer of the second conductivity type are sequentially formed on a compound semiconductor substrate of the first conductivity type. Predetermined portions of the contact layer and of the clad layer are etched to form a reverse mesa structure. A passivation layer is formed on the overall substrate and the passivation existing on the reverse mesa structure is removed to expose the contact layer. A metal layer is formed on the exposed contact layer to contact therewith and a conductive metal layer is uniformly formed on the metal layer and the passivation layer. A pad metal layer is formed on the conductive metal layer to fill the etched portions of either side of the reverse mesa structure.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: June 23, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Ang-Seo Kim
  • Patent number: 5770471
    Abstract: In fabricating a semiconductor laser, an etch stopping layer of a semiconductor material not containing Al has a dopant impurity introduced during growth, by ion-implantation or by diffusion, from a high dopant concentration region located near the etch stopping layer. Since the etch stopping layer does not contain Al, it is less likely that the etch stopping layer will be oxidized during fabrication and a current blocking layer grown on the etch stopping layer has improved crystalline quality. Therefore, the current blocking effect is maintained and the reliability of the device is improved. The dopant impurity causes disordering of the etch stopping layer upon heat treatment, resulting in a larger band gap energy for the etch stopping layer than for an active layer. This prevents laser light originating in the active layer from being absorbed by the etch stopping layer. The characteristics of the laser are improved.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: June 23, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yutaka Nagai
  • Patent number: 5763291
    Abstract: A method of fabricating a semiconductor laser producing visible light includes forming a double heterojunction (DH) structure on a GaAs substrate including an n type GaAs buffer layer, an n type AlGaInP cladding layer, an Al.sub.x Ga.sub.(1-x) InP active layer, a first p type AlGaInP cladding layer, a p type GaInP etch stopping layer, a second p type AlGaInP cladding layer, and a p type GaAs cap layer. A stripe-shaped mask is formed on the DH structure, the p type GaAs cap layer is selectively etched using the mask, and the second p type AlGaInP cladding layer is selectively etched to the p type GaInP etch stopping layer to form a stripe-shaped ridge. Therefore, a high precision ridge can be formed easily.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: June 9, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Motoda, Manabu Kato
  • Patent number: 5734177
    Abstract: A semiconductor device formed on an insulating substrate of the present invention includes: a gate wiring provided on the insulating substrate; a first insulating film provided so as to cover the gate wiring; an upper electrode formed so as to face the gate wiring in such a manner that the first insulating film is interposed therebetween; a second insulating film provided so as to cover the upper electrode; and another electrode formed on the second insulating film, wherein the upper electrode is electrically connected to the another electrode via a contact hole formed through the second insulating film, a storage capacitor is formed of a structure including the upper electrode, the first insulating film, and the gate wiring opposing the upper electrode through the first insulating film, the upper electrode and the gate wiring have substantially the same width.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: March 31, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiromi Sakamoto
  • Patent number: 5726078
    Abstract: A buried-ridge structure of the quaternary/tertiary structures of In.sub.x Ga.sub.1-x As.sub.y P.sub.1-y /InGaP (x and y<1) are grown on a GaAs substrate by Low Pressure Metalorganic Chemical Vapor Deposition (LP-MOCVD) in a two-step process. The process comprises steps of growing and doping the requisite epitaxial layers, etching these layers so that stripes or mesas of material remain and then regrowing the material by gas molecular beam epitaxy (GSMBE). The structures are then processed into devices.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: March 10, 1998
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 5665612
    Abstract: Disclosed is a method for fabricating a planar buried heterostructure laser diode, comprising the steps of sequentially forming a first clad layer, an undoped active layer and a second clad layer on a substrate so as to complete a first crystal growth; forming a patterned mask layer on the second clad layer; non-selectively etching the second clad layer, the active layer, the first clad layer and the substrate using the mask layer as an etching mask; selectively etching the substrate and the first and second layers; sequentially forming a first and second current blocking layers on a structure formed by the selective etching step so as to complete a second crystal growth; sequentially forming a third clad layer and an ohmic contact layer thereon after removal of the mask layer so as to complete a third crystal growth; and forming a first electrode on a rear surface of the substrate and forming a second electrode on a surface of the third clad layer.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: September 9, 1997
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jung-Kee Lee, Dong-Hoon Jang, Jeong-Soo Kim, Kyung-Hyun Park
  • Patent number: 5629232
    Abstract: Light emitting devices are requiring greater switching speeds to achieve greater modulation bandwidths. The problems of intrinsic capacitance associated with conventional semiconductor heterojunction devices are reduced by the reduction of pn junction capacitance as well as the use of a semi-insulating blocking layer and a conductive substrate. Furthermore, a light absorbing layer is disposed on one side of an unetched portion of the semi-insulating material and an active layer disposed on opposite side. Also, the interface of the semi-insulating material and the active and absorbing layers are at prescribed angles that reduce back reflections to the absorbing and active layers. This arrangement reduces pumping in the absorbing region and thus reduces the lasing effect, allowing for a stable LED. The angle at the interface is determined by having the structure at a predetermined crystallographic direction and having the semi-insulating mesa etched to reveal a predetermined crystalline plane.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: May 13, 1997
    Assignee: The Whitaker Corporation
    Inventor: Ching-Long Jiang