Tapered Etching Patents (Class 438/40)
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Publication number: 20040002176Abstract: This invention proposes to make memory using organic materials. The basic structure of the memory cell is a field effect organic transistor using a ferroelectric thin film polymer as gate dielectric. By controlling the gate voltage to polarize the thin film ferroelectric polymer polarized in either an “up” or “down” state, the source-drain current can be controlled between two different values under the same source-drain voltage. The source-drain current thus can be used to represent either a “0” or “1” state. The organic thin film transistor can be made from poly(phenylenes), thiophene oligomers, pentacene, polythiophene, perfluoro copper phthalocyanine or other organic thin films. The ferroelectric thin film can be poly(vinylidene fluoride) (PVDF), poly(vinyldiene-trifluoroethylene) (P(VDF-TrFE)) copolymers, odd-numbered nylons, cyanopolymers, polyureas, or other ferroelectric thin films.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Applicant: Xerox CorporationInventor: Baomin Xu
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Patent number: 6664145Abstract: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.Type: GrantFiled: July 19, 2000Date of Patent: December 16, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yasuyuki Arai
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Patent number: 6661033Abstract: On an upper side there is a structured output coupling layer with flanks which are aligned at an angle between 60° and 88° with respect to a layer plane and which form boundaries for output coupling areas provided for the emergence of radiation and offset from one another. The output coupling areas are formed as flat truncated cones and can be rippled or zigzagged at the flanks, in order to increase the probability that the radiation produced strikes an outer interface of the output coupling layer more steeply than at a limiting angle of total reflection.Type: GrantFiled: December 30, 2002Date of Patent: December 9, 2003Assignee: OSRAM Opto Semiconductors GmbHInventors: Norbert Linder, Ralph Wirth, Heribert Zull
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Patent number: 6653176Abstract: A method for manufacturing an x-ray detector comprises the steps of: preparing an insulating substrate; forming a gate and a pad on the insulating substrate; forming a gate insulating film, an amorphous silicon layer and an etch stopper over the insulating substrate, inclusive of the gate and the pad; simultaneously forming a channel layer, an ohmic contact layer and a source/drain over the gate insulating film, inclusive of the etch stopper, and a common electrode over a proper portion of the gate insulating film; forming a first storage electrode over the gate insulating film, inclusive of the common electrode; forming a protective layer over the entire structure of the insulating substrate on which the source/drain and the first storage electrode have been formed, and subsequently forming a contact hole and via holes over a proper portion of the protective layer; and forming a second storage electrode over the protective layer.Type: GrantFiled: December 11, 2002Date of Patent: November 25, 2003Assignee: Boe-Hydis Technology Co., Ltd.Inventors: Hyun Jin Kim, Seung Moo Rim, Jin Hui Cho, Kyoung Seok Son
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Patent number: 6653162Abstract: An optical device having a current blocking layer of a buried ridge structure and a fabrication method thereof are disclosed. This invention reduces a leakage current between active layer and ion implant layer in buried ridge structure. To minimize leakage current, a P-N-P current blocking layer and an ion implanting current blocking layer are combined. An optical device of the present invention includes: active layers of a mesa structure in a predetermined region on a substrate; a first current blocking layer of a P-N-P structure, which is placed to cover the mesa structure; and a second current blocking layer of a buried ridge structure, which is placed to surround the environs of the first current blocking layer.Type: GrantFiled: April 3, 2002Date of Patent: November 25, 2003Assignees: Electronics and Telecommunications Research Institute, Korea TelecomInventors: Sung Bock Kim, Jeong Soo Kim
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Publication number: 20030190763Abstract: This invention provides a top-emitting OLED display device that includes a substrate; an array of OLED elements disposed on one side of the substrate; and a desiccant material provided in a patterned arrangement over the array of OLED elements on the same side of the substrate such that the desiccant material does not interfere with the light emitted by the OLED elements.Type: ApplicationFiled: April 4, 2002Publication date: October 9, 2003Applicant: Eastman Kodak CompanyInventors: Ronald S. Cok, Michael L. Boroson, Terrence R. O'Toole
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Patent number: 6627472Abstract: A ridge-type semiconductor laser producing method. This method includes the steps of successively laminating, on a compound semiconductor substrate, a lower clad layer, an active layer, and an upper first clad layer; forming, on the upper first clad layer, an upper second clad layer in the form of a ridge; and selectively growing a light confining layer at each side of the upper second clad layer in the form of a ridge. At the time of the selective growth of the light confining layers, there is used a III-group element feeding raw material including a III-group element compound having a methyl group.Type: GrantFiled: June 21, 2001Date of Patent: September 30, 2003Assignee: Rohm Co., Ltd.Inventor: Takashi Kimura
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Patent number: 6607933Abstract: A beam expander for providing coupling between a semiconductor optical device and an optical fiber comprises a double layer structure that may be integrated with the optical device. The first, underlying layer of the expander comprises a relatively high refractive index material (e.g., 3.34), thus providing improved coupling efficiency between the optical device and the fiber. The second, covering layer of the expander comprises a relatively low refractive index material (e.g., 3.28), for providing the large mode size desired at the fiber input. The parameters of each layer can be adjusted independently, allowing for the two criteria (coupling efficiency and mode size) to be separately optimized.Type: GrantFiled: August 7, 2001Date of Patent: August 19, 2003Assignee: Agere Systems Optoelectronics Guardian Corp.Inventors: Yuliya Anatolyevna Akulova, Mindaugas Fernand Dautartas, Marlin Wilbert Focht, Kenneth Gerard Glogovsky, Abdallah Ougazzaden, Justin Larry Peticolas
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Patent number: 6593162Abstract: The present invention relates to a method of manufacturing a semiconductor optical device. The present invention discloses a method of manufacturing an optical device of a planar buried heterostructure (PBH) type by which an active layer region of a taper shape at both ends is patterned, an undoped InP layer is selectively grown in order to reduce the propagation loss and two waveguides are simultaneously formed by means of a self-aligned method, thus simplifying the process to increase repeatability and yield.Type: GrantFiled: June 27, 2002Date of Patent: July 15, 2003Assignee: Electronics and Telecommunications Research InstituteInventors: Kyung Hyun Park, Yong Soon Baek, Sung Bock Kim, Kwang Ryong Oh
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Patent number: 6589807Abstract: The semiconductor device according to the present invention comprises a V-groove having V-shaped cross-section formed on a semiconductor substrate or on an epitaxial growth layer grown on a semiconductor substrate, and an active layer is provided only at the bottom of said V-groove. The method for manufacturing a semiconductor device according to the present invention comprises the steps of forming a stripe-like etching protective film in <011> direction of a semiconductor substrate or an epitaxial growth layer grown on it, performing gas etching using hydrogen chloride as etching gas on a semiconductor substrate or on an epitaxial growth layer grown on a semiconductor substrate to form a V-groove, and forming an active layer at the bottom of said V-groove.Type: GrantFiled: May 31, 2001Date of Patent: July 8, 2003Assignee: Mitsubishi Chemical CorporationInventors: Kenji Shimoyama, Kazumasa Kiyomi, Hideki Gotoh, Satoru Nagao
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Patent number: 6573116Abstract: There is provided a method of manufacturing a ridge type LC-DFB semiconductor laser in which a laser substrate having a cladding layer made of a material for a ridge stripe formed on an active layer made of semiconductor. A stripe mask is formed on the cladding layer to form two lateral flat portions from the cladding layer, by a selective wet etching, so as to form a ridge stripe protruding therefrom and having a flat top portion at which the stripe mask capped. A grating mask is formed on the two lateral flat portions, side walls of the ridge stripe and the stripe mask. The grating mask has a periodic structure in the direction in which the ridge stripe extends.Type: GrantFiled: July 20, 2001Date of Patent: June 3, 2003Assignee: Pioneer Electronic CorporationInventors: Yoshiaki Watanabe, Kiyoshi Takei, Nong Chen, Kiyofumi Chikuma
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Patent number: 6551848Abstract: A method for fabricating a semiconductor light emitting device is provided. The method involves: forming a light emitting construct including a p-type electrode on a n-type substrate; etching a bottom surface of the n-type substrate; and forming an n-type electrode on the etched bottom surface of the n-type substrate. The bottom surface of the n-type substrate is wet or dry etched. The bottom surface of the n-type substrate is free from damage so that stable attachment of the etched bottom surface of the n-type substrate is ensured with improved properties of the light emitting device which may be a semicoductor laser diode.Type: GrantFiled: March 14, 2002Date of Patent: April 22, 2003Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Joon-seop Kwak, Kyo-yeol Lee
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Patent number: 6548319Abstract: A method for manufacturing a semiconductor laser diode is described. The method for manufacturing a semiconductor laser diode includes sequentially forming a buffer layer, a first clad layer, a first waveguide layer, an active layer, a second waveguide layer, a second clad layer, and a cap layer on a substrate, patterning the cap layer, and patterning the second clad layer as a ridge structure by making the patterned cap layer as an upper layer, selectively forming a passivation layer for covering the second clad layer patterned as the ridge structure around the cap layer, and forming an electrode in contact with the cap layer on the passivation layer.Type: GrantFiled: August 10, 2001Date of Patent: April 15, 2003Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Joon-Seop Kwak
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Publication number: 20030042492Abstract: At least a lower cladding layer, an active layer for generating laser light, a first upper cladding layer, an etching stopper layer and a second upper cladding layer are stacked on a substrate. An impurity for restraining laser light absorption is diffused into the second upper cladding layer along a region where a light-emitting end surface is to be formed, under a condition that allows the etching stopper layer to maintain a function of stopping etching for the second upper cladding layer (First annealing process). Etching is performed until the etching stopper layer is reached such that the second upper cladding layer is left in a ridge shape. The impurity in the second upper cladding layer is re-diffused into the active layer to thereby cause local intermixing of the active layer in a portion extending along the light-emitting end surface and located just under the ridge (Second annealing process).Type: ApplicationFiled: September 5, 2002Publication date: March 6, 2003Inventor: Masanori Watanabe
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Patent number: 6521476Abstract: A method for manufacturing a semiconductor optical functional device, comprising: forming a laminated semiconductor layer over a substrate; forming an island-form preliminary pattern whose side wall surface is substantially perpendicular to the upper surface of the substrate by patterning all or part of the laminated semiconductor layer; forming an insulating material component on the top side of the substrate so that the upper surface of the preliminary pattern and part of the side walls of the preliminary pattern are exposed; and etching the side walls of the preliminary pattern and thereby changing the preliminary pattern into a reversed-mesa structure component that contributes to optical function and forming a space between the reversed-mesa structure component and the insulating material component.Type: GrantFiled: October 17, 2001Date of Patent: February 18, 2003Assignee: Oki Electric Industry Co., Ltd.Inventor: Munechika Kubota
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Patent number: 6512783Abstract: There is provided a semiconductor laser which comprises a first cladding layer formed of compound semiconductor having first conductivity type impurity and having a mesa-shaped projection, an active layer formed on the projection like a stripe and having side surfaces which are inclined at an angle of more than 70 degrees but less than 90 degrees relative to an upper surface of the first cladding layer, buried layers formed on both sides of the projection and having second conductivity type impurity, current blocking layers each having one end which contacts a virtual surface obtained by extending upward a side surface of the active layer and having a first facet which extends downward from the one end and is inclined by about 55 degrees relative to the upper surface of the first cladding layer and formed on each buried layer and having the first conductivity type impurity, and second cladding layers formed on the current blocking layers and the active layer and having the second conductivity type impurity.Type: GrantFiled: December 3, 1999Date of Patent: January 28, 2003Assignees: Fujitsu Limited, Fujitsu Quantum Devices LimitedInventors: Tsuyoshi Yamamoto, Hajime Shoji, Takayuki Watanabe, Takuya Fujii, Hirohiko Kobayashi
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Publication number: 20020187578Abstract: There is provided a method for manufacturing capacitor in a semiconductor memory device. The method for manufacturing a memory device having a dielectric layer includes the steps of forming a seed layer as a first dielectric layer by using an ALD method and forming a second dielectric layer by using a CVD method.Type: ApplicationFiled: May 24, 2002Publication date: December 12, 2002Inventor: Kwon Hong
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Publication number: 20020187579Abstract: A method for manufacturing a semiconductor optical functional device, comprising: forming a laminated semiconductor layer over a substrate; forming an island-form preliminary pattern whose side wall surface is substantially perpendicular to the upper surface of the substrate by patterning all or part of the laminated semiconductor layer; forming an insulating material component on the top side of the substrate so that the upper surface of the preliminary pattern and part of the side walls of the preliminary pattern are exposed; and etching the side walls of the preliminary pattern and thereby changing the preliminary pattern into a reversed-mesa structure component that contributes to optical function and forming a space between the reversed-mesa structure component and the insulating material component.Type: ApplicationFiled: October 17, 2001Publication date: December 12, 2002Inventor: Munechika Kubota
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Publication number: 20020187577Abstract: The present invention relates to a ridge-stripe semiconductor laser device and a process for producing the same. More specifically, the object of the present invention is to control the formation of cavities at the side of the ridge without adding any step, and to provide a ridge stripe semiconductor laser device with good properties by strictly controlling its ridge width and a process for producing the same. Thereby, it is possible to form a ridge whose sidewalls stand almost vertically.Type: ApplicationFiled: June 11, 2002Publication date: December 12, 2002Applicant: SHARP KABUSHIKI KAISHAInventors: Masahiko Sakata, Atsuo Tsunoda
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Patent number: 6465269Abstract: A semiconductor optical device has a gain region for oscillating a laser light beam and a spot-size conversion region for converting a spot-size of the laser light beam emitted from the gain region. Further, an optical waveguide is formed by the use of a selective growth mask along the gain region and the spot-size conversion region. With such a structure, the optical waveguide includes a waveguide taper portion and has a width and a facet. In this event, the width gradually becomes narrower towards the facet. As a result, the waveguide taper portion is tapered along a direction from the gain region towards the facet.Type: GrantFiled: February 16, 2001Date of Patent: October 15, 2002Assignee: NEC CorporationInventor: Yuji Furushima
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Patent number: 6455343Abstract: The present invention provides a method of manufacturing a light emitting diode based on an epitaxial layer structure. The epitaxial layer structure includes a substrate of a first conductivity type, a lower cladding layer of the first conductivity type formed on a top side of the substrate, an active layer formed on the lower cladding layer, an upper cladding layer of a second conductivity type formed on the active layer, at least one upper aluminum-rich layer formed on the upper cladding layer, and a cap layer formed on the at least one upper aluminum-rich layer. The method includes the steps of forming an opening hole in the epitaxial layer structure for passing through each upper aluminum-rich layer, oxidizing a predetermined region of each upper aluminum-rich layer, filling the opening hole with an insulating material, and forming an upper electrode on the cap layer and a lower electrode on a back side of the substrate.Type: GrantFiled: March 28, 2000Date of Patent: September 24, 2002Assignee: United Epitaxy Company, Ltd.Inventors: Tzer-Perng Chen, Chih-Sung Chang, Holin Chang
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Patent number: 6399286Abstract: A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.Type: GrantFiled: August 26, 1999Date of Patent: June 4, 2002Assignee: Taiwan Semiconductor Manufacturing Corp.Inventors: Yuan-Hung Liu, Bor-Wen Chan
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Patent number: 6358316Abstract: In a method for producing a semiconductor device, a compound semiconductor cap layer including no aluminum is grown on a compound semiconductor layer including aluminum, a mask pattern insulating film is formed on a part of the compound semiconductor cap layer, the compound semiconductor wafer with the insulating mask pattern is immersed in an ammonium sulfide solution, the compound semiconductor wafer is selectively etched away using a chlorine containing gas in a reaction chamber, and a groove formed in the etching process is filled with a compound semiconductor layer grown in the reaction chamber by MOCVD. Therefore, a regrowth interface on which no impurity is segregated is attained, improving the quality of the regrown crystal layer.Type: GrantFiled: August 9, 1995Date of Patent: March 19, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hirotaka Kizuki, Norio Hayafuji, Tatsuya Kimura
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Publication number: 20020022285Abstract: In the fabrication of a semiconductor laser emitting apparatus which emits laser beams having two different wavelengths, surface steps of the laminate film which is formed so as to cover the first semiconductor laser emitting device and constitutes the second semiconductor laser emitting device, is removed, so that processing with high precision is realized.Type: ApplicationFiled: February 28, 2001Publication date: February 21, 2002Inventor: Hironobu Narui
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Patent number: 6335216Abstract: A method for fabricating a semiconductor laser device includes the steps of patterning a first photoresist film on a top of a ridge stripe of a laser structure by using a second photoresist film as a mask. The first photoresist film is used for selectively etching an insulator film on the ridge stripe selectively from other portion on the side surfaces of the ridge stripe. The first photoresist film is of a negative image type having a viscosity of 50 centipoises.Type: GrantFiled: April 28, 2000Date of Patent: January 1, 2002Assignee: The Furukawa Electric Co., Ltd.Inventors: Junji Yoshida, Keiichi Yabusaki, Naoki Tsukiji
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Patent number: 6277663Abstract: A semiconductor laser diode includes a mesa having a width on a semiconductor substrate and aligned with a direction of resonance, a current blocking layer formed by selective growth on both sides of the mesa and having a first embedded layer and a second embedded layer covering the first embedded layer.Type: GrantFiled: September 14, 1999Date of Patent: August 21, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Keisuke Matsumoto, Kazuhisa Takagi, Tohru Takiguchi
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Patent number: 6261859Abstract: A surface-emitting semiconductor device is fabricated by a method comprising the steps of epitaxially growing, on a first substrate comprising a semiconductor, semiconductor layers having a semiconductor active layer capable of emitting light upon feed of an electric current; forming an electrode for feeding electric current to the semiconductor active layer; bonding the first substrate on which the semiconductor layers have been formed, to a second substrate with the former's semiconductor layer side inward; and removing the first substrate from the bonded substrates so as to leave the semiconductor layers on the second substrate.Type: GrantFiled: August 5, 1998Date of Patent: July 17, 2001Assignee: Canon Kabushiki KaishaInventor: Toshihiko Ouchi
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Patent number: 6238943Abstract: An optical semiconductor device of the present invention is provided with a core layer having a quantum well layer in that film thickness gets thinner from a inner region to an end portion in an optical waveguide region.Type: GrantFiled: September 22, 1999Date of Patent: May 29, 2001Assignee: Fujitsu LimitedInventors: Hirohiko Kobayashi, Mitsuru Ekawa, Nirou Okazaki, Shouichi Ogita, Haruhisa Soda, Haruhiko Tabuchi, Takuya Fujii
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Patent number: 6180429Abstract: The specification describes a lift-off technique useful in the manufacture of III-V semiconductor devices such as MQW lasers. The lift-off step is improved by a spacer layer of III-V semiconductor that can be non-selectively etched to form a mesa stripe, and selectively etched for the lift-off step. The spacer layer allows the etch mask to be dimensionally adjusted to reduce or eliminate overhang of the mesa, and prevent adverse shadowing effects. MBE is effective for both growing the multilayer stack and regrowing the blocking layer. A self-aligned mask on the multilayer stack can be produced by removing the overhang, and facilitating lift-off by producing an undercut in the III-V spacer layer using selective etching.Type: GrantFiled: November 23, 1998Date of Patent: January 30, 2001Assignee: Lucent Technologies Inc.Inventors: Klaus Alexander Anselm, James Nelson Baillargeon, Alfred Yi Cho, Wen-Yen Hwang
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Patent number: 6174748Abstract: A method for fabricating a high power laser diode device with an output emission with a nearly circular mode profile for efficient coupling into an optical fiber. A vertical taper waveguide and a window tolerance region are formed in a base structure of the device employing successive etching steps. Further regrowth completes the device structure. The resultant laser device has a vertical and lateral tapered waveguide that adiabatically transforms the highly elliptical mode profile in an active gain section of the device into a substantially circular mode profile in a passive waveguide section of the device.Type: GrantFiled: February 11, 2000Date of Patent: January 16, 2001Assignee: SDL, Inc.Inventors: Heonsu Jeon, Jean-Marc Verdiell
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Patent number: 6165811Abstract: A method of fabricating a semiconductor laser comprises the steps of sequentially depositing a lower cladding layer, an active layer, a first upper cladding layer, an etching stop layer, a second upper cladding layer and an ohmic contact layer over a compound semiconductor substrate, forming an etching mask over the ohmic contact layer so as to expose channel regions and to shield the ridge regions between the channel regions, performing wet etching to etch the ohmic contact layer and the second upper cladding layer so as to expose the etching stop layer so as to form the channels and the ridges having narrower widths than the parts of the etching mask shielding the ridge regions, and implanting dopant ions into the parts of the first upper cladding layer and the active layer below the channels to form ion-implanted regions by using the etching mask as the ion implantation mask.Type: GrantFiled: November 19, 1998Date of Patent: December 26, 2000Assignees: Electronics and Telecommunications Research Institute, Korea TelecomInventors: Jung Kee Lee, Kyung Hyun Park, Ho Sung Cho, Eun Soo Nam, Dong Hoon Jang
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Patent number: 6162655Abstract: A method of fabricating an expanded beam optical waveguide device (e.g., a laser), comprises the steps of (a) forming a first semiconductor waveguide region having first and second sections of different thickness and an intermediate vertical taper section of varying thickness coupling the first and second sections to one another, the first waveguide region being effective to expand the size of the beam as it propagates from the first section to the second section, (b) forming a second semiconductor region (e.g., a laser active region) on the first waveguide region, (c) etching the second region so as to form an essentially vertical first surface of length A-B which extends obliquely across the propagation axis of the device, (d) forming a third semiconductor region (e.g.Type: GrantFiled: January 11, 1999Date of Patent: December 19, 2000Assignee: Lucent Technologies Inc.Inventors: John Evan Johnson, Leonard Jan-Peter Ketelsen, Janet L. Lentz, Charles H. Joyner, Sharon Kay Sputz
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Patent number: 6143583Abstract: The method of the present invention provides a process for manufacturing MEMS devices having more precisely defined mechanical and/or electromechanical members. The method of the present invention begins by providing a partially sacrificial substrate and a support substrate. In order to space the mechanical and/or electromechanical members of the resulting MEMS device above the support substrate, mesas are formed on the support substrate. By forming the mesas on the support substrate instead of the partially sacrificial substrate, the mechanical and/or electromechanical members can be more precisely formed from the partially sacrificial substrate since the inner surface of the partially sacrificial substrate is not etched and therefore remains planar. As such, trenches can be precisely etched through the planar inner surface of the partially sacrificial substrate to define mechanical and/or electromechanical members of the MEMS device.Type: GrantFiled: June 8, 1998Date of Patent: November 7, 2000Assignee: Honeywell, Inc.Inventor: Ken Maxwell Hays
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Patent number: 6136624Abstract: An array substrate typically used in a liquid crystal display device includes inter-layer insulating films thick enough to prevent step-off breakage of conductive layers at contact holes while promising a reliability. Thick inter-layer insulating films are made by stacking a film made of an inorganic material, such as silicon nitride or silicon oxide, having a low moisture permeability and thereby promising a reliability of the liquid crystal display device, and a film made of an organic material, such as acrylic resin, that can be readily stacked thick so that the inner wall of the contact hole is gently sloped with respect to the substrate surface to thereby prevent step-off breakage of a conductive layer as thin as 100 nm or less.Type: GrantFiled: March 9, 1998Date of Patent: October 24, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Masato Kemmochi, Masato Shoji
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Patent number: 6130142Abstract: While a silicon substrate is heated, gold is evaporated thereon at a thickness of 0.6 nm, whereby melted alloy droplets are formed on the substrate surface. Then, the silicon substrate is heated to 450.degree.-650.degree. C. in a silane gas atmosphere of less than 0.5 Torr. As a result, a silane gas decomposition reaction occurs with the melted alloy droplets serving as catalysts, whereby silicon wires grow on the substrate surface. Subsequently, the metal alloy droplets at the tips of the silicon wires are removed and surface portions of the silicon wires are oxidized. Resulting surface oxide films are thereafter removed. As a result, silicon quantum wires that are thinner by the thickness of the surface oxide films are obtained.Type: GrantFiled: August 18, 1999Date of Patent: October 10, 2000Assignee: Sony CorporationInventors: Jonathan Westwater, Dharam Pal Gosain, Miyako Nakagoe, Setsuo Usui
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Patent number: 6103542Abstract: An optoelectronic device, such as a laser of the ridge waveguide type, can be provided with the necessary mesa (14) by means of wet or dry etching with a mask (20). The etching process is stopped when an etching stopper layer (5) is reached. A laser obtained by wet etching is indeed least expensive, but it is found to have a kink in its power-current characteristic at an undesirably low power value.According to the invention, such a laser must be manufactured in that the mask (20) used is given a width which is (much) greater than the width desired for the mesa (14), and in that, after a (preferably wet) etching process down to or down to close to the etching stopper layer (5), etching is continued with a wet isotropic etchant which is selective relative to the etching stopper layer (5) until the mesa (14) formed has the desired width.A very narrow and steep mesa (14) can thus be realized in an inexpensive manner.Type: GrantFiled: September 25, 1997Date of Patent: August 15, 2000Assignee: JDS Uniphase CorporationInventors: Hendrik G. Pomp, Bernardus A. H. Van Bakel, Johanna M. Bokhorst, Leo M. Weegels
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Patent number: 5991322Abstract: A semiconductor optical device includes a first semiconductor layer, and a diffraction grating disposed on the first semiconductor layer. The diffraction grating includes portions of a superlattice layer grown on the first semiconductor layer and including alternatingly arranged second semiconductor layers of a semiconductor material in which mass transport hardly occurs during growth of other semiconductor layers and third semiconductor layers of a semiconductor material different from the material of the second semiconductor layers. The device includes a fourth semiconductor layer burying the diffraction grating. In this structure, since the second semiconductor layers are included in the diffraction grating, the shape of the diffraction grating is maintained during the vapor phase deposition of the fourth semiconductor layer. Therefore, the thickness, amplitude, and pitch of the diffraction grating that determine the optical coupling constant are controlled with high precision.Type: GrantFiled: July 21, 1995Date of Patent: November 23, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tohru Takiguchi, Katsuhiko Goto, Hirotaka Kizuki
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Patent number: 5963786Abstract: A semiconductor laser has a first conduction type clad layer, an active layer and a second conduction type clad layer formed on a first conduction type semiconductor substrate in this order. An inverted mesa-shaped ridge is formed on a part of the second conduction type clad layer and a first conduction type current stopping layer is formed on each side of the ridge. Each side of the inverted mesa-shaped ridge is curved into a concave surface in a plane perpendicular to the longitudinal direction of the ridge.Type: GrantFiled: January 21, 1998Date of Patent: October 5, 1999Assignee: Fuji Photo Film Co., Ltd.Inventor: Hideki Asano
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Patent number: 5950068Abstract: A semiconductor device comprises a monocrystalline silicon wafer having a major surface lying in the {100} crystal plane. Disposed on the surface is a mesa having a generally square cross-section with generally rounded corners. The mesa has four main side walls each having a slope of around 45 degrees with respect to the base plane of the mesa, and the horizontal edges of the main side walls are disposed at an angle of at least around 12 degrees to the {111} directions on the wafer surface. The corners of the mesa each comprises a number of surfaces also having slopes of around 45 degrees and one surface having a slope of around 54 degrees. A high-low (N.sup.+ N.sup.- or P.sup.+ P.sup.-) junction is disposed within the mesa and makes a continuous line intercept with the mesa side walls around the entire periphery of the mesa. Except for exceptionally small deviations of no great significance, the high-low junction intercept is at a constant height location entirely around the mesa periphery.Type: GrantFiled: August 30, 1996Date of Patent: September 7, 1999Assignee: General Instrument Corp.Inventor: W. G. Einthoven
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Patent number: 5923949Abstract: Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode on a surface of a substrate and forming fluorine bearing spacers on the sidewalls of the gate electrode. The fluorine bearing spacers may, for example, be formed of an NF.sub.3 -doped glass material.Type: GrantFiled: March 21, 1997Date of Patent: July 13, 1999Assignee: Advanced Micro DevicesInventors: Mark I. Gardner, Mark C. Gilmer
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Patent number: 5920767Abstract: The disclosure describes a method of forming a groove in a structure of a semiconductor laser diode, which comprises a crystal growth procedure of epitaxial growth of a core layer comprising MP, wherein M represents one or more of elements belonging to group IIIb of periodic table and an upper layer comprising MAs, wherein M represents one or more of elements belonging to group IIIb of periodic table, successively on (100) surface of MAs crystals in a lower layer comprising MAs; a photolithography and wet etching procedure of, after forming an etching mask on the upper layer, forming an etching window to the etching mask; a first etching procedure of selective etching the upper layer; and a second etching procedure of selective etching other faces except for the face in which (111) face of MP crystals in the core layer is exposed.Type: GrantFiled: July 22, 1996Date of Patent: July 6, 1999Assignee: Mitsubishi Chemical CompanyInventors: Hideyoshi Horie, Toshinari Fujimori, Satoru Nagao, Nobuyuki Hosoi, Hideki Goto
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Patent number: 5910012Abstract: A waveguide type semiconductor photodetecting device has a semiconductor substrate, a photodetecting element, and a waveguide optically coupled with the photodetecting element which can avoid occurrence of light loss in the tapered waveguide even when a width of a light inciding side of the tapered waveguide is widened. The waveguide has a waveguide layer gradually narrowing a width and gradually increasing a layer thickness and a refraction index from light incident side to the photodetecting element. The waveguide is integrated with the photodetecting element on the semiconductor substrate.Type: GrantFiled: August 1, 1997Date of Patent: June 8, 1999Assignee: NEC CorporationInventor: Takeshi Takeuchi
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Patent number: 5888842Abstract: A method for manufacturing a surface-emitting laser array device is disclosed. In order to control the polarization characteristics of the surface-emitting laser, the surface-emitting laser array device according to the present invention can be manufactured by alternately arranging the surface-emitting laser formed by inclining a cavity in the <110> and <110> direction in accordance with the row or the column direction of the surface-emitting laser, so that the polarization characteristics of the surface-emitting laser in two directions which are relatively perpendicular to each other may be obtained. According to the present invention, it has an advantageous effect that the interaction between the adjacent laser beams can be minimized with maintaining the symmetric feature of the lasing beam when manufacturing an integrated surface-emitting laser array device.Type: GrantFiled: August 28, 1997Date of Patent: March 30, 1999Assignee: Electronics and Telecommunications Research InstituteInventors: Hye Yong Chu, Byueng-Su Yoo, Hyo-Hoon Park
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Patent number: 5888844Abstract: An (Al,Ga)As/(Al,Ga,In)P semiconductor layer structure is etched using an SiCl.sub.4 or an SiCl.sub.4 /(He,Ne) plasma. The etching is carried out at 0.degree. to 80.degree. C. and at a plasma pressure below 1.33.times.10.sup.-1 Pa (1 mTorr). The etched surfaces are sufficiently smooth for the etching process to be used in the production of (Al,Ga)As/(Al,Ga,In)P semiconductor lasers.Type: GrantFiled: February 26, 1997Date of Patent: March 30, 1999Assignee: Sharp Kabushiki KaishaInventors: Timothy David Bestwick, Craig Tombling
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Patent number: 5882951Abstract: An InP-based opto-electronic integrated circuit including an active layer having one or more quantum wells (36, 38). According to the invention, a barrier layer (34) of AlGaInAs is formed, preferably between the quantum wells and the substrate (30) to prevent the migration of species from the substrate and lower InP layers that tend to shift the emission wavelengths of the quantum wells to shorter wavelengths, i.e., a blue shift. The barrier layer can be patterned so that some areas of the quantum wells exhibit blue shifting to a shorter wavelength while other areas retain their longer wavelength during annealing.Type: GrantFiled: June 18, 1997Date of Patent: March 16, 1999Assignee: Bell Communications Research, Inc.Inventor: Rajaram Bhat
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Patent number: 5834329Abstract: A ridge wavegide laser diode, with an inverse mesa structure, resistant to heat and improved in the adhesion of a contact metal to a contact layer, which can be obtained by forming a polyimide spacer in such a way that polyimide remains only at the lower part of the corner of the inverse mesa structure. In the diode, the contact metal is minimally broken off at the opposite sides of the mesa structure.Type: GrantFiled: October 15, 1996Date of Patent: November 10, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Ang Seo Kim, Don Soo Kim, Sang Yong Lee, Young Kun Sin
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Patent number: 5834330Abstract: A II-VI semiconductor device is fabricated using a selective etchant in the form of aqueous solution of HX where X is Cl or Br. The II-VI semiconductor device is composed of a number of layers. Selective etching can be enabled by introducing Mg into one of the semiconductor layers. The resultant device may include a semiconductor layer containing Mg.Type: GrantFiled: October 7, 1996Date of Patent: November 10, 1998Assignee: Minnesota Mining and Manufacturing CompanyInventors: Michael A. Haase, Paul F. Baude, Thomas J. Miller
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Patent number: 5834331Abstract: A p-i-n structure for use in photoconductors and diodes is disclosed, being formed of an Al.sub.x Ga.sub.1-x N alloy (X=0.fwdarw.1) with In.sub.y Ga.sub.1-Y N (Y=0.fwdarw.1) which as grown by MOCVD procedure with the p-type layer adjacent the substrate. In the method of the subject invention, buffer layers of p-type material are grown on a substrate and then doped. The active, confinement and cap layers of n-type material are next grown and doped. The structure is masked and etched as required to expose a surface which is ion implanted and annealed. A p-type surface contact is formed on this ion-implanted surface which is of sufficiently low resistance as to provide good quality performance for use in a device.Type: GrantFiled: October 17, 1996Date of Patent: November 10, 1998Assignee: Northwestern UniversityInventor: Manijeh Razeghi
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Patent number: 5827754Abstract: A fabrication method for a high output quantum wire array laser diode structure having a low threshold current and a high output is formed by fabricating a short period GaAs quantum wire array and removing an unnecessary quantum well layer with laser holographic lithography techniques and a metalorganic chemical vapor deposition and by forming a current blocking layer which is required in fabricating a laser diode with lithography techniques using a photoresist mask on a micro-patterned structure.Type: GrantFiled: December 20, 1996Date of Patent: October 27, 1998Assignee: Korea Institute of Science and TechnologyInventors: Suk-Ki Min, Eun Kyu Kim
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Patent number: 5821134Abstract: Disclosed is a method of producing an electron-absorption modulator having a reverse mesa structure. In the electron-absorption modulator, a first clad of a first conductivity type, an active layer of the first conductivity type, a second clad layer of a second conductivity type and an ohmic contact layer of the second conductivity type are formed on a semiconductor substrate of the first conductivity type. Then, a predetermined mask pattern is formed on the ohmic contact layer. Afterwards, the ohmic contact layer is etched by using the mask pattern. Then, the second clad layer and the active layer below the ohmic contact layer are etched in the form of the reverse mesa structure to expose the first clad layer. Then, the first clad layer is etched at a predetermined depth in the form of a mesa structure.Type: GrantFiled: June 25, 1997Date of Patent: October 13, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Byung-Kwon Kang, Jung-Koo Kang, You-Ri Jo, Jong-Deog Kim, Seung-Jo Jeong, Young-kun Sin