Mesa Formation Patents (Class 438/39)
  • Patent number: 11710944
    Abstract: A multi-wavelength light emitting device is manufactured by forming first and second epitaxial materials overlying first and second surface regions. The first and second epitaxial materials are patterned to form a plurality of first and second epitaxial dice. At least one of the first plurality of epitaxial dice and at least one of the second plurality of epitaxial dice are transferred from first and second substrates, respectively, to a carrier wafer by selectively etching a release region, separating from the substrate each of the epitaxial dice that are being transferred, and selectively bonding to the carrier wafer each of the epitaxial dice that are being transferred. The transferred first and second epitaxial dice are processed on the carrier wafer to form a plurality of light emitting devices capable of emitting at least a first wavelength and a second wavelength.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: July 25, 2023
    Assignee: KYOCERA SLD Laser, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, Eric Goutain, James W. Raring, Paul Rudy, Vlad Novotny
  • Patent number: 11267392
    Abstract: A partition member (20) partitions a space occupied by a person from the outside. The space is, for example, an interior of a mobile object (30) such as a vehicle. A substrate (100) is disposed on a surface of the partition member (20) on the space side and has optical transparency. On a surface (a second surface (110b)) of the substrate (100) on the space side, a plurality of light-emitting units and an insulating layer (150) are disposed. Each light-emitting unit (140) includes a light-transmitting first electrode (110), an organic layer (120), and a second electrode (130) in this order from the external side. The insulating layer (150) defines the plurality of light-emitting units (140). A third region (106: a light-transmitting region) in the substrate (100) in which the second electrode (130) and the insulating layer (150) are not formed is provided between light-emitting units (140) next to each other.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: March 8, 2022
    Assignee: PIONEER CORPORATION
    Inventors: Hiroki Tan, Teruichi Watanabe, Isamu Ohshita
  • Patent number: 11164991
    Abstract: A light emitting device includes: a plurality of light emitting elements; a plurality of light transmissive members, each located on an upper surface of a respective one of the light emitting element; a mounting board on which the light emitting elements are disposed; a first cover member located on or above the mounting board, the first cover member comprising: a first reflective material containing layer disposed between the light emitting elements and containing a first reflective material, and a light transmissive layer disposed between the light transmissive members; and a second cover member disposed around the light emitting elements and comprising a second reflective material.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 2, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Ozeki, Atsushi Kojima, Chinami Nakai
  • Patent number: 11107945
    Abstract: A component includes a light emitting semiconductor chip, wherein the semiconductor chip includes a layer arrangement including a plurality of layers, the p-conducting layer and the n-conducting layer adjoin one another in an active zone, a first electrical contact is configured on the p-conducting side of the layer arrangement at a first side of the semiconductor chip, a second electrical contact is configured on the n-conducting side of the layer arrangement at a second side of the semiconductor chip, the second side being situated opposite the first side of the semiconductor chip, the first side of the semiconductor chip transitions into the second side via an end side, the semiconductor chip is secured by the end side on a substrate, the substrate includes a first and second further electrical contact, and the further electrical contacts electrically conductively connect to the electrical contacts of the semiconductor chip.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: August 31, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Alexander Linkov, Frank Singer, Matthias Bruckschloegl, Siegfried Herrmann, Jürgen Moosburger, Thomas Schwarz
  • Patent number: 11038321
    Abstract: Vertical-cavity surface-emitting lasers (VCSELs) and methods for making such are provided. The VCSELs include stepped upper reflectors having respective differently-sized apertures. This allows the lower portion of the reflector to have formed therein a wider-diameter aperture to allow for increased current injection. The upper portion of the reflector has formed therein a narrower-diameter, mode-selecting aperture to allow higher-order modes to be reduced, leading to single-mode operation. The VCSELs are thus capable of higher-power emission in a single mode, allowing for longer-distance signaling over optical fiber, despite modal dispersion within the fiber and/or at the coupling between the VCSEL and the fiber. The two differently-sized apertures can be formed via respective lateral oxidation processes following etch-down to form the respective steps of the upper reflector.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 15, 2021
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Milton Feng, Xin Yu
  • Patent number: 10923622
    Abstract: Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, a pixel element for a micro-light emitting diode (LED) display panel includes a first color nanowire LED, a second color nanowire LED, the second color different than the first color, and a pair of third color nanowire LEDs, the third color different than the first and second colors. A continuous insulating material layer ius laterally surrounding the first color nanowire LED, the second color nanowire LED, and the pair of third color nanowire LEDs.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Anup Pancholi, Ali Khakifirooz
  • Patent number: 10854584
    Abstract: An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide LED dies that are joined to a carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: December 1, 2020
    Assignee: CREE, INC.
    Inventors: Michael John Bergmann, David Todd Emerson, Joseph G. Clark, Christopher P. Hussell
  • Patent number: 10833211
    Abstract: A light generator comprises a light conversion device and a light source arranged to apply a light beam to the light conversion element. The light conversion device includes an optoceramic or other solid phosphor element comprising one or more phosphors embedded in a ceramic, glass, or other host, a metal heat sink, and a solder bond attaching the optoceramic phosphor element to the metal heat sink. The optoceramic phosphor element does not undergo cracking in response to the light source applying a light beam of beam energy effective to heat the optoceramic phosphor element to the phosphor quenching point.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: November 10, 2020
    Assignee: Materion Corporation
    Inventors: Michael P. Newell, Zan Aslett, Robert Cuzziere, Andrew P. Houde, Derrick Brown
  • Patent number: 10784325
    Abstract: A thin film transistor (TFT) to control a light emitting diode (LED) or an organic light emitting diode (OLED) includes a channel region configured as a saddle channel extending between the drain region and the source region of the TFT. The saddle channel is formed by deposition of channel material on a fin structure, and the contour of the saddle channel is defined by the contour of the fin structure. Deposition of the channel material for the saddle channel may be performed by: (i) atomic layer deposition (ALD) of amorphous silicon; (ii) ALD of amorphous silicon followed by annealing to form polycrystalline silicon; or (iii) deposition of indium gallium zinc oxide (IGZO) material by one of ALD, plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: September 22, 2020
    Assignee: INTEL CORPORATION
    Inventors: Khaled Ahmed, Prashant Majhi, Kunjal Parikh
  • Patent number: 10749070
    Abstract: In a method according to embodiments of the invention, a semiconductor structure including a III-nitride light emitting layer disposed between a p-type region and an n-type region is grown. The p-type region is buried within the semiconductor structure. A trench is formed in the semiconductor structure. The trench exposes the p-type region. After forming the trench, the semiconductor structure is annealed.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: August 18, 2020
    Assignee: LUMILEDS LLC
    Inventors: Isaac Wildeson, Erik Charles Nelson, Parijat Deb
  • Patent number: 10658548
    Abstract: A method for producing an optoelectronic semiconductor chip is specified, wherein a method step A) involves providing a semiconductor layer stack comprising a semiconductor layer of a first type, a semiconductor layer of a second type and an active layer arranged between the semiconductor layer of the first type and the semiconductor layer of the second type. Furthermore, the method comprises in a method step B) forming a mesa structure in the semiconductor layer of the first type, the semiconductor layer of the second type and the active layer. The method furthermore comprises in a method step C) applying a passivation layer to the mesa structure by means of vapour deposition or sputtering.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: May 19, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Fabian Kopp, Attila Molnar
  • Patent number: 10615548
    Abstract: A safety power connector includes a male section that has contacts for carrying electric current, one or more magnets, and a protrusion. A female section has a receptacle for receiving the protrusion and contacts that mate with contacts of the male section. When the male section is absent, no “hot” electrical potential is present at the contacts of the female section, thereby reducing potential for an electric shock. When the male section aligns with the female section and the protrusion inserted into the centrally located receptacle of the female section causes closure of a switch in the female section and a magnetic field from the one or more magnets of the male section cause closure of a magnetically actuated switch caused, providing electrical potential to the contacts of the female section that are now in contact with the contacts of the male section.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 7, 2020
    Inventor: Steven Pink
  • Patent number: 10608407
    Abstract: A method of manufacturing a semiconductor laser element includes: a cleaning process of holding a semiconductor light emission element that emits light from a facet thereof in a plasma sputtering device in which a target is covered with quartz, and cleaning the facet by irradiating the facet with plasma in the plasma sputtering device; and a dielectric film formation process of transporting the cleaned semiconductor light emission element to a deposition device without exposing the semiconductor light emission element to an atmosphere, and forming a dielectric film on the cleaned facet in the deposition device.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 31, 2020
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yutaka Ohki, Masafumi Tajima
  • Patent number: 9929314
    Abstract: Disclosed herein is an LED chip including electrode pads. The LED chip includes a semiconductor stack including a first conductive type semiconductor layer, a second conductive type semiconductor layer on the first conductive type semiconductor layer, and an active layer interposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a first electrode pad located on the second conductive type semiconductor layer opposite to the first conductive type semiconductor layer; a first electrode extension extending from the first electrode pad and connected to the first conductive type semiconductor layer; a second electrode pad electrically connected to the second conductive type semiconductor layer; and an insulation layer interposed between the first electrode pad and the second conductive type semiconductor layer. The LED chip includes the first electrode pad on the second conductive type semiconductor layer, thereby increasing a light emitting area.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: March 27, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Ye Seul Kim, Kyoung Wan Kim, Yeo Jin Yoon, Sang Hyun Oh, Keum Ju Lee, Jin Woong Lee, Da Yeon Jeong, Sang Won Woo
  • Patent number: 9716029
    Abstract: A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that are distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into a donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 25, 2017
    Assignee: SOITEC
    Inventors: Fabrice Lallement, Christophe Figuet, Daniel Delprat
  • Patent number: 9472741
    Abstract: A semiconductor light-emitting device includes a substrate; a first cladding layer formed on the substrate; a first guide layer formed on the first cladding layer; an active layer formed on the first guide layer; a second guide layer formed on the active layer; a contact layer formed on the second guide layer; a cladding electrode formed on the contact layer, and made of conductive metal oxide; and a pad electrode electrically coupled to the cladding electrode. The semiconductor light-emitting device includes a mesa structure including the contact layer. The cladding electrode has a greater width than the mesa structure. The cladding electrode covers an upper surface and side surfaces of the mesa structure, and is electrically coupled to the contact layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: October 18, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Hiroshi Ohno
  • Patent number: 9437785
    Abstract: Light emitting diodes include a silicon carbide substrate having first and second opposing faces, a diode region on the first face, anode and cathode contacts on the diode region opposite the silicon carbide substrate and a hybrid reflector on the silicon carbide substrate opposite the diode region. The hybrid reflector includes a transparent layer having an index of refraction that is lower than the silicon carbide substrate, and a reflective layer on the transparent layer, opposite the substrate. A die attach layer may be provided on the hybrid reflector, opposite the silicon carbide substrate. A barrier layer may be provided between the hybrid reflector and the die attach layer.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: September 6, 2016
    Assignee: Cree, Inc.
    Inventors: Michael John Bergmann, Kevin Ward Haberern, Bradley E. Williams, Winston T. Parker, Arthur Fong-Yuen Pun, Doowon Suh, Matthew Donofrio
  • Patent number: 9412813
    Abstract: One aspect includes a method for forming a buried material layer in a semiconductor body, including providing a semiconductor body having a first side and having a plurality of first trenches extending from the first surface into the semiconductor body. Each of the plurality of first trenches has a bottom and has at least one sidewall and the plurality of first trenches is separated from one another by semiconductor mesa regions. A first material layer is formed on the bottom of each of the plurality of first trenches such that the first material layer leaves at least one segment of at least one sidewall of each of the plurality of trenches uncovered. Each of the plurality of first trenches is filled by epitaxially growing a semiconductor material from the at least one uncovered sidewall segment. After filling the first trenches, second trenches are formed in the mesa regions.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: August 9, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Helmut Strack
  • Patent number: 9307664
    Abstract: A power adapter between an alternating current (AC) source and an external direct current (DC) consumer device consumes no electrical power until the DC device is connected to the power adapter. The power adapter includes a first magnet, a second magnet which is repelled by the first magnet, and a movable conductive member arranged on the second magnet. The insertion of the external DC device pushes the second magnet towards the first magnet and establishes a connection between the AC power source and the power adaptor. When the external device is removed, the movable conductive member is driven away by a repulsive force between the magnets to disconnect the external AC power source from the power adapter.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: April 5, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Min Lin, Chun-Fu Wu, I-Fan Chung
  • Patent number: 9246061
    Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-Type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: January 26, 2016
    Assignee: Koninklijke Philips N.V.
    Inventors: Jipu Lei, Kwong-Hin Henry Choy, Yajun Wei, Stefano Schiaffino, Danel Alexander Steigerwald
  • Patent number: 9236524
    Abstract: The present disclosure relates to a method of manufacturing a semiconductor light emitting device, comprising: forming a finger electrode in electrical communication with a second semiconductor layer; forming, on the finger electrode, a non-conductive reflective layer made up of a multi-layer dielectric film, for reflecting light from the active layer towards a first semiconductor layer on the side of a growth substrate, with the non-conductive reflective layer including a bottom layer formed by chemical vapor deposition and at least two layers formed by physical vapor deposition; and forming an electrical connection, passing through the non-conductive reflective film and being connected the finger electrode.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 12, 2016
    Assignee: SEMICON LIGHT CO., LTD.
    Inventors: Soo Kun Jeon, Eun Hyun Park, Yong Deok Kim
  • Patent number: 9223088
    Abstract: A method for manufacturing a semiconductor optical device includes the steps of forming a semiconductor mesa by etching a stacked semiconductor layer, the semiconductor mesa being defined by two grooves, one on each side of the semiconductor mesa; forming a first insulating film on a side surface and a top surface of the semiconductor mesa; forming a resin film on the first insulating film, the resin film filling the grooves; etching the resin film on the semiconductor mesa to form a first opening in the resin film, the first insulating film being exposed through the first opening; etching the first insulating film exposed through the first opening to expose the top surface of the semiconductor mesa; depositing an ohmic metal on the top surface of the semiconductor mesa; and depositing a second insulating film on the ohmic metal and a surface of the resin film.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: December 29, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hirohiko Kobayashi, Yoshihiro Yoneda, Hideki Yagi
  • Patent number: 9209021
    Abstract: A first side surface of post of the first stripe is formed so that a plane which is most parallel to the first side surface among low-index planes of the growing Group III nitride semiconductor is a m-plane (10-10), and a first angle between the first lateral vector obtained by orthogonally projecting a normal vector of the first side surfaces to the main surface and a m-axis projected vector obtained by orthogonally projecting a normal vector of the m-plane of the growing semiconductor to the main surface is from 0.5° to 6°. A second side surface of post of the second stripe is formed so that a plane which is most parallel to the second side surface among low-index planes of the growing semiconductor is an a-plane (11-20), and a second angle between the second lateral vector and an a-axis projected vector of the a-plane is from 0° to 10°.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: December 8, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Koji Okuno, Takahide Oshio, Naoki Shibata, Hiroshi Amano
  • Patent number: 9196796
    Abstract: Embodiments of the invention provide a semiconductor light emitting diode having an ohmic electrode structure, and a method of manufacturing the same. The semiconductor light emitting diode includes a light emitting structure having an upper surface constituting an N-face; and an ohmic electrode structure located on the light emitting structure. Here, the ohmic electrode structure includes a lower diffusion preventing layer, a contact layer, an upper diffusion preventing layer, and an Al protective layer from the N-face of the light emitting structure.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: November 24, 2015
    Assignees: Seoul Viosys Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Jong Lam Lee, Yang Hee Song
  • Patent number: 9159554
    Abstract: Embodiments described herein generally relate to a method of fabrication of a device structure comprising Group III-V elements on a substrate. A <111> surface may be formed on a substrate and a Group III-V material may be grown from the <111> surface to form a Group III-V device structure in a trench isolated between a dielectric layer. A final critical dimension of the device structure may be trimmed to achieve a suitably sized node structure.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: October 13, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Errol Antonio C. Sanchez, Xinyu Bao, Wonseok Lee, David Keith Carlson, Zhiyuan Ye
  • Patent number: 9158139
    Abstract: A method for manufacturing a Mach-Zehnder modulator includes the steps of forming a stacked semiconductor layer, the stacked semiconductor layer including a first conductivity type semiconductor layer, a core layer and a second conductivity type semiconductor layer, forming a waveguide mesa, the waveguide mesa having a first portion, a second portion and a third portion arranged between the first and second portions; forming a buried region on the waveguide mesa; forming an opening in the buried region on the third portion by etching the buried region using a mask; etching the second conductivity type semiconductor layer in the third portion through the buried region as a mask; and removing the buried region after etching the second conductivity type semiconductor layer. In the step of etching the second conductivity type semiconductor layer, the buried region covers a side surface of the third portion of the waveguide mesa.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: October 13, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takamitsu Kitamura, Hideki Yagi
  • Patent number: 9142719
    Abstract: A patterned substrate for epitaxially forming a light-emitting diode includes: a top surface; a plurality of spaced apart recesses, each of which is indented downwardly from the top surface and each of which is defined by a recess-defining wall, the recess-defining wall having a bottom wall face, and a surrounding wall face that extends from the bottom wall face to the top surface; and a plurality of protrusions, each of which protrudes upwardly from the bottom wall face of the recess-defining wall of a respective one of the recesses. A light-emitting diode having the patterned substrate is also disclosed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 22, 2015
    Assignee: NATIONAL CHUNG-HSING UNIVERSITY
    Inventors: Dong-Sing Wuu, Ray-Hua Horng, Wei-Ting Lin
  • Patent number: 9105807
    Abstract: A semiconductor optical emitting device comprises an at least partially transparent substrate and an active semiconductor structure arranged on a first side of the substrate. A first portion of light generated by the active semiconductor structure is emitted through the substrate from the first side of the substrate to a second side of the substrate along a primary light emission path. The second side of the substrate has a groove formed therein with at least first and second surfaces configured to reflect respective additional portions of the light generated by the active semiconductor structure along respective first and second angled light emission paths. The first and second angled light emission paths may be in opposite directions to one another and substantially perpendicular to the primary light emission path, although numerous other light emission path arrangements are possible.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: August 11, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Joseph M. Freund
  • Patent number: 9059061
    Abstract: The present disclosure provides an embodiment of an image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: June 16, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jeng-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Patent number: 9040328
    Abstract: A manufacturing method for an LED includes providing a substrate having a buffer layer and a first N-type epitaxial layer, forming a blocking layer on the first N-type epitaxial layer, and etching the blocking layer to form patterned grooves penetrating the blocking layer to the first N-type epitaxial layer. A second N-type epitaxial layer is then formed on the blocking layer to contact the first N-type epitaxial layer; a light emitting layer, a P-type epitaxial layer and a conductive layer are thereafter disposed on the second N-type epitaxial layer; an N-type electrode is formed to electrically connect with the first N-type epitaxial layer, and a P-type electrode is formed on the conductive layer. The N-type electrode is disposed on the blocking layer and separated from the second N-type epitaxial layer and has a portion extending into the patterned grooves to contact the first N-type epitaxial layer.
    Type: Grant
    Filed: May 4, 2014
    Date of Patent: May 26, 2015
    Assignee: Zhongshan Innocloud Intellectual Property Services Co., Ltd.
    Inventors: Ya-Wen Lin, Shih-Cheng Huang, Po-Min Tu, Chia-Hung Huang, Shun-Kuei Yang
  • Publication number: 20150124076
    Abstract: Exemplary embodiments provide solid-state microscope (SSM) devices and methods for processing and using the SSM devices. The solid-state microscope devices can include a light emitter array having a plurality of light emitters with each light emitter individually addressable. During operation, each light emitter can be biased in one of three operating states including an emit state, a detect state, and an off state. The light emitter can include an LED (light emitting diode) including, but not limited to, a nanowire based LED or a planar LED to provide various desired image resolutions for the SSM devices. In an exemplary embodiment, for near-field microscopy, the resolution of the SSM microscope can be essentially defined by the pitch p, i.e., center-to-center spacing between two adjacent light emitters, of the light emitter array.
    Type: Application
    Filed: January 7, 2015
    Publication date: May 7, 2015
    Inventor: Stephen D. Hersee
  • Publication number: 20150085888
    Abstract: To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (AWG) comprised of InP is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5° to 1.0° in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type InP is formed over the AWG with a V/III ratio of 2000 or more. Thereby, it is possible to obtain excellent multiple quantum wells (MQWs) by reducing a film thickness variation of the AWG. Moreover, the cover layer having side faces where a (0-11) plane almost perpendicular to a substrate surface mainly appears can be formed. A sectional shape of a lamination part of the cover layer and the AWG becomes an approximately rectangular shape. Therefore, an electrification region can be enlarged and it is possible to reduce a resistance of the semiconductor device.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 26, 2015
    Inventors: Satoshi AE, Shoutarou KITAMURA, Tetsuro OKUDA, Suguru KATO, Isao WATANABE
  • Publication number: 20150063391
    Abstract: An optical semiconductor device has: a semiconductor structure; a mesa structure including the semiconductor structure, a p-type semiconductor layer formed on a plane portion, a first side face and a second side face of the mesa structure, and a high-resistance semiconductor layer burying the mesa structure and the p-type semiconductor layer. The first side face is inclined toward a principal surface of the substrate more than the second side face. The p-type semiconductor layer has a carrier concentration in a portion related to the first side face lower than that of a portion related to the plane portion and the second side face. A distance between a lower end of the active layer and a boundary between the first side face and the second face in a vertical direction to the plane portion is not less than 0.1 ?m and not more than 0.5 ?m.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventor: Tatsuya Takeuchi
  • Patent number: 8962398
    Abstract: A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Publication number: 20150050768
    Abstract: A laser diode device includes: a semiconductor substrate including a semi-polar surface, the semiconductor substrate being formed of a hexagonal III-nitride semiconductor; an epitaxial layer including a light emitting layer, the epitaxial layer being formed on the semi-polar surface of the semiconductor substrate, and the epitaxial layer including a ridge section; a first electrode formed on a top surface of the ridge section; an insulating layer covering the epitaxial layer in an adjacent region of the ridge section and a side surface of the ridge section, the insulating layer covering part or all of side surfaces of the first electrode continuously from the epitaxial layer; a pad electrode formed to cover a top surface of the first electrode and the insulating layer, the pad electrode being electrically connected to the first electrode; and a second electrode formed on a surface, of the semiconductor substrate, opposite to the semi-polar surface.
    Type: Application
    Filed: September 26, 2014
    Publication date: February 19, 2015
    Inventors: Noriyuki FUTAGAWA, Hiroshi NAKAJIMA, Katsunori YANASHIMA, Takashi KYONO, Masahiro ADACHI
  • Publication number: 20150037919
    Abstract: A method of manufacturing a semiconductor laser according to an aspect of the present invention includes (a) sequentially epitaxially growing a first cladding layer, an active layer and a second cladding layer on a semiconductor substrate composed of InP or GaAs and having a plane index of (100), (b) forming a plurality of growth start surfaces having a plane index greater than (100) in an upper surface of the second cladding layer, and (c) epitaxially growing a third cladding layer containing zinc in the plurality of growth start surfaces of the second cladding layer.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 5, 2015
    Inventor: Masami ISHIURA
  • Patent number: 8932888
    Abstract: A method of applying a conversion means to an optoelectronic semiconductor chip includes preparing the optoelectronic semiconductor chip having a main radiation face, preparing the conversion means, the conversion means being applied to a main carrier face of a carrier, arranging the conversion means such that it faces the main radiation face and has a spacing relative to the main radiation face, and releasing the conversion means from the carrier and applying the conversion means to the main radiation face by irradiation and heating of an absorber constituent of the conversion means and/or of a release layer located between the conversion means and the carrier with a pulsed laser radiation which passes through the carrier.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: January 13, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Patent number: 8921141
    Abstract: Aspects of the invention provide methods and devices. In one embodiment, the invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanopyramids are grown utilizing a CVD based selective area growth technique. The nanopyramids are grown directly or as core-shell structures.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: December 30, 2014
    Assignee: Glo AB
    Inventors: Olga Kryliouk, Nathan Gardner, Giuliano Portilho Vescovi
  • Patent number: 8912028
    Abstract: A semiconductor light emitting device, which includes a light transmissive electrode layer formed using a conductive thin film and an insulating thin film to substitute for a transparent electrode layer, comprises a substrate; a first semiconductor layer formed on the substrate; an active layer formed on the first semiconductor layer; a second semiconductor layer formed on the active layer; a light transmissive electrode layer formed on the second semiconductor layer, the light transmissive electrode layer having a structure in which at least one conductive thin film and at least one insulating thin film are deposited; and a first electrode formed on the light transmissive electrode layer, wherein the light transmissve electrode layer includes at least one contact portion for contacting the at least one conductive thin film with the first electrode.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: December 16, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Taeil Jung, YoungChae Kim, SunMan Kim, Yeji Han, Chunghoon Park, Byeong-Kyun Choi, Se-Eun Kang
  • Patent number: 8912557
    Abstract: An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer. The first n-type GaN layer, the connecting layer, and the second n-type GaN layer are formed on the substrate in sequence. The connecting layer is etchable by alkaline solution, and a bottom surface of the second n-type GaN layer facing towards the connecting layer has a roughed exposed portion. The GaN on the bottom surface of the second n-type GaN layer is N-face GaN. A top surface of the second n-type GaN layer facing away from the connecting layer includes a first area and a second area. The light emitting layer and the p-type GaN layer are formed on the first area of the top surface of the second n-type GaN layer in sequence.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 16, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Tzu-Chien Hung, Chia-Hui Shen
  • Patent number: 8906727
    Abstract: In one embodiment, a method of growing a heteroepitaxial layer comprises providing a patterned substrate containing patterned features having sidewalls. The method also includes directing ions toward the sidewalls in an exposure, wherein altered sidewall regions are formed, and depositing the heteroepitaxial layer under a set of deposition conditions effective to preferentially promote epitaxial growth on the sidewalls in comparison to other surfaces of the patterned features.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: December 9, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Chi-Chun Chen, Cheng-Huang Kuo
  • Publication number: 20140353712
    Abstract: Embodiments of a monolithically integrated optical resonator are disclosed. In one embodiment, the optical resonator is a nanopillar optical resonator that is formed directly on a substrate and promotes a helically-propagating cavity mode. The helically-propagating cavity mode results in significant reflection or, in some embodiments, total internal reflection at an interface of the nanopillar optical resonator and the substrate even if refractive indices of the nanopillar optical resonator and the substrate are the same or similar. As a result, strong optical feedback, and thus strong resonance, is provided in the nanopillar optical resonator.
    Type: Application
    Filed: July 15, 2011
    Publication date: December 4, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Connie Chang-Hasnain, Forrest Sedgwick, Roger Chen, Thai-Truong Du Tran, Kar Wei Ng, Wai Son Ko
  • Patent number: 8900903
    Abstract: A method for producing an optical semiconductor device includes the steps of forming a semiconductor structure; forming a mask on the semiconductor structure; etching the semiconductor structure with the mask to form first and second stripe-shaped grooves and a mesa portion; forming a protective film on a top surface and side surfaces of the mesa portion; forming a resin portion on the protective film; etching the resin portion and the protective film formed on the top surface; forming an upper electrode on the top surface; and forming an electrical interconnection on the resin portion. The resin portion has an inclined surface region that rises from a first point above the mesa portion toward a second point above the first stripe-shaped groove. The step of etching the resin portion and the protective film includes the substeps of etching the resin portion and simultaneously etching the resin portion and the protective film.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: December 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshihiro Yoneda, Hirohiko Kobayashi, Ryuji Masuyama
  • Patent number: 8900902
    Abstract: Provided is a producing of a surface-emitting laser capable of aligning a center axis of a surface relief structure with that of a current confinement structure with high precision to reduce a surface damage during the producing. The producing of the laser having the relief provided on a laminated semiconductor layer and a mesa structure, the process comprising the steps of: forming, on the layer, one of a first dielectric film and a first resist film having a first pattern for defining the mesa and a second pattern for defining the relief and then forming the other one of the films; forming a second resist film to cover the second pattern and expose the first pattern; and forming the mesa by removing the layer under the first pattern using the second resist film.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: December 2, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tatsuro Uchida
  • Patent number: 8900901
    Abstract: A method is for manufacturing a nitride semiconductor laser element including a substrate, a nitride semiconductor layer that is laminated on the substrate and that has a ridge on its surface, an insulating protective film, and an electrode that is electrically connected with the nitride semiconductor layer. The method includes forming the ridge; forming a monocrystalline first film from the side faces of the ridge to the nitride semiconductor layer on both sides of the ridge; and forming a second film containing polycrystalline or an amorphous substance over the first film thereby forming the insulating protective film.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: December 2, 2014
    Assignee: Nichia Corporation
    Inventors: Shingo Masui, Tomonori Morizumi
  • Patent number: 8890184
    Abstract: A nanostructured light-emitting device including: a first type semiconductor layer; a plurality of nanostructures each including a first type semiconductor nano-core grown in a three-dimensional (3D) shape on the first type semiconductor layer, an active layer formed to surround a surface of the first type semiconductor nano-core, and a second type semiconductor layer formed to surround a surface of the active layer and including indium (In); and at least one flat structure layer including a flat-active layer and a flat-second type semiconductor layer that are sequentially formed on the first type semiconductor layer parallel to the first type semiconductor layer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-sung Kim, Taek Kim, Moon-seung Yang
  • Patent number: 8877652
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Patent number: 8878259
    Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Harold J. Hovel, Qiang Huang, Xiaoyan Shao, James Vichiconti, George F. Walker
  • Patent number: RE49298
    Abstract: The present invention provides a light emitting element capable or realizing at least one of lower resistance, higher output, higher power efficiency (1 m/W), higher mass productivity and lower cost of the element using a light transmissive electrode for an electrode arranged exterior to the light emitting structure. A semiconductor light emitting element includes a light emitting section, a first electrode and a second electrode on a semiconductor structure including first and second conductive type semiconductor layers, the first and the second electrodes respectively including at least two layers of a first layer of a light transmissive conductive film conducting to the first and the second conductive type semiconductor and a second layer arranged so as to conduct with the first layer. First and second light transmissive insulating films are respectively arranged so as to overlap at least one part of the first and the second layers.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: November 15, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Masahiko Sano, Takahiko Sakamoto, Keiji Emura, Katsuyoshi Kadan
  • Patent number: RE49406
    Abstract: The present invention provides a light emitting element capable or realizing at least one of lower resistance, higher output, higher power efficiency (1 m/W), higher mass productivity and lower cost of the element using a light transmissive electrode for an electrode arranged exterior to the light emitting structure. A semiconductor light emitting element includes a light emitting section, a first electrode and a second electrode on a semiconductor structure including first and second conductive type semiconductor layers, the first and the second electrodes respectively including at least two layers of a first layer of a light transmissive conductive film conducting to the first and the second conductive type semiconductor and a second layer arranged so as to conduct with the first layer. First and second light transmissive insulating films are respectively arranged so as to overlap at least one part of the first and the second layers.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: January 31, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Masahiko Sano, Takahiko Sakamoto, Keiji Emura, Katsuyoshi Kadan