Air Isolation (e.g., Beam Lead Supported Semiconductor Islands, Etc.) Patents (Class 438/411)
  • Patent number: 10541173
    Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: January 21, 2020
    Assignee: ASM IP Holding B.V.
    Inventor: Chiyu Zhu
  • Patent number: 10468349
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Patent number: 10373892
    Abstract: A solid state relay includes a source bus and a drain bus. Solid state switches are arranged to switch power from the drain bus to the source bus. A control circuit controls a gate of the solid state switches. Each solid state switch includes a source terminal, a drain terminal and a gate terminal. The source terminals are conductively attached to the source bus and the drain terminals are conductively attached to the drain bus. The gate terminal opens and closes power through the solid state switches. The source bus is electrically isolated from the drain bus when the plurality of solid state switches is controlled by the gate terminal to an open state, the source bus is in electrical communication with the drain bus when the solid state switches is controlled by the gate terminal to a closed state.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: August 6, 2019
    Assignees: TE CONNECTIVITY CORPORATION, TE CONNECTIVTY INDIA PRIVATE LIMITED
    Inventors: Palanisamy Vellaiyanaicken, Robert Steve Felisida Delacruz
  • Patent number: 9634042
    Abstract: The present disclosure provides a display substrate, a method for manufacturing the display substrate, and a display device. An intermediate layer is formed on an organic base plate, a thermal expansion coefficient of the intermediate layer is smaller than that of the organic base plate and greater than that of an inorganic thin film, and the inorganic thin film is formed on the intermediate layer.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: April 25, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tao Sun, Tao Gao, Song Zhang
  • Patent number: 9595655
    Abstract: A semiconductor device that is equipped with a semiconductor substrate, a composite metal film, and a detection terminal is provided. The composite metal film is formed on a surface or a back face of the semiconductor substrate, and has a first metal film, and a second metal film that is joined to the first metal film and is different in Seebeck coefficient from the first metal film. The detection terminal can detect a potential difference between the first metal film and the second metal film.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: March 14, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Yoshihito Mizuno
  • Patent number: 9159682
    Abstract: Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.
    Type: Grant
    Filed: September 8, 2013
    Date of Patent: October 13, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chee Seng Foong, Boon Yew Low, Navas Khan Oratti Kalandar
  • Patent number: 9125309
    Abstract: Provided is an epoxy resin allowing a cured product that is less changed in terms of heat resistance due to thermal history and has low thermal expansion, the epoxy resin having high solvent solubility. The epoxy resin is a polyglycidyl ether of a naphthol-novolac resin including, at predetermined proportions, a trimer and a dimer that have specific structures.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: September 1, 2015
    Assignee: DIC Corporation
    Inventor: Yutaka Satou
  • Patent number: 9099402
    Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 4, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Mirzafer Abatchev, Gurtej Sandhu
  • Patent number: 9035419
    Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Woo Oh, Dae-Sin Kim, Young-Kwan Park, Keun-Ho Lee, Seon-Young Lee
  • Publication number: 20150126001
    Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.
    Type: Application
    Filed: January 7, 2015
    Publication date: May 7, 2015
    Inventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez
  • Patent number: 8987860
    Abstract: A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-young Song, Cheol-ju Yun, Seung-hee Ko
  • Patent number: 8969164
    Abstract: A semiconductor structure comprises a substrate, a gate stack, a base area, and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate. A supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate; a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure. A stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure. Correspondingly, a method is provided for manufacturing such a semiconductor structure, which inhibits the short channel effect, reduces the parasitic capacitance and leakage current, and enhances the steepness of the source/drain region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 3, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8962443
    Abstract: A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 24, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Timothy J. Whetten, Wayne P. Richling
  • Patent number: 8921974
    Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: December 30, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thoralf Kautzsch, Boris Binder, Uwe Rudolph, Frank Hoffman
  • Patent number: 8906729
    Abstract: The invention relates to a micro-device with a cavity, the micro-device comprising a substrate, the method comprising steps of: A) providing the substrate, having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant, and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity, i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Patent number: 8901701
    Abstract: A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 2, 2014
    Inventor: Chia-Sheng Lin
  • Patent number: 8883610
    Abstract: In sophisticated metallization systems, air gaps may be formed on the basis of a self-aligned patterning regime during which the conductive cap material of metal lines may be protected by providing one or more materials, which may subsequently be removed. Consequently, the etch behavior and the electrical characteristics of metal lines during the self-aligned patterning regime may be individually adjusted.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: November 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert Seidel, Markus Nopper, Axel Preusse
  • Patent number: 8872305
    Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, James S. Dunn, David L. Harame, Anthony K. Stamper
  • Patent number: 8766427
    Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 1, 2014
    Assignee: NXP, B.V.
    Inventor: Marnix Bernard Willemsen
  • Patent number: 8748286
    Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Na, Young-Woo Park, Dong-Hwa Kwak, Tae-Yong Kim, Jee-Hoon Han, Jang-Hyun You, Dong-Sik Lee, Su-Jin Park
  • Patent number: 8741735
    Abstract: A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: June 3, 2014
    Assignee: SK hynix Inc.
    Inventors: Sung Min Hwang, Hyeon Soo Kim
  • Patent number: 8736018
    Abstract: A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hee Kim, Gil-Heyun Choi, Kyu-Hee Han, Byung-Lyul Park, Byung-Hee Kim, Sang-Hoon Ahn, Kwang-Jin Moon
  • Patent number: 8710618
    Abstract: An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: April 29, 2014
    Assignee: Honeywell International Inc.
    Inventors: Kenneth H. Heffner, William J. Dalzell, Kara L. Warrensford
  • Patent number: 8703598
    Abstract: A manufacturing method of a lead frame substrate includes: applying a photosensitive resist or a dry film to first and second surfaces of a metal plate; pattern-exposing the photosensitive resist or the dry film, and then developing the first surface and the second surface to form on the first surface a first resist pattern for forming a connection post and to form on the second surface a second resist pattern for forming a wiring pattern; etching the first surface partway down the metal plate to form the connection post; filling the first surface with a pre-molding resin to a thickness with which the etched surface is buried; removing the pre-molding resin uniformly in a thickness direction of the pre-molding resin until a bottom surface of the connection post is exposed; and etching the second surface to form a wiring pattern.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 22, 2014
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Susumu Maniwa, Takehito Tsukamoto, Junko Toda
  • Publication number: 20140097511
    Abstract: An integrated diode array and a corresponding manufacturing method are provided. The integrated diode array includes a substrate having an upper side, and a plurality of blocks of several diodes, which are positioned in a planar manner and are suspended at the substrate above a cavity situated below them in the substrate. The blocks are separated from one another by respective gaps, and within a specific block, the individual diodes are electrically insulated from one another by first STI trenches situated between them.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 10, 2014
    Applicant: ROBERT BOSCH GMBH
    Inventors: Gregor Schuermann, Hubert Benzel
  • Patent number: 8664078
    Abstract: An object is to provide a semiconductor device in which, through a simpler process, junction capacitance and power consumption can be reduced more than a conventional semiconductor device, and a manufacturing method thereof. An insulating film including an opening is formed over a base substrate and a part of a bond substrate is transferred to the base substrate, with the insulating film interposed therebetween, whereby a semiconductor film including a cavity between the semiconductor film and the base substrate is formed over the base substrate. Then, a semiconductor device including a semiconductor element such as a transistor is manufactured using the semiconductor film. The transistor includes a cavity between the base substrate and the semiconductor film used as an active layer. One cavity may be provided or a plurality of cavities may be provided.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hidekazu Miyairi
  • Patent number: 8629035
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming an isolation trench in a substrate, and forming an amorphous layer on a sidewall surface of the isolation trench. The method further includes forming a sacrificial layer in the isolation trench via the amorphous layer, and forming an air gap layer on the sacrificial layer. The method further includes forming an air gap in the isolation trench under the air gap layer by removing the sacrificial layer after forming the air gap layer.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Patent number: 8603889
    Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, James S. Dunn, David L. Harame, Anthony K. Stamper
  • Patent number: 8563421
    Abstract: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Bon-young Koo, Ki-hyun Hwang
  • Patent number: 8546237
    Abstract: A method of transferring an epitaxial film from an original substrate to a destination substrate comprises: growing an epitaxial film grown with a sacrificial layer on the original substrate; patterning the epitaxial film into a plurality of sections; attaching the plurality of sections to a stretchable film; removing the plurality of sections attached to the stretchable film from the original substrate; stretching the sections apart as needed; and attaching a permanent substrate to the plurality of sections; and trimming the sizes of the sections as needed for precise positioning prior to integrated circuit device fabrication.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: October 1, 2013
    Assignee: Oepic Semiconductors, Inc.
    Inventor: Majid Riaziat
  • Patent number: 8501577
    Abstract: A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 6, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Jiantao Bian, Zengfeng Di, Miao Zhang
  • Patent number: 8497183
    Abstract: A method of making a device. The method comprises providing a first layer including a first material on a surface of a substrate, removing a portion of the first layer and a corresponding portion of the substrate to form an opening in the first layer and a recessed portion in the surface of the substrate, and supplying a liquid mixture to the opening and the recessed portion. The liquid mixture includes a first component having a first chemical affinity to the first material and a second component having a second chemical affinity to the first material, which is smaller than the first chemical affinity. The method also includes removing the second component and forming a second layer including the first component. The second layer covers the recessed portion and adheres to an edge portion of the first layer, such that the second layer and the recessed portion define a cavity.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: July 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Hsiang Hsiang Ko, Hung Jui Chang, Yi Ming Chen, Hsien-Wei Lin
  • Patent number: 8492295
    Abstract: A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
  • Patent number: 8481400
    Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: July 9, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thoralf Kautzsch, Boris Binder, Frank Hoffmann, Uwe Rudolph
  • Patent number: 8481401
    Abstract: A method for manufacturing a component having a through-contact includes: providing a substrate; forming an insulating layer on the substrate; structuring the insulating layer, the insulating layer being removed at least in a predetermined trenching area surrounding a selected substrate area; performing an etching process in which the structured insulating layer functions as a mask to remove substrate material in the trenching area and to create a trench structure surrounding the selected substrate area; and forming a metallic layer on the insulating layer, the metallic layer sealing the trench structure.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: July 9, 2013
    Assignee: Robert Bosch GmbH
    Inventor: Jochen Reinmuth
  • Patent number: 8476118
    Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 8466033
    Abstract: A light emitting diode comprises a substrate, a buffer layer, a semiconductor layer and a semiconductor light emitting layer. The buffer layer is disposed on the substrate. The semiconductor layer is disposed on the buffer layer. The semiconductor light emitting layer is disposed on the semiconductor layer. A plurality of voids is defined within the semiconductor layer. Each void encloses air therein. A method for manufacturing the light emitting diode is also provided. Light generated by the semiconductor light emitting layer toward the substrate is reflected by the voids to emit out of the light emitting diode.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: June 18, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang, Shun-Kuei Yang, Chia-Hung Huang
  • Patent number: 8440538
    Abstract: In making an airbridge structure, a second resist layer is applied over a first resist layer. The resist layers are exposed and developed to have a predetermined width W2. A third resist layer is applied. The third resist layer is also exposed and developed to have a predetermined width W3. An airbridge-forming material layer is applied to the layer stack structure consisting of the first, second, and third resist layers, forming an airbridge. The resist layers are removed, completing the manufacture of the airbridge, which has a stepped cross section.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: May 14, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Kosaka, Ko Kanaya, Yoshihiro Tsukahara
  • Patent number: 8426290
    Abstract: A device and a method for manufacturing it are disclosed. The device contains a plurality of transistors, a plurality of transmission mediums connected to the transistors; and a substrate having a first portion supporting the transistors and the transmission mediums thereon, and further having a plurality of discrete second portions extending from the first portion. The method disclosed teaches how to manufacture the device.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: April 23, 2013
    Assignee: HRL Laboratories, LLC
    Inventor: Debabani Choudhury
  • Patent number: 8304316
    Abstract: In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: November 6, 2012
    Assignee: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Gehan Anil Joseph Amaratunga, Tanya Trajkovic, Vasantha Pathirana
  • Patent number: 8298911
    Abstract: In a method of forming a wiring structure, a first insulation layer is formed on a substrate, the first insulation layer comprising a group of hydrocarbon (C?H?) wherein ? and ? are integers. A second insulation layer is formed on the first insulation layer, the second insulation layer being avoid of the group of hydrocarbon. A first opening is formed through the first and the second insulation layers by etching the first and the second insulation layers. A damaged pattern and a first insulation layer pattern are formed by performing a surface treatment on a portion of the first insulation layer corresponding to an inner sidewall of the first opening. A sacrificial spacer is formed in the first opening on the damaged pattern and on the second insulation layer. A conductive pattern is formed in the first opening.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyoung-Woo Lee
  • Patent number: 8294194
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Noda, Hidenobu Nagashima
  • Patent number: 8264060
    Abstract: Providing a first layer of a semiconductor structure having at least one air gap between conductive lines formed in the first layer. The air gap extends into the first layer from a first surface of the first layer. A barrier dielectric material over the first surface and the air gap is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. An air gap can extend from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: September 11, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Greg Braeckelmann, Marius Orlowski, Andreas Wild
  • Patent number: 8258014
    Abstract: According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: September 4, 2012
    Assignee: Infineon Technologies AG
    Inventors: Cynthia Blair, Donald Fowlkes
  • Publication number: 20120208344
    Abstract: A chemical mechanical polishing (CMP) composition, comprising (A) at least one type of inorganic particles which are dispersed in the liquid medium (C), (B) at least one type of polymer particles which are dispersed in the liquid medium (C), (C) a liquid medium, wherein the zeta-potential of the inorganic particles (A) in the liquid medium (C) and the zeta-potential of the polymer particles in the liquid medium (C) are of same signs.
    Type: Application
    Filed: November 10, 2010
    Publication date: August 16, 2012
    Applicant: BASF SE
    Inventors: Michael Lauter, Vijay Immanuel Raman, Yuzhuo Li, Shyam Sundar Venkataraman, Daniel Kwo-Hung Shen
  • Patent number: 8241992
    Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
  • Patent number: 8232653
    Abstract: A wiring structure includes a conductive pattern on a substrate, a first insulation layer pattern between adjacent conductive patterns and a second insulation layer pattern on the first insulation layer pattern. The first insulation layer pattern is separated from the conductive pattern by a first distance to provide a first air gap. The second insulation layer pattern is spaced apart from the conductive pattern by a second distance substantially smaller than the first distance to provide a second air gap. The wiring structure may have a reduced parasitic capacitance while simplifying processes for forming the wiring structure.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyoung-Woo Lee
  • Patent number: 8211777
    Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
  • Patent number: 8163586
    Abstract: A method for producing a device with at least one suspended membrane, including the following steps: Producing a trench through a first sacrificial layer and a second layer deposited on the first sacrificial layer, the trench completely surrounding at least a portion of the first sacrificial layer and at least a portion of the second layer, filling all or a portion of the trench with at least one material capable of resisting at least one etching agent, and etching the portion of the first sacrificial layer with the etching agent through at least one opening made in the second layer, the portion of the second layer forming at least one portion of the suspended membrane.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: April 24, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Patrice Rey, Mouna Salhi
  • Patent number: 8153503
    Abstract: The invention relates to a method for protecting the interior of at least one cavity (4) having a portion of interest (5) and opening onto a face of a microstructured element (1), consisting of depositing, on said face, a nonconformal layer (6) of a protective material, in which said nonconformal layer closes off the cavity without covering the portion of interest. The invention also relates to a method for producing a device comprising such a microstructured element.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: April 10, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Barbara Charlet, Hélène Le Poche, Yveline Gobil