Abstract: A method for forming a through-silicon via includes the steps of defining a groove in each chip of a wafer which has a plurality of semiconductor chips; applying liquid polymer on the wafer to fill the groove; forming an insulation layer on a sidewall of the groove through patterning the polymer; forming a metal layer to fill the groove which is formed with the insulation layer on the sidewall thereof; and back-grinding a backside of the wafer to expose the metal layer filled in the groove.

Abstract: As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal base pattern on the chip to form the capped chip. In one embodiment, a front surface of the chip is exposed which extends from a contact of the chip to an edge of the chip. In another embodiment, a conductive connection is formed to the contact, the conductive connection extending from the contact to a terminal at an exposed plane above the front surface of the chip.

Abstract: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.

Abstract: An insulating film on a semiconductor substrate has a first titanium nitride film, an aluminum film, and a second titanium nitride film formed thereon, and an insulating film is formed so as to cover a lower electrode wiring. Then, the insulating film is dry-etched anisotropically so that the insulating film on the lower electrode wiring is removed, and a portion of the insulating film on the lower electrode wiring is left as a sidewall. A deposit deposited during the etching of the insulating film on the lower electrode wiring is removed by radical etching without using ion bombardment. The deposit contains Ti that is a metal element forming the second titanium nitride film. Subsequently, the second titanium nitride film is nitrided through ammonium plasma, and an insulating film to cover the lower electrode wiring is formed.

Abstract: Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through, the dielectric layer; forming a sacrificial layer on opposing sidewalls of the trench; filling the trench with a electrical conductor; and removing a portion of the sacrificial layer from between the electrical conductor and the dielectric layer to form air-gaps.

Abstract: An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive has partially cured, the wafer is singulated. The individual integrated circuits or die are then mounted onto a substrate such as a printed circuit board. When the solder balls of the integrated circuit are reflowed to form joints with corresponding contact pads on the substrate, the underfill adhesive reflows and is completely cured. In an alternative embodiment, the underfill adhesive is fully cured after it is disposed onto the active surface of the wafer.

Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

Abstract: A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.

Abstract: Provided is a lead frame package with an expansion plane to minimize electrical parasitics introduced into the semiconductor chip's electrical system (e.g., power delivery system, signal loops, etc.). Also provided are methods for assembling such lead frame packages into various semiconductor packages. Generally, a lead frame package includes a down set die attach pad over an underlying bottom plate. Both the die attach pad and the bottom plate may be used as intermediary connections for either power or ground connections. As compared to conventional lead frame package having an intermediary connection, the lead frame packages of the present invention can provide for any combination of shorter wire bond lengths, more wire bond connections, improved power delivery system, or reduced amounts of electrical parasitics.

Abstract: A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.

Abstract: A dielectric wiring structure and method of manufacture therefor. The wiring structure includes air dielectric formed in a hemisphere. The wiring structure also includes, in embodiments, a method of simultaneously forming a MEMS structure with a transistor circuit using substantially the same steps. The MEMS structure of this embodiment includes freestanding electrodes which are not fixed to the substrate.

Abstract: A method of manufacturing a MOS transistor is provided that achieves high-speed devices by reducing nitrogen diffusion to a silicon substrate interface due to redistribution of nitrogen and further suppressing its diffusion to a polysilicon interface, which prevents realization of faster transistors. An oxide film is exposed to a nitriding atmosphere to introduce nitrogen into the oxide film, and a thermal treatment process is performed in an oxidizing atmosphere. The thermal treatment process temperature in the oxidizing atmosphere is made equal to or higher than the maximum temperature in all the thermal treatment processes that are performed later than that thermal treatment process step.

Abstract: A multi-layered wire structure includes a substrate, a plurality of first conductive lines formed in a first layer over the substrate extending in parallel to each other in a first direction, a plurality of second conductive lines formed in a second layer over the first layer extending in parallel to each other in a second direction orthogonal to the first direction, a plurality of sets of third conductive lines formed in the second layer extending in the first direction, each set of third conductive lines corresponding to one of the first conductive lines, and a plurality of sets of conductive paths formed between the first layer and the second layer, each set of conductive paths corresponding to one of the first conductive lines and one set of third conductive lines and electrically connecting the corresponding first conductive line to the corresponding set of third conductive lines.

Abstract: Methods for forming porous insulative materials for use in forming dielectric structures of semiconductor devices are disclosed. Each insulative material may include a first, substantially nonporous state and a second, porous state. When in the first state, the insulative materials may be processed or support layers or structures which are being processed. When in the second state, the insulative materials have a reduced dielectric constant and, thus, increased electrical insulation properties. Semiconductor device structures including layers or other features formed from one of the insulative materials are also disclosed. Methods for forming the insulative material and for causing the insulative material to become porous are also disclosed.

Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

Abstract: In a method of forming a conductive line for a semiconductor device using a carbon nanotube and a semiconductor device manufactured using the method, the method includes activating a surface of an electrode of the semiconductor device using surface pretreatment to create an activated surface of the electrode, forming an insulating layer on the activated surface of the electrode, and forming a contact hole through the insulating layer to expose a portion of the activated surface of the electrode, and supplying a carbon-containing gas onto the activated surface of the electrode through the contact hole to grow a carbon nanotube, which forms the conductive line, on the activated surface of the electrode. Alternatively, the activation step of the surface of the electrode may be replaced with a formation of a catalytic metal layer on the surface of the electrode.

Abstract: A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions. In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.

Abstract: A dual layer of polymeric material is deposited with a base layer and top layer resist onto an integrated circuit structure with topography. The base layer planarizes the surface and fills in the native topography. The base layer decomposes almost completely when exposed to an oxidizing environment. The top layer contains a high composition of oxidizing elements and is photosensitive. (i.e., the layer can be patterned by exposing normal lithographic techniques.) The patterning allows the creation of escape paths for the decomposition products of the underlying base layer. This structure is decomposed in an oxidizing ambient (or plasma) leaving behind a thin carbon-containing membrane. This membrane layer blocks deposition of future layers, creating air gaps in the structure.

Abstract: A component having an airdome enclosure that protects the component from its external environment. An airdome enclosure according to the present techniques avoids the high costs of employing special materials and/or specialized process steps in the manufacture of a component. An electronic component according to the present techniques includes a set of substructures formed on a substrate and an airdome enclosure over the substructures that protects the substructures and that hinders the formation of parasitic capacitances among the substructures.

Abstract: The disclosure relates to method and apparatus for isolating sensitive regions of a semiconductor device by providing a thermal path or an electromagnetic shield. The thermal path may include vias having different length, depth and configuration such that the thermal path between the two regions is lengthened. In addition, the vias may be fully or partially filled with an insulating material having defined conductive properties to further retard heat electromagnetic or heat transmission between the regions. In another embodiment, electrical isolation between two regions is achieved by etching a closed loop or an open loop trench at the border of the regions and filling the trench with a conductive material to provide proper termination of electromagnetic fields within the substrate.

Abstract: A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1?xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1?xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1?xGex layer; trench etching of the top silicon and Si1?xGex, into the silicon substrate to form a first trench; selectively etching the Si1?xGex layer to remove substantially all of the Si1?xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1?xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.

Abstract: A method of manufacturing a semiconductor device has the steps of: forming a mushroom gate traversing an active region of a semiconductor substrate and having a fine gate and an expanded over gate formed thereon; coating a first organic material film on the semiconductor substrate; patterning the first organic material film and leaving the first organic material film only near the mushroom gate; coating a second organic (insulating) material film covering the left first organic material film; forming an opening through the second organic material film to expose the first organic material film; and dissolving and removing the first organic material film via the opening to form a hollow space in the second organic material film.

Abstract: A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer).

Abstract: A damascene interconnect that reduces interconnect intra-layer capacitance and/or inter-layer capacitance is provided. The damascene interconnect structure has air gaps between metal lines and/or metal layers. The interconnect structure is fabricated to a via level through a processing step prior to forming contact vias, then one or more air gaps are formed into the damascene structure so that the air gaps are positioned between selected metal lines. A sealing layer is then deposited over the damascene structure to seal the air gaps.

Abstract: A method for forming a semiconductor device having isolation structures decreases leakage current. A channel isolation structure decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures are formed under current electrode regions to prevent leakage between the current electrodes.

Abstract: An insulating sheet which connects a semiconductor chip and a wiring substrate is provided between the semiconductor chip and the wiring substrate. The insulating sheet has windows therethrough at positions corresponding to those of connection pads of the wiring substrate and has leads, one end of each of the leads being fixed on the sheet and the other end of each of the leads protruding from the opposite surface of the sheet through a window. Each of solder balls of the semiconductor chip is connected to the fixed one end of one of the leads, and each of the connection pads is connected to the other end of each of the leads to electrically connect the semiconductor chip and the wiring substrate.

Abstract: A method for forming at least one conductive line intended to receive high-frequency or high-value currents, formed above a given portion of a solid substrate outside of which are formed other elements, including the steps of digging at least one trench in the solid substrate; forming an insulating area in the trench; and forming said conductive line above the insulating area.

Abstract: A method of making a semiconductor device comprising: providing a semiconductor substrate having a plurality of discrete devices formed therein, and a plurality of metal layers and support layers, the support layers comprising an uppermost support layer and other support layers, and wherein each metal layer has an associated support layer having at least a portion underlying the metal layer, and wherein the plurality of metal layers includes an uppermost metal layer including a sealing pad having an opening therethrough, and a passivation layer having at least one opening therein exposing a portion of the sealing pad including the opening therethrough, and the uppermost support layer having a portion exposed through the opening in the sealing pad; exposing the uppermost support layer to an etching material through the opening in the sealing pad and etching away the support layers; and sealing the opening in the sealing pad.

Abstract: The invention relates to a method of making an integrated circuit inductor that comprises a silicon substrate and an oxide layer on the silicon substrate. In one aspect, the method comprises depositing an inductive loop on the oxide layer, and making a plurality of apertures in the oxide layer beneath the inductive loop. The method also comprises providing a plurality of bridges adjacent the apertures and provided by portions of the oxide layer between an inner region within the inductive loop and an outer region of the oxide layer without the inductive loop, the inductive loop being supported on the bridges. The method comprises forming a trench in the silicon substrate beneath the bridges, to provide an air gap between the inductive loop and the silicon substrate.

Abstract: A method for forming interlevel dielectric levels in a multilevel interconnect structure formed by a damascene process. The conductive features characteristic of the damascene process are formed in a removable mandrel material for each level of the interconnect structure. In at least one level, a portion of the mandrel material underlying the bond pad is clad on all sides with the metal forming the conductive features to define a support pillar. After all levels of the interconnect structure are formed, the mandrel material surrounding the conductive features is removed to leave air-filled voids that operate as an interlevel dielectric. The support pillar is impermeable to the etchant such that mandrel material and metal inside the support pillar is retained. The support pillar braces the bond pad against vertical mechanical forces applied by, for example, probing or wire bonding and thereby reduces the likelihood of related damage to the interconnect structure.

Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.

Abstract: A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.

Abstract: A method for forming back-end-of-line (BEOL) interconnect structures in disclosed. The method and resulting structure includes etchback for low-k dielectric materials. Specifically, a low dielectric constant material is integrated into a dual or single damascene wiring structure which contains a dielectric material having relatively high dielectric constant (i.e., 4.0 or higher). The damascene structure comprises the higher dielectric constant material immediately adjacent to the metal interconnects, thus benefiting from the mechanical characteristics of these materials, while incorporating the lower dielectric constant material in other areas of the interconnect level.

Abstract: A process for manufacturing a membrane sensor over a silicon substrate, preferably a thermal membrane sensor. A thin layer of silicon carbide or silicon nitride is deposited over an area of porous silicon formed in the surface of the substrate, and then openings that extend as far as the layer of porous silicon are formed in the silicon carbide or silicon nitride layer via a dry etching process. Next, semiconductor structures and conductor path structures are implanted into the upper surface of the membrane layer via lithographic steps, and then the sacrificial layer of porous silicon is removed using a suitable solvent such as ammonia. Thus an empty space that thermally isolates the sensor membrane from the substrate is created beneath the membrane layer.

Abstract: A method to fabricate a silicon-on-nothing device on a silicon substrate is provided. The disclosed silicon-on-nothing device is fabricated on an isolated floating silicon active area, thus completely isolated from the silicon substrate by an air gap. The isolated floating silicon active area is fabricated on a silicon germanium layer with a surrounding isolation trench. A plurality of anchors is then fabricated to anchor the silicon active area to the silicon substrate before selectively etching the silicon germanium layer to form the air gap. Isolation trench fill and planarization complete the formation of the isolated floating silicon active area. The silicon-on-nothing device on the isolated floating silicon active area can be polysilicon gate or metal gate and with or without raised source and drain regions.

Abstract: A semiconductor device according to the present invention includes a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the nonvolatile memory devices includes a word gate formed over a semiconductor layer with a gate insulating layer interposed in between, impurity layers formed in the semiconductor layer, and sidewall-shaped control gates formed along both side surfaces of the word gate. The control gate includes a first control gate and a second control gate which are adjacent to each other. The first control gate is formed on a first insulating layer formed of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The second control gate is formed on a second insulating layer formed of a silicon oxide film.

Abstract: A method of forming a floating structure lifting up from a substrate and a method of manufacturing a field emission device (FED) employing the floating structure are provided. The method of forming a floating structure includes forming an expansion causer layer, which can generate a byproduct from the reacting with a predetermined reactant gas causing volume expansion, on the substrate; forming an object material layer for the floating structure on a resultant stack; forming a hole through which the reactant gas is supplied on a resultant stack; supplying the reactant gas through the hole so that the object material layer partially lifts up from the substrate due to the byproduct generated from the reaction of the expansion causer layer with the reactant gas; and removing the byproduct through the hole so that the portion of the object material layer lifting up from the substrate can be completely separated from the substrate to form the floating structure.

Abstract: Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.

Abstract: Conductive lines, such as co-axial lines, integrated circuitry incorporating such conductive lines, and methods of forming the same are described. In one aspect, a substrate having an outer surface is provided. A masking material is formed over the outer surface and subsequently patterned to form a conductive line pattern. An inner conductive layer is formed within the conductive line pattern, followed by formation of a dielectric layer thereover and an outer conductive layer over the dielectric layer. Preferred implementations include forming the inner conductive layer through electroplating, or alternatively, electroless plating techniques. Other preferred implementations include forming the dielectric layer from suitable polymer materials having desired dielectric properties. A vapor-deposited dielectric layer of Parylene is one such preferred dielectric material.

Abstract: Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.

Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structures are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.

Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the device layer of the SOI wafer, providing a substrate, wherein a pattern has been etched onto the substrate, bonding the SOI wafer and the substrate together, removing the handle layer of the SOI wafer, removing the dielectric layer of the SOI wafer, then performing a structural etch on the device layer of the SOI wafer to define the device.

Abstract: An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through the overlying hard mask. As a result, an air gap may be created having desirable characteristics as a dielectric.

Abstract: In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches are etched in the first and second layer of dielectric in an X and Y-direction respectively. The trenches are filled with a layer of nitride and polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. Openings are created through the thin layer of oxide that align with the points of intersect of the nitride in the trenches in the layers of dielectric. The nitride is removed from the trenches by a wet etch, thereby opening trenches in the layers of dielectric with both sets of trenches being interconnected. The openings in the thin layer of oxide are closed, leaving a network of trenches containing air in the two layers of dielectric.

Abstract: In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.

Abstract: The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating covering. Then, an opening is etched into the insulating covering, and the lower conductive layer is selectively removed. As a result, one the one hand, low-capacitance wiring can be fabricated and, on the other hand, this enables MOS transistors to be programmed in a simple manner.

Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used.

Abstract: A method of manufacturing a semiconductor device which can solve a problem in which a wafer is warped by the influence of thermal contraction of a sealing resin due to a difference in thermal contraction between the wafer and the sealing resin. A second wafer on which electrodes are formed is stacked on a first wafer such that the electrodes of the second wafer are electrically connected to the electrodes formed on the first wafer, a portion between the first wafer and the second wafer is sealed with a resin, the second wafer and the sealing resin are half cut to expose the conductive posts from the sealing resin, conductive bumps for performing electric connection to an external circuit are formed on the exposed conductive posts, and the wafer is diced into independent semiconductor devices.