Semiconductor Islands Formed Upon Insulating Substrate Or Layer (e.g., Mesa Isolation, Etc.) Patents (Class 438/412)
  • Patent number: 9831308
    Abstract: A semiconductor device includes a plurality of substantially vertical semiconductor pillars on a substrate, and a hard mask layer overlying the plurality of semiconductor pillars. A contiguous portion of the hard mask layer connects two or more of the plurality of semiconductor pillars.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 28, 2017
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Zhongshan Hong
  • Patent number: 9607880
    Abstract: A method of manufacturing a silicon-on-insulator (SOI) substrate is provided. The method includes forming an island-shaped insulating layer on a first surface of a first semiconductor substrate in a first region, forming a silicon epitaxial layer on the first surface of the first semiconductor substrate so as to cover the island-shaped insulating layer, forming a trench by etching the silicon epitaxial layer so as to expose the island-shaped insulating layer, and forming a first insulating adhesive layer on the silicon epitaxial layer and the island-shaped insulating layer so as to fill the trench.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: March 28, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Herb He Huang, Clifford I. Drowley
  • Patent number: 9568828
    Abstract: A liquid immersion member including first and second members forming the immersion space; first member having a first lower surface disposed at a portion of the optical member surrounding, second member having a second upper surface opposite to the first lower surface via a gap and a second lower surface opposing the substrate and second member disposed at a portion of exposure light optical path surrounding; driving apparatus to move the second member with respect to the first; controlling the driving apparatus so the second member's operation in the substrate first operation movement is between exposure termination and start of a first and second shot regions differently from a second member's operation in the substrate second movement period which is between exposure termination and start of a third and fourth shot regions; first and second shot regions are in the same row contrary to third and fourth shot regions.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: February 14, 2017
    Assignee: NIKON CORPORATION
    Inventor: Shinji Sato
  • Patent number: 9507265
    Abstract: An exposure apparatus includes a liquid immersion member including a first member and a second member and configured to form a liquid immersion space of the liquid, a driving apparatus configured to move the second member with respect to the first member; and a controller configured to control the driving apparatus. The controller controls the driving apparatus so that a first operation of the second member in a first movement period of the substrate between exposure termination of a first shot region and exposure start of a second shot region is different from a second operation of the second member in a second movement period of the substrate between exposure termination of a third shot region and exposure start of a fourth shot region, the first and second shot regions being included in the same row, the third and fourth shot regions being arranged in different rows.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: November 29, 2016
    Assignee: NIKON CORPORATION
    Inventor: Shinji Sato
  • Patent number: 9318874
    Abstract: A semiconductor device includes a semiconductor layer stacked on a substrate, a stripe-shaped ridge formed on a surface of the semiconductor layer, and electrode formed on an upper surface of the ridge and a protective film disposed on each side of the ridge. The electrode includes a flat portion having a flat surface substantially parallel to the upper surface of the ridge and sloped portions on both sides of the flat portion with each of the sloped portions having a sloped surface that is sloped with respect to the upper surface of the ridge. The protective film covers a region from a side surface of the ridge to the sloped surface of the sloped portion of the electrode.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: April 19, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Atsuo Michiue, Yasuhiro Kawata
  • Patent number: 9293180
    Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: March 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eui-chul Jeong, Sung-hee Lee, Dae-sin Kim, Seung-hwan Kim, Dae-sun Kim, Sua Kim, Dong-soo Woo, Na-ra Kim
  • Patent number: 9177792
    Abstract: A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Tai Chang, Yi-Shan Chen, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9153665
    Abstract: Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. In addition, a gate and a gate dielectric are formed on the sidewalls of each pillar.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: October 6, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien-An Yu, Yuan-Sung Chang, Yi-Fong Lin, Chin-Piao Chang, Chih-Huang Wu, Wen-Chieh Wang
  • Patent number: 9105792
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: August 11, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9035419
    Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Woo Oh, Dae-Sin Kim, Young-Kwan Park, Keun-Ho Lee, Seon-Young Lee
  • Patent number: 8999764
    Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell
  • Patent number: 8999779
    Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sebastian Naczas, Vamsi Paruchuri, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 8969164
    Abstract: A semiconductor structure comprises a substrate, a gate stack, a base area, and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate. A supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate; a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure. A stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure. Correspondingly, a method is provided for manufacturing such a semiconductor structure, which inhibits the short channel effect, reduces the parasitic capacitance and leakage current, and enhances the steepness of the source/drain region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 3, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8956942
    Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed, thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: February 17, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Prasanna Khare
  • Patent number: 8952454
    Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Shimizu, Junichi Yamashita, Takuichiro Shitomi
  • Publication number: 20140370686
    Abstract: Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventors: Paul D. Hurwitz, Robert L. Zwingman
  • Patent number: 8802990
    Abstract: A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Zhengwen Li, Kevin S. Petrarca, Roger A. Quon, Carl J. Radens, Brian C. Sapp
  • Patent number: 8785291
    Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiaojun Yu, Brian J. Greene, Yue Liang
  • Patent number: 8779469
    Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Greene, Yue Liang, Xiaojun Yu
  • Publication number: 20140097522
    Abstract: The present disclosure provides multi-junction solar cell structures and fabrication methods thereof that improve electrical testing capability and reduce chip failure rates. In the present invention a special masking pattern is used in the layout such that all or some of the epitaxial layers are etched away in the corner areas of each solar cell. Consequently, the semiconductor substrate or one or more of the interconnections between junctions become accessible from the top (the side facing the sun) to make electrical connections.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 10, 2014
    Applicant: Solar Junction Corporation
    Inventors: ONUR FIDANER, DANIEL DERKACS, PAUL F. LAMARCHE, MICHAEL W. WIEMER
  • Patent number: 8685805
    Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chang-Woo Oh
  • Patent number: 8664653
    Abstract: Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo
  • Patent number: 8535996
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 17, 2013
    Assignee: SOITEC
    Inventors: Mohamad Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karin Landry, Carlos Mazure
  • Patent number: 8525227
    Abstract: There is provided a semiconductor device including a base substrate; a semiconductor layer formed on the base substrate and having a mesa protrusion including a receiving groove; a source electrode and a drain electrode disposed to be spaced apart from each other on the semiconductor layer, the source electrode having a source leg and the drain electrode having a drain leg; and a gate electrode insulated from the source electrode and the drain electrode and having a recess part received into the receiving groove. The mesa protrusion has a superlattice structure including at least one trench at an interface between the mesa protrusion and the source electrode and between the mesa protrusion and the drain electrode, respectively, and the source leg and the drain leg are received in the trench.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 3, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Chul Jeon, Ki Yeol Park, Young Hwan Park, Jung Hee Lee
  • Patent number: 8507332
    Abstract: A method for manufacturing components on a mixed substrate. The method comprises the following steps: providing a substrate of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer between a supporting substrate and a thin layer, forming in this substrate a plurality of trenches opening out at a free surface of the thin layer and extending over a depth such that each trench passes through the thin layer and the buried oxide layer, these primary trenches delimiting at least one island of the SeOI substrate, forming a mask inside the primary trenches and as a layer covering the areas of the free surface of the thin layer located outside the islands, proceeding with heat treatment for dissolving the buried oxide layer present at the island, so as to reduce the thickness thereof.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: August 13, 2013
    Assignee: Soitec
    Inventors: Gregory Riou, Didier Landru
  • Patent number: 8501577
    Abstract: A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 6, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Jiantao Bian, Zengfeng Di, Miao Zhang
  • Patent number: 8486802
    Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-hoon Jang, Young-bae Yoon, Hee-soo Kang, Young-seop Rah, Jeong-dong Choe
  • Patent number: 8481354
    Abstract: Methods for creating a microelectromechanical systems (MEMS) device using a single double, silicon-on-insulator (SOI) wafer. The double SOI wafer includes at least a base layer of silicon, a first layer of silicon, and a second layer of silicon, the layers of silicon are separated by an oxide layer. A stationary electrode with rigid support beams is formed into the second layer of silicon. A proof mass and at least one spring are formed into the first layer of silicon. The proof mass is separated from the stationary electrode by a first gap and the proof mass is separated from the base silicon layer by a second gap.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: July 9, 2013
    Assignee: Honeywell International Inc.
    Inventor: Lianzhong Yu
  • Patent number: 8460984
    Abstract: FIN-FET ICs with adjustable FIN-FET channel widths are formed from a semiconductor layer (42). Fins (36) may be etched from the layer (42) and then some (46) locally shortened or the layer (42) may be locally thinned and then fins (46) of different fin heights etched therefrom. Either way provides fins (46) and FIN-FETs (40) with different channel widths W on the same substrate (24). Fin heights (H) are preferably shortened by implanting selected ions (A, B, C, etc.) through a mask (90, 90?, 94, 94?, 97, 97?) to locally enhance the etch rate of the layer (42) or some of the fins (36). The implant(s) (A, B, C, etc.) is desirably annealed and then differentially etched. This thins part(s) (42-i) of the layer (42) from which the fins (46) are then etched or shortens some of the fins (46) already etched from the layer (42). For silicon, germanium is a suitable implant ion.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: June 11, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Jeremy Wahl, Kingsuk Maitra
  • Patent number: 8420467
    Abstract: A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Nobutoshi Aoki
  • Patent number: 8389995
    Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: March 5, 2013
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S.)
    Inventors: Guillaume Saint-Girons, Ludovic Largeau, Gilles Patriarche, Philippe Regreny, Guy Hollinger
  • Patent number: 8236665
    Abstract: A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Bog Kim
  • Patent number: 8217423
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R Holt, Renee T Mo, Kern Rim
  • Patent number: 8084310
    Abstract: Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: December 27, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Bencherki Mebarki, Li Yan Miao, Christopher Dennis Bencher, Jen Shu
  • Patent number: 8067740
    Abstract: An image sensor includes a semiconductor substrate; first pixels laid out above cavities provided within the semiconductor substrate, the first pixels converting thermal energy generated by incident light into an electric signal; supporting parts connected between the first pixels and the semiconductor substrate, the supporting parts supporting the first pixels above the cavities; and second pixels fixedly provided on the semiconductor substrate without via the cavities, wherein a plurality of the first pixels and a plurality of the second pixels are laid out two-dimensionally to form a pixel region, and each of the second pixels is adjacent to the first pixels.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: November 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keita Sasaki, Hideyuki Funaki, Hiroto Honda, Ikuo Fujiwara, Koichi Ishii, Hitoshi Yagi
  • Patent number: 8058136
    Abstract: A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 15, 2011
    Assignee: Inotera Memories, Inc.
    Inventors: Chien-Hsun Chen, Tzung Han Lee, Chung-Lin Huang
  • Patent number: 8048728
    Abstract: A manufacturing method is provided which achieves an SOI substrate with a large area and can improve productivity of manufacture of a display device using the SOI substrate. A plurality of single-crystalline semiconductor layers are bonded to a substrate having an insulating surface, and a circuit including a transistor is formed using the single-crystalline semiconductor layers, so that a display device is manufactured. Single-crystalline semiconductor layers separated from a single-crystalline semiconductor substrate are applied to the plurality of single-crystalline semiconductor layers. Each of the single-crystalline semiconductor layers has a size corresponding to one display panel (panel size).
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8043933
    Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: October 25, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Chien-Teh Kao, Xinliang Lu, Zhenbin Ge, Mei Chang, Hoiman Raymond Hung, Nitin Ingle
  • Patent number: 8033011
    Abstract: A method for mounting a thinned semiconductor wafer on a carrier substrate for further processing is disclosed. The method consists of a series of steps, which is based on providing a frame with a double-side tape to mount the thinned wafer on the carrier substrate. The frame is used to support the double-side tape and can be designed to fit the conventional production line for holding, picking and transferring wafers. The carrier substrate can be a sapphire substrate, a quartz substrate or other substrates that can sustain further processing, such as thermal treatments and/or chemical etchings. The method of the present invention not only prevents possible damages to the highly brittle chip after wafer thinning, but also fits the conventional production line for processing semiconductor wafers.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: October 11, 2011
    Assignee: Win Semiconductors Corp.
    Inventors: Jason Chou, Chang-Hwang Hua, Ping-Wei Chen, Sen Yang
  • Patent number: 7951659
    Abstract: A method of forming a microelectronic device comprising, on a same support: at least one semi-conductor zone strained according to a first strain, and at least one semi-conductor zone strained according to a second strain, different to the first strain, comprising: the formation of semi-conductor zones above a pre-strained layer, then trenches extending through the thickness of the pre-strained layer, the dimensions and the layout of the semi-conductor zones as a function of the layout and the dimensions of the trenches being so as to obtain semi-conductor zones having a strain of the same type as that of the pre-strained layer and semi-conductor zones having a strain of a different type to that of the pre-strained layer.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: May 31, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Younes Lamrani, Jean-Charles Barbe, Marek Kostrzewa
  • Patent number: 7927962
    Abstract: A method of manufacturing a semiconductor device and a semiconductor device manufactured by the method, the method comprising: (a) forming a buffer layer on a semiconductor substrate; (b) patterning the buffer layer in a first direction to form buffer layer patterns having lateral surfaces and being spaced from each other at predetermined intervals; (c) forming a semiconductor epitaxial layer on and between the buffer layer patterns; (d) forming a first trench in the semiconductor epitaxial layer in a second direction perpendicular to the first direction to expose lateral surfaces of the buffer layer patterns; (e) selectively removing the buffer layer patterns exposed by the first trench to form spaces; (f) forming buried insulation films in the spaces formed by removal of the buffer layer patterns, a portion of semiconductor epitaxial layer being disposed between the buried insulation films; (g) removing a portion of the semiconductor epitaxial layer disposed between the buried insulation films to form a sec
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: April 19, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Soo Yoo
  • Patent number: 7923345
    Abstract: A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: April 12, 2011
    Assignee: NXP B.V.
    Inventors: Jan Sonsky, Wibo D. Van Noort
  • Patent number: 7902007
    Abstract: Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: March 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-joo Kim, Tae-hee Lee, Dae-kil Cha, Yoon-dong Park
  • Patent number: 7897477
    Abstract: Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: March 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Chun Wang, Tzu-Hsuan Hsu
  • Patent number: 7892948
    Abstract: The present invention provides a method for manufacturing an SOI wafer in which a thickness of an SOI layer is increased by growing an epitaxial layer on the SOI layer of the SOI wafer having an oxide film and the SOI layer formed on a base wafer, wherein the epitaxial growth is performed in such a manner that a reflectivity of a surface of the SOI wafer on which the epitaxial layer is grown in a wavelength region of a heating light at the start of the epitaxial growth falls within the range of 30% to 80%. As a result, in the method for manufacturing the SOI wafer in which a thickness of the SOI layer is increased by growing the epitaxial layer on the SOI layer of the SOI wafer having the oxide film and the SOI layer formed on the base wafer, a method for manufacturing a high-quality SOI wafer with less slip dislocation and others is provided.
    Type: Grant
    Filed: January 15, 2007
    Date of Patent: February 22, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Shinichiro Yagi
  • Patent number: 7863117
    Abstract: An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with a active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mahmoud A. Mousa, Christopher S. Putnam
  • Patent number: 7855116
    Abstract: In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: December 21, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Kiyotoshi
  • Patent number: 7851277
    Abstract: An object is to reduce the adverse influence which a portion of a gate insulating layer where the thickness has decreased, that is, a step portion, has on semiconductor element characteristics so that the reliability of the semiconductor element is improved. A semiconductor layer is formed over an insulating surface; a side surface of the semiconductor layer is oxidized using wet oxidation to form a first insulating layer; a second insulating layer is formed over the semiconductor layer and the first insulating layer; and a gate electrode is formed over the semiconductor layer and the first insulating layer with the second insulating layer interposed therebetween.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: December 14, 2010
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Patent number: 7829407
    Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: November 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 7749817
    Abstract: A system and method for producing a single-crystal germanium layer on a dielectric layer by producing a germanium-on-insulator assembly between the surface portions of the third material. The choice of location for these surface portions therefore makes it possible to define the zone on which it is desired to produce the germanium-on-insulator layer. The wafer may be freely chosen between a pure single-crystal silicon wafer and a silicon-on-insulator wafer. A single-crystal germanium first layer is produced on the surface portion of the silicon. The RPCVD produces a partially crystalline germanium first layer. The layer thus comprises various nuclei that have crystallized in possibly different lattices. After carrying out a recrystallization annealing operation, which makes the layer monocrystalline by recrystallizing the various nuclei in one and the same crystal lattice. Thus, the layers are continuous with the single-crystal silicon lattice.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: July 6, 2010
    Assignee: STMicroelectronics (Crolles) SAS
    Inventors: Olivier Kermarec, Yves Campidelli