Abstract: A semiconductor device array having silicon device islands isolated from the substrate by an insulator. High array density is achieved by forming source and drain interconnects in the space between the islands. Also disclosed are processes for forming and programming such arrays.

Abstract: An inbred corn line, designated LH172Bt810, is disclosed. The invention relates to the seeds of inbred corn line LH172Bt810, to the plants of inbred corn line LH172Bt810 and to methods for producing a corn plant produced by crossing the inbred line LH172Bt810 with itself or another corn line. The invention further relates to hybrid corn seeds and plants produced by crossing the inbred line LH172Bt810 with another corn line.

Abstract: A method for rounding corners of a silicon substrate, in accordance with the present invention, includes forming a plateau on a silicon substrate having corners at edges of the plateau. A mask is formed on a top surface of the plateau, which is recessed back from vertical edges of the plateau to provide exposed horizontal portions. Fluorine or Argon dopants are implanted at the corners and on the exposed portions, and the substrate is oxidized such that the corners become rounded providing a gradual transition at the edges of the plateau.

Abstract: A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers wherein a first doped and activated polysilicon layer (either n-type and-p-type) is patterned on a substrate. An isolation material layer is formed abutting the first doped and activated polysilicon layer in the corners formed at the junction between the first doped and activated polysilicon layer and the substrate. A second doped and activated polysilicon layer (either n-type or p-type) is applied over the first doped and activated polysilicon layer and the isolation material layer. The second doped and activated polysilicon layer is planarized to the height of the first doped and activated polysilicon layer. The first and second doped and activated polysilicon layers are etched to substantially bifurcate the first and second doped and activated polysilicon layers. Further processing steps known in the art are utilized to complete the MOS device.

Abstract: The formation of a fully-depleted, ESD protected CMOS device is described. The device is formed on an SOI or SIMOX substrate, over which an oxide pad is grown to a thickness of between 10 and 30 nm. Appropriate ions are implanted into the oxide to adjust the threshold voltage of an ESD transistor. A portion of the top silicon film is thinned to a thickness no greater than 50 nm. The fully depleted CMOS devices are fabricated onto the thinned top silicon film, while the ESD devices are fabricated onto the top silicon film having the original thickness.

Abstract: In a method for producing a semiconductor substrate completed through a bonding process for joining a semiconductor wafer to a support substrate by performing heat treatment thereto in a state in which the semiconductor wafer is closely joined to the support substrate, the method according to the present invention includes the following steps, i.e., a depositing process for depositing a poly-crystal semiconductor which covers all areas of a surface to be bonded on the surface of the semiconductor wafer; a heat treatment process for performing the heat treatment to the semiconductor wafer provided after the depositing process, during a predetermined time under a temperature equal to or higher than the heat treatment temperature at the bonding process; and a polishing process for flattening the surface of the poly-crystal semiconductor provided after the heat treatment process. After the above processes were performed in order, the bonding process is performed after the polishing process.

Abstract: A semiconductor device which can prevent formation of a parasitic transistor and degradation in its threshold voltage is obtained. In the semiconductor device, a sidewall insulating film the width of which is increased toward its lower portion is formed on a side wall of a semiconductor layer, and a gate electrode layer is formed such that it extends on the semiconductor layer and the sidewall insulating film.

Abstract: A semiconductor structure having a first conductive trace fabricated adjacent to a second conductive trace over an insulating layer. A dielectric material is located over and between the first and second conductive traces. A borderless contact extends through the dielectric material to contact the first conductive trace. An air gap is formed in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. The first portion of the air gap is offset toward the second trace.

Abstract: This invention discloses a MOSFET power device supported on a substrate. The MOSFET power device includes a plurality polysilicon-with-oxide-cap segments disposed over a gate oxide layer including two outermost segments and a plurality of inner segments include a plurality of gate oxide-plug openings. Each of the inner segments functions as agate and the two outer most segments function as a field plate and an equal potential ring separated by a termination oxide-plug gap and the gate oxide-plug openings and the termination oxide-plug gap having an aspect ratio greater or equal to 0.5. The MOSFET power device further includes a plurality of MOSFET transistor cells for each of the gates, wherein each transistor cells further includes a source region, a body region, the transistor cells further having a common drain disposed at a bottom surface of the substrate.

Abstract: In a method manufacturing a semiconductor device, a semiconductor layer having a device forming region is formed on substrate. Next, a region except for the device forming region is changed into an insulator. In this case, a conducting path is left across the semiconductor device to electrically connect the semiconductor device with an adjacent semiconductor device. Subsequently, the device forming region is etched on the condition that the conducting path is left. Finally, the conducting path is disrupted after the etching process. Thus, the semiconductor device and the adjacent semiconductor device are left in an electrical contact via the conducting path during the etching process. Consequently, the uniformity of the etching between the semiconductor devices is largely improved.

Abstract: Fabrication of atomic step-free regions on a substrate surface is achieved by first forming a two-dimensional pattern on the substrate. The pattern is preferably a grating comprising an array of troughs or mesas which are separated from one another by a plurality of ridges or trenches. Any atomic steps on the flat top surfaces of the troughs or mesas are moved into barrier regions formed by the ridge or trench sidewalls during a high temperature annealing or deposition step, thereby leaving the flat surfaces of the troughs and mesas free of atomic steps. Structures having step-free regions large enough to accommodate micron sized devices having nanometer sized features are thereby formed.

Abstract: Methods of forming semiconductor-on-insulator field effect transistors include the steps of forming an insulated trench containing a semiconductor region therein and an insulating region mesa at a bottom of the trench, so that the semiconductor region has relatively thick regions adjacent the sidewalls of the trench and has a relatively thin region above the mesa. Dopants can then be added to the thick regions to form low resistance source and drain regions on opposite sides of the thin region which acts as the channel region. Because the channel region is thin, low junction capacitance can also be achieved. An insulated gate electrode can also be formed on the face of the semiconductor region, above the channel region, and then source and drain contacts can be formed to the source and drain regions to complete the device.

Abstract: The present invention is a technique for producing planar silicon on insulator MOS transistors, where the channel regions are created in an underlying single crystal silicon wafer, and where the source-drain extension regions are created by damascene patterning a thin film of amorphous silicon deposited on a layer of oxide deposited on the silicon wafer.

Abstract: After formation of a sandwich over a substrate of a layer of silicon dioxide (3) followed by a layer of silicon (1) having a pad oxide (7) thereon and a patterned silicon nitride layer (9) over the pad oxide, the unmasked portion of the pad oxide and silicon are removed to provide mesas of silicon with silicon nitride thereover and possibly removal of some of the buried oxide layer. A flowable insulator (15), preferably silsesquioxane (H.sub.x SiO.sub.1.5, where x.ltoreq.1, depending upon the level of polymerization) in a contaminant-free, high purity solvent which is later removed during an annealing step, is placed over the exposed surface such that it fills the voids between the mesas of silicon with silicon nitride thereon and extends over the nitride. The flowable insulator, due to its flowability, provides a generally planar surface. The flowable insulator is etched back and a cap oxide (17) is optionally deposited over the etched back insulator layer.

Abstract: The present invention discloses a method for manufacturing 3-D transistors with high electrostatic discharge (ESD) reliability. Pad oxide layers are on a silicon substrate and a thick field oxide is on the silicon substrate between the pad oxide layer. An oxygen amorphized region is formed in the substrate by using an ion implantation having oxygen ions as dopants and the field oxide as a hard mask. A high-temperature thermal annealing is implemented to convert the oxygen amorphized region into an oxygen implant-induced oxide regions. Then, the pad oxide layers and the field oxide are removed to form a field oxide region on the substrate and silicon islands on the oxygen implant-induced oxide regions. A thin gate oxide is deposited on the surface of the substrate and the silicon islands to seal the silicon islands. Finally, PMOSFETs are formed on the silicon islands and bulk NMOSFET buffers are formed on the field oxide region of the substrate.

Abstract: A method for forming a gap in a silicon layer is described. A silicon layer is formed over a substrate. A nitride layer is formed over the silicon layer and an oxide layer is formed over the silicon layer, adjacent to the nitride layer. A portion of the oxide layer is then removed to form an exposed region of the silicon layer. Then an etchant is applied to the exposed region to form an gap of the silicon layer.

Abstract: A semiconductor device and method of manufacture thereof is provided. According to one embodiment, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are removed to expose one or more portions of the substrate within the trench. A plurality of doped polysilicon pillars are formed within the trench. The doped polysilicon pillars include one or more active region pillars formed on the one or more exposed portions of the substrate.

Abstract: A method of making an integrated circuit in semiconductor on insulator material and the circuit which comprises providing a semiconductor on insulator structure having a device layer, preferably silicon, and an electrically insulating layer, the device layer being in contact with one surface of the electrically insulating layer. An underlayer is provided which contacts the opposing surface of the electrically insulating layer. The structure is then patterned and trenches are etched to expose a surface of the underlying layer and to form mesas extending from the underlying layer. Ions can now optionally be implanted into selected regions of the underlying layer. A dielectric is provided between the mesas extending to or into the substrate and fabrication of the integrated circuit is then completed. The dielectric can be a thermal oxide at the exposed surface with a dielectric over the thermal oxide.

Abstract: A semiconductor on insulator structure (50) includes a silicon layer (30) formed on an insulating substrate (20). The silicon layer (30) is partitioned into two sections (32, 34) which are electrically isolated from each other. The thickness of the silicon layer (30) in a first section (32) of the silicon layer (30) is adjusted independently from the thickness of the silicon layer (30) in a second section (34) of the silicon layer (30). Independently adjusting the thickness of the silicon layer (30) allows optimizing the performance of semiconductor devices (60, 80) fabricated in the first and second sections (32, 34) of the semiconductor on insulator structure (50).

Abstract: A method for fabricating a GeSi/Si/SiO.sub.2 heterostructure comprises the steps of: (a) providing a monocrystalline Si substrate; (b) defining a GeSi region within the Si substrate while leaving a Si cap overlying the GeSi region, the Si cap being an integral part of the monocrystalline substrate; and (c) oxidizing part of the Si cap to thereby produce the GeSi/Si/SiO.sub.2 heterostructure.

Abstract: A semiconductor device and a method for fabricating the same, wherein a thick side wall oxide film or polysilicon film is formed on the edge portion of the second silicon substrate. At the side wall of the oxide film or polysilicon film, the thickness of an active semiconductor substrate at its edge portion increases, thereby obtaining an increased threshold voltage at the edge portion. That is, the formation of the side wall oxide film is carried out to prevent a gate oxide film of the semiconductor device from being directly formed on each side wall of the active silicon substrate. As a result, it is possible to prevent a degradation in electrical characteristic due to a degradation in threshold voltage caused by a reduced thickness of the active semiconductor substrate at its edge portion.

Abstract: An inbred maize line, designated PH05W, the plants and seeds of inbred maize line PH05W, methods for producing a maize plant produced by crossing the inbred line PH05W with itself or with another maize plant, and hybrid maize seeds and plants produced by crossing the inbred line PH05W with another maize line or plant.

Abstract: A semiconductor device having a silicon-on-insulator structure, and a method for fabricating the semiconductor device, wherein a thick silicon oxide film is formed on each side wall of an active silicon substrate, thereby obtaining an increased threshold voltage at the edge of the active silicon substrate. The semiconductor device includes a first silicon substrate, a first silicon oxide film formed over the first silicon substrate, a second silicon substrate on the first silicon oxide film, second silicon oxide films, respectively disposed on opposite side walls of the second silicon substrate, a gate oxide film formed on the second silicon substrate, a gate electrode formed over the gate oxide film, and source/drain impurity diffusion regions, respectively formed in portions of the second silicon substrate disposed at both sides of the gate electrode.