Semiconductor Islands Formed Upon Insulating Substrate Or Layer (e.g., Mesa Isolation, Etc.) Patents (Class 438/412)
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Patent number: 6797547Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.Type: GrantFiled: October 3, 2003Date of Patent: September 28, 2004Assignee: Texas Instruments IncorporatedInventors: Sheldon D. Haynie, Steven L. Merchant, Sameer P. Pendharkar, Vladimir Bolkhovsky
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Patent number: 6784074Abstract: A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.Type: GrantFiled: June 6, 2003Date of Patent: August 31, 2004Assignee: NSC-Nanosemiconductor GmbHInventors: Vitaly Shchukin, Nikolai Ledentsov
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Patent number: 6774006Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.Type: GrantFiled: December 18, 2002Date of Patent: August 10, 2004Assignee: Micron Technology, Inc.Inventor: Alan R. Reinberg
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Patent number: 6767773Abstract: An operating semiconductor layer is formed in such a manner that amorphous silicon layer is formed to be shaped so that it has a wide region and a narrow region and the narrow region is connected to the wide region at a position asymmetric to the wide region, and the amorphous silicon layer is crystallized by scanning a CW laser beam from the wide region toward the narrow region in a state that a polycrystalline silicon layer as a heat-retaining layer encloses the narrow region from a side face through the silicon oxide layer.Type: GrantFiled: August 29, 2002Date of Patent: July 27, 2004Assignee: Fujitsu LimitedInventors: Yasuyuki Sano, Akito Hara, Michiko Takei, Nobuo Sasaki
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Publication number: 20040108546Abstract: A MOS transistor suitable for microscopic applications and a fabrication method thereof are disclosed. The fabrication method includes forming a trench by selectively etching a semiconductor substrate; forming a channel region consisting of a silicon layer with a predetermined width in the bottom of the trench and forming a gate oxide film on the channel region; forming a SiGe film on the gate oxide film and within the trench and burying the trench; forming a gate groove with a predetermined width to expose the gate oxide film by selectively etching the SiGe film; and forming a gate electrode by forming a silicon layer on the exposed gate oxide film such that the gate groove is buried.Type: ApplicationFiled: December 3, 2003Publication date: June 10, 2004Applicant: Anam Semiconductor Inc.Inventor: Kwan-Ju Koh
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Patent number: 6703285Abstract: An object of the present invention is to provide a method for manufacturing a capacitor structure that makes it possible to control the accumulation of electric charges on a top electrode film as a factor that brings about electrostatic breakdown in the insulating film of an MIM capacitor structure, and to provide a method for manufacturing capacitor elements with a low percent defective. The first technique is characterized in that a top electrode film is formed on a substrate after a grounded conductive member is brought into contact with a bottom electrode film or insulating film, and the conductive member is then separated from the bottom electrode film or insulating film. The second technique is characterized in that a top electrode film is formed on a substrate in a state in which a member kept at a negative potential is disposed around the substrate.Type: GrantFiled: September 26, 2002Date of Patent: March 9, 2004Assignee: Oki Electric Industry Co., Ltd.Inventors: Yoshikazu Arakawa, Keiichi Hashimoto
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Patent number: 6686647Abstract: Indium phosphor (InP) Gunn diode that realizes improvements in thermal characteristics, yield factor of good products and easy assembly to planar circuits is provided. In a Gunn diode of the present invention, contact layers are interposing an active layer. An anode electrode and a cathode electrode are formed on the uppermost contact layer. A high resistance region around the cathode electrode is formed at least in an uppermost contact layer by ion implantation using the cathode and anode electrode as a mask. A region under the cathode electrode functions as a Gunn diode and a region under the anode electrode function as a conductive path from the anode electrode to the active layer. These two regions are defined by the high resistance region.Type: GrantFiled: June 12, 2001Date of Patent: February 3, 2004Assignee: New Japan Radio Co., Ltd.,Inventors: Chikao Kimura, Atsushi Nakagawa
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Publication number: 20030228724Abstract: Disclosed is a method of manufacturing a semiconductor device. A plurality of device separation regions are formed in an SOI layer of an SOI substrate, a desired impurity is implanted into a body portion of an Si active layer region, and therereafter a gate electrode is formed with a gate insulation film therebetween. Thereafter, an impurity is implanted into the Si active layer region to form extension portions of source/drain portions, and then an impurity different in polarity from the impurity in the source/drain portions is halo-implanted to form a reverse-characteristic layer. In the halo implantation, the range of projection is set to reach the inside of a buried oxide film. With this configuration, in a fully depleted SOI-MOSFET or the like provided with a thin film SOI layer, it is made possible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance and to secure a sufficient driving capability.Type: ApplicationFiled: March 18, 2003Publication date: December 11, 2003Inventor: Kazuhide Koyama
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Patent number: 6656806Abstract: A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed. The SOI structure includes a BOX layer of insulation material formed on a silicon substrate; an SOI layer formed on the BOX layer; a well formed within a device isolation area of the SOI layer such that its lower surface is in contact with the BOX layer; a field oxide film formed on a surface side within the well; a gate line formed across an active area on the SOI layer and a portion on the field oxide film; an N+ type source/drain area formed within the active area along both sides of the gate line to contact its lower surface with the BOX layer; an insulation layer formed on such resultant structure; and an opening part that is formed within the insulation layer.Type: GrantFiled: March 11, 2002Date of Patent: December 2, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Min-Su Kim
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Patent number: 6627515Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.Type: GrantFiled: December 13, 2002Date of Patent: September 30, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Horng-Huei Tseng, Jyh-Chyurn Guo, Chenming Hu, Da-Chi Lin
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Patent number: 6620654Abstract: A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers includes forming a first doped and activated polysilicon area (either n-type or p-type) on a substrate. An isolation material layer is formed abutting the first activated area. A second doped and activated polysilicon area of opposite conductivity type from the first activated area is formed adjacent to the isolation material layer. The second activated opposite area has a height that does not exceed that of the first doped and activated polysilicon layer. Further processing may be effected to complete the MOS device. The method of the present invention eliminates ion implantation and annealing steps used in previously existing methods.Type: GrantFiled: August 28, 2001Date of Patent: September 16, 2003Assignee: Micron Technology, Inc.Inventor: Salman Akram
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Patent number: 6583024Abstract: A silicon wafer having a thick, high-resistivity epitaxially grown layer and a method of depositing a thick, high-resistivity epitaxial layer upon a silicon substrate, such method accomplished by: a) providing a silicon wafer substrate and b) depositing a substantially oxygen free, high-resistivity epitaxial layer, with a thickness of at least 50 &mgr;m, upon the surface of the silicon wafer. The silicon wafer substrate may then, optionally, be removed from the epitaxial layer.Type: GrantFiled: December 6, 2001Date of Patent: June 24, 2003Assignee: SEH America, Inc.Inventors: Oleg V. Kononchuk, Sergei V. Koveshnikov, Zbigniew J. Radzimski, Neil A. Weaver
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Patent number: 6576494Abstract: A microelectronic device package and method for manufacture. In one embodiment, the device package can include a support member having a first surface, a second surface facing opposite the first surface and a cavity extending through the support member from the first surface to the second surface. A microelectronic device is disposed in the cavity and is supported in the cavity with a removable retention member. The microelectronic device is electrically coupled to the support member and is partially surrounded with an encapsulating material. The removable retention member is then removed to expose a surface of the microelectronic device. Accordingly, the package can have a low profile because the encapsulating material does not surround one of the microelectronic device surfaces. In one embodiment, a heat conductive material can be engaged with the exposed surface of the microelectronic device to increase the rate at which heat is transferred away from the microelectronic device.Type: GrantFiled: June 28, 2000Date of Patent: June 10, 2003Assignee: Micron Technology, Inc.Inventor: Warren M. Farnworth
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Patent number: 6570217Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.Type: GrantFiled: April 22, 1999Date of Patent: May 27, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Toshihiko Iinuma, Kiyotaka Miyano
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Patent number: 6551899Abstract: A method for fabricating nonvolatile memory devices includes forming one or more polyislands, each having a conductive layer and a dielectric layer, on a dielectric layer of a substrate before the creation of control gates on the memory device. In particular, the polyislands may be formed by providing a substrate with a dielectric layer on a surface of the substrate, and forming one or more bar-like structures on the substrate. Each of the bar-like structures includes a conductive layer and a dielectric layer. The bar-like structures are then patterned with compositions having various etching sensitivities for the components of the bar-like structures, to thereby create one or more polyislands before the addition of a second conductive layer over the resulting structure.Type: GrantFiled: June 14, 2002Date of Patent: April 22, 2003Inventors: Hsu-Sheng Yu, Chun-Hung Lee
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Patent number: 6541348Abstract: Gettering layers are formed near element isolation insulating films in an active layer on a buried oxide film. The gettering layers trap mainly heavy metals diffused from the element isolation insulating films into the active layer.Type: GrantFiled: February 4, 2002Date of Patent: April 1, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Hiroomi Nakajima
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Patent number: 6537866Abstract: A method for forming insulating spacers for separating conducting layers in semiconductor wafer fabrication. The spacers are formed by removing portions of a protective photoresist layer through photolithography, and then through etching of exposed portions of the insulating layer. The spacers allow for fabrication of components that are smaller in size than are obtainable through conventional photolithography methods.Type: GrantFiled: October 18, 2000Date of Patent: March 25, 2003Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Jeffrey A. Shields, Tuan D. Pham, Jusuke Ogura, Bharath Rangarajan, Simon Siu-Sing Chan
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Patent number: 6531376Abstract: A method of making a semiconductor device (10) having a low permittivity region (24) includes forming a first layer (30/42) over a surface of a trench (20), and etching through an opening (70) in the first layer that is smaller than a width (W2) of the trench to remove a first material (38) from the trench. A second material (44) is deposited to plug the opening to seal an air pocket (40) in the trench. The low permittivity region features air pockets with a high volume because the small size of the opening allows the second material to plug the trench without accumulating significantly in the trench.Type: GrantFiled: April 17, 2002Date of Patent: March 11, 2003Assignee: Semiconductor Components Industries LLCInventors: Weizhong Cai, Chandrasekhara Sudhama, Yujing Wu, Keith Kamekona
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Patent number: 6514832Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.Type: GrantFiled: March 31, 2000Date of Patent: February 4, 2003Assignee: New Japan Radio Co., Ltd.Inventors: Atsushi Nakagawa, Kenichi Watanabe
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Patent number: 6509626Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.Type: GrantFiled: May 23, 2001Date of Patent: January 21, 2003Inventor: Alan R. Reinberg
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Patent number: 6503799Abstract: There is provided a method of forming an element isolation structure that can maintain its element isolation capability even with the progress of miniaturization of semiconductor elements. Through thermal processing in a nitrogen atmosphere at 900° C., a non single-crystal silicon film (80) is crystallized into single-crystal form by epitaxial growth on the main surface of a substrate, thereby to form an epitaxial silicon film (85). The epitaxial silicon film (85) is then planarized by CMP to expose the upper surface of an element isolation insulating film (50). This completes the element isolation insulating film (50) having a two-level protruding shape.Type: GrantFiled: November 26, 2001Date of Patent: January 7, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuyuki Horita, Takashi Kuroi, Shuuichi Ueno
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Patent number: 6503812Abstract: The semiconductor device comprises a semiconductor substrate (SB) having locally at least one zone (ZL) terminating in the surface of the substrate and entirely bordered, along its lateral edges and its bottom, by an insulating material so as to be completely isolated from the rest of the substrate. The horizontal isolating layer may be a layer of constant thickness or a crenellated layer.Type: GrantFiled: January 11, 2002Date of Patent: January 7, 2003Assignee: STMicroelectronics S. A.Inventors: Olivier Menut, Guillaume Bouche, Herve Jaouen
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Patent number: 6500710Abstract: On a SIMOX substrate having a plurality of STI layers and first conductivity type semiconductor layers disposed in the row direction, a stacked-layer structure SS is formed on a gate dielectric film formed on the first conductivity type semiconductor layer, the structure SS being made of a first polysilicon film, a second gate dielectric film and a second polysilicon film. Second conductivity type source and drain regions are formed in the first conductivity type semiconductor layer on both sides of the structure SS. In a plurality of source regions adjacent in the column direction between the stacked-layer structures SS, a common source line CSL is formed which is made of second conductivity type source region connecting semiconductor regions, source regions and conductive films formed on these semiconductor and source regions.Type: GrantFiled: June 22, 2001Date of Patent: December 31, 2002Assignee: Fujitsu LimitedInventor: Shinichi Nakagawa
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Patent number: 6489193Abstract: A novel process for isolating devices on a semiconductor substrate is disclosed. An isolation layer is first formed over the semiconductor substrate and patterned into at least two isolation mesas on the substrate. Next, a blanket semiconductor layer is formed over the substrate with a thickness sufficient to cover the isolation mesas. The semiconductor layer is subjected to planarization until the isolation mesas are exposed, thus resulting in a semiconductor region between the two isolation mesas to serve as an active region for semiconductor devices.Type: GrantFiled: January 9, 2002Date of Patent: December 3, 2002Assignee: Silicon Integrated Systems Corp.Inventors: Lung Chen, Teng-Feng Wang, Zen-Long Yang, Shih-Hui Chang, Yung-Shin Wang
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Patent number: 6472290Abstract: An electrical isolation method for silicon microelectromechanical systems provides trenches filled with insulation layers that support released silicon structures. The insulation layer that fills the trenches passes through the middle portion of the electrodes, anchors the electrodes to the silicon substrate and supports the electrode. The insulation layers do not attach the electrode to the sidewalls of the substrate, thereby forming an electrode having an “island” shape. Such an electrode is spaced far apart from the adjacent walls of the silicon substrate providing a small parasitic capacitance for the resulting structure. The isolation method is consistent with fabricating a complex structure or a structure with a complicated electrode arrangement. Furthermore, the structure and the electrode are separated from the silicon substrate in a single release step.Type: GrantFiled: January 9, 2001Date of Patent: October 29, 2002Assignee: Chromux Technologies, Inc.Inventors: Dong-il Cho, Sangwoo Lee, Sangjun Park, Sangchul Lee
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Publication number: 20020132444Abstract: The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.Type: ApplicationFiled: May 20, 2002Publication date: September 19, 2002Applicant: Matsushita Electronics CorporationInventors: Manabu Yanagihara, Tsuyoshi Tanaka, Akihisa Sugimura
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Publication number: 20020123205Abstract: In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.Type: ApplicationFiled: April 16, 2002Publication date: September 5, 2002Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Takuji Matsumoto
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Publication number: 20020102813Abstract: A method for manufacturing a semiconductor device with a shallow channel on a silicon-on-insulator substrate is disclosed. The method uses a dielectric layer as a mask, an oxygen implantation and a heating process to form a silicon dioxide layer within a silicon-on-insulator substrate before forming a gate electrode on the silicon-on-insulator substrate. That is, the junction depth of the channel is reduced. First of all, a silicon-on-insulator substrate having a silicon layer and an insulating layer is provided, wherein the silicon layer is separated by the insulating layer. Secondly, a first dielectric layer is deposited on the silicon layer. Thirdly, a gate region pattern is transferred into the first dielectric layer to form a trench and expose the silicon layer. Then, oxygen molecules are implanted into the silicon layer, and the silicon-on-insulator substrate is heated to form a silicon dioxide layer therein. Next, a second dielectric layer is deposited and the trench is filled with the same.Type: ApplicationFiled: January 31, 2001Publication date: August 1, 2002Inventors: Der-Yuan Wu, Chih-Cheng Liu
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Patent number: 6420310Abstract: The present invention provides a thermal transfer image receiving sheet comprising a substrate sheet and a dye receptor layer disposed on at least one surface of the substrate sheet, wherein the dye receptor layer comprises polycarbonate resin of a random copolymer having a main chain which comprises, as essential units, an unit 1 represented by the following formula 1 and an unit 2 represented by the following formula 2, or a polycarbonate resin of a homopolymer which comprises the unit 2, an amount ratio of the unit 1 being not more than 70 mol %, the polycarbonate resin having a Tg of not less than 125° C.Type: GrantFiled: April 30, 2001Date of Patent: July 16, 2002Assignee: Dai Nippon Printing Co., Ltd.Inventors: Hitoshi Saito, Shino Takao, Hirofumi Tomita
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Patent number: 6399460Abstract: A method of manufacturing a semiconductor device including the steps of (a) forming an element isolation insulating film in an element isolation region of a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order, and (b) forming, in an element formation region of the SOI substrate, a transistor having a channel formation region selectively disposed in a main surface of the semiconductor layer, a gate structure on the channel formation region, and source/drain regions disposed is the main surface of the semiconductor layer and the adjacent channel formation region. The method also includes the step of (c) selectively growing, after said steps (a) and (b), a polycrystal semiconductor layer on the source/drain regions in a self-aligned manner, which is prescribed by the element isolation insulating film and the gate structure.Type: GrantFiled: October 5, 2000Date of Patent: June 4, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Yamaguchi, Hidekazu Yamamoto
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Patent number: 6387713Abstract: To offer a microstructure fabrication apparatus capable of realizing MEMS and a Rugate Filter excellent in performance characteristics by patterning a thick functional material film in high aspect ratio with a simple and practical manufacturing method. A Si layer is employed for a mask pattern. The advantages of the Si layer are withstood a process conducted at high temperature for forming a PZT layer, which is the functional material layer, patterned in high aspect ratio, and achieves excellent process consistency for the whole manufacturing processes of the microfabrication. A trench or a gap is formed with the mask pattern deeper than the desired PZT layer. The PZT layer, or functional material layer (films) is formed on the whole surface including the bottom of the concave part of the mask pattern. The PZT layer deposited on the mask pattern is removed with the mask pattern itself, and selectively remains the pattern of the PZT layer, thereby obtaining a pattern of the desired functional material layer.Type: GrantFiled: June 4, 2001Date of Patent: May 14, 2002Assignee: Sony CorporationInventor: Masaki Hara
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Patent number: 6368936Abstract: An alignment mark is formed in an SOI substrate comprised of a support substrate, an insulating layer and a semiconductor film by etching through first oxide and nitride films formed on the semiconductor film and etching through the semiconductor film and the insulating layer so that the hole extends to the support substrate. The first oxide film is formed on the semiconductor film and the first nitride film is formed thereover. The first nitride film is etched to expose part of the first oxide film and a well is formed in the semiconductor film by ion implantation in the region where the first nitride film is etched. The alignment mark is then formed by etching through the first nitride film, the first oxide film, the semiconductor film and the insulation layer so that the hole extends to the support substrate. Remaining portions of the first nitride film and the first oxide film are removed and second oxide and nitride films are formed on the semiconductor film.Type: GrantFiled: November 19, 1999Date of Patent: April 9, 2002Assignee: Seiko Instruments Inc.Inventor: Yoshifumi Yoshida
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Publication number: 20020038901Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.Type: ApplicationFiled: March 15, 2001Publication date: April 4, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takashi Kuroi, Syuichi Ueno, Katsuyuki Horita
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Publication number: 20020005562Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing stepType: ApplicationFiled: May 23, 2001Publication date: January 17, 2002Inventors: Jong-Dae Kim, Sang-Gl Kim, Jin-Gun Koo, Dae-Yong Kim
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Publication number: 20020001915Abstract: In a step & scan projection exposure apparatus having a controller for setting for each step driving a step driving profile on the basis of a scan synchronization error, the step driving profile can be set by the exposure region layout, step direction, scan driving profile, and the like. Also, the step driving profile is determined by parameters such as the accelerations and speeds of reticle and wafer stages, the time taken until synchronous scan driving starts after step driving, and the time taken until exposure starts after the start of synchronous scan driving. A method of maintaining the apparatus by using a network, a semiconductor device manufacturing method, and a semiconductor manufacturing factory are also provided.Type: ApplicationFiled: June 29, 2001Publication date: January 3, 2002Inventor: Satoshi Akimoto
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Patent number: 6335230Abstract: A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers wherein a first doped and activated polysilicon layer (either n-type and p-type) is patterned on a substrate. An isolation material layer is formed abutting the first doped and activated polysilicon layer in the corners formed at the junction between the first doped and activated polysilicon layer and the substrate. A second doped and activated polysilicon layer (either n-type or p-type) is applied over the first doped and activated polysilicon layer and the isolation material layer. The second doped and activated polysilicon layer is planarized to the height of the first doped and activated polysilicon layer. The first and second doped and activated polysilicon layers are etched to substantially bifurcate the first and second doped and activated polysilicon layers. Further processing steps known in the art are utilized to complete the MOS device.Type: GrantFiled: January 4, 2000Date of Patent: January 1, 2002Assignee: Micron Technology, Inc.Inventor: Salman Akram
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Patent number: 6319333Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.Type: GrantFiled: August 7, 1998Date of Patent: November 20, 2001Assignee: Micron Technology, Inc.Inventor: Wendell P. Noble
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Patent number: 6312992Abstract: Thin film transistor and method for fabricating the same, is disclosed, in which a channel width of the thin film transistor is made greater in a narrow area for improving an on/off performance of the thin film transistor, the thin film transistor including a source electrode formed on a substrate, a columnar conductive layer connected to the source electrode, a drain electrode formed on the conductive layer, a gate insulating film formed to cover the conductive layer and the drain electrode, a gate electrode formed on the gate insulating film surrounding the conductive layer, and an insulting film formed between the source electrode and the gate electrode.Type: GrantFiled: September 23, 1998Date of Patent: November 6, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Seok Won Cho
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Publication number: 20010033002Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.Type: ApplicationFiled: May 21, 2001Publication date: October 25, 2001Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maurice H. Norcott, Devendra K. Sadana
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Publication number: 20010034109Abstract: A method of increasing trench density for semiconductor devices such as, for example, trench MOSFETs. Trenches are formed in a substrate with mesas interposed between the trenches. The initial width of the mesas are made less than target width so that a reduction in trench pitch can be realized. After a silicon layer is grown inside the trenches, the width of the mesas is increased to a final width that is two times the thickness of the silicon layer. The thickness of the silicon layer is precalculated so that it is of sufficient thickness to ensure compliance with the target mesa width.Type: ApplicationFiled: May 1, 2001Publication date: October 25, 2001Inventors: Gordon K. Madson, Joelle Sharp
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Patent number: 6303412Abstract: Methods of forming semiconductor-on-insulator field effect transistors include the steps of forming an insulated trench containing a semiconductor region therein and an insulating region mesa at a bottom of the trench, so that the semiconductor region has relatively thick regions adjacent the sidewalls of the trench and has a relatively thin region above the mesa. Dopants can then be added to the thick regions to form low resistance source and drain regions on opposite sides of the thin region which acts as the channel region. Because the channel region is thin, low junction capacitance can also be achieved. An insulated gate electrode can also be formed on the face of the semiconductor region, above the channel region, and then source and drain contacts can be formed to the source and drain regions to complete the device.Type: GrantFiled: April 3, 2000Date of Patent: October 16, 2001Assignee: Samsung Electronics Co., Ltd.Inventor: Kyu-charn Park
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Publication number: 20010016396Abstract: A thin-film resistor has: 1. a resistance layer positioned on a dielectric layer, 2. a protective layer positioned on the resistance layer and having two openings on two ends of the resistance layer, 3. an insulating layer covering the upper and side surfaces of the protective layer, the side surfaces of the resistance layer, and the surface of the dielectric layer, the protective layer having two openings above the two openings of the protective layer, 4. two plugs positioned in the two openings of the insulating layer and the protective layer for electrically connecting to the two ends of the resistance layer, and 5. two conductive layers formed on the insulting layer and positioned on the two plugs, and which are used as two electrical wires for electrically connecting to the two ends of the resistance layer.Type: ApplicationFiled: March 8, 2001Publication date: August 23, 2001Inventor: Jia-Sheng Lee
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Patent number: 6277703Abstract: A method including: forming doped regions on a monocrystalline substrate; growing an epitaxial layer; forming trenches in the epitaxial layer extending to the doped regions; anodizing the doped regions in an electro-galvanic cell to form porous silicon regions; oxidizing the porous silicon regions; removing the oxidized porous silicon regions to form a buried air gap; thermally oxidizing the substrate to grow an oxide region from the walls of the buried air gap and the trenches, until the buried air gap and the trenches themselves are filled.Type: GrantFiled: May 14, 1999Date of Patent: August 21, 2001Assignee: STMicroelectronics S.R.L.Inventors: Gabriele Barlocchi, Flavio Francesco Villa
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Patent number: 6277704Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.Type: GrantFiled: May 24, 2000Date of Patent: August 21, 2001Assignee: Micron Technology, Inc.Inventor: Alan R. Reinberg
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Patent number: 6232229Abstract: A microelectronic device fabricating method includes providing a substrate having a beveled portion and forming a layer of structural material on the beveled portion. Some of the structural material can be removed from the beveled portion by anisotropic etching to form a device feature from the structural material. The device feature can be formed on the beveled portion as with a pair of spaced, adjacent barrier material lines that are substantially void of residual shorting stringers extending therebetween. Structural material can be removed from the beveled portion to form an edge defined feature on a substantially perpendicular edge of the substrate. The beveled portion and perpendicular edge can be part of a mandril. The mandril can be removed from the substrate after forming the edge defined feature.Type: GrantFiled: November 19, 1999Date of Patent: May 15, 2001Assignee: Micron Technology, Inc.Inventor: Alan R. Reinberg
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Patent number: 6229076Abstract: According to the invention, there is provided an inbred corn plant designated 01HGI4. This invention thus relates to the plants, seeds and tissue cultures of the inbred corn plant 01HGI4, and to methods for producing a corn plant produced by crossing the inbred corn plant 01HGI4 with itself or with another corn plant, such as another inbred. This invention further relates to corn seeds and plants produced by crossing the inbred plant 01HGI4 with another corn plant, such as another inbred, and to crosses with related species. This invention further relates to the inbred and hybrid genetic complements of the inbred corn plant 01HGI4, and also to the RFLP and genetic isozyme typing profiles of inbred corn plant 01HGI4.Type: GrantFiled: January 10, 2000Date of Patent: May 8, 2001Assignee: DeKalb Genetics CorporationInventor: Michael A. Hall
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Patent number: 6225168Abstract: Semiconductor devices having a metal gate electrode and a titanium or tantalum nitride gate dielectric barrier layer and processes for fabricating such devices are provided. The use of a metal gate electrode along with a titanium or tantalum nitride gate dielectric barrier layer can, for example, provide a highly reliable semiconductor device having an increased operating speed as compared to conventional transistors.Type: GrantFiled: June 4, 1998Date of Patent: May 1, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, H. Jim Fulford, Charles E. May, Fred Hause, Dim-Lee Kwong
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Patent number: 6215145Abstract: A nonvolatile flash memory array having silicon device islands isolated from the substrate by an insulator. Each island comprises a split-gate transistor with a control gate and floating gate formed in the upper portion of the island, and source, drain and channel regions formed in a lower portion of the island. High array density is achieved by forming source and drain interconnects in the space between the islands. Also disclosed are processes for forming and programming such arrays.Type: GrantFiled: April 6, 1998Date of Patent: April 10, 2001Assignee: Micron Technology, Inc.Inventor: Wendell P. Noble
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Patent number: 6211039Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form de SOI islands.Type: GrantFiled: November 12, 1996Date of Patent: April 3, 2001Assignee: Micron Technology, Inc.Inventor: Wendell P. Noble
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Patent number: 6204145Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.Type: GrantFiled: August 7, 1998Date of Patent: March 20, 2001Assignee: Micron Technology, Inc.Inventor: Wendell P. Noble