Having Air-gap Dielectric (e.g., Groove, Etc.) Patents (Class 438/421)
  • Patent number: 8823155
    Abstract: A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: September 2, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Toshio Nakasaki
  • Patent number: 8822303
    Abstract: A method of fabricating a semiconductor component that including the following steps is provided. A plurality of stacked structures is formed on a substrate. A first dielectric layer is formed to cover the stacked structures, wherein the first dielectric layer has a plurality of overhangs, the overhangs wrap top portions of the stacked structures. A dry conformable etching process is performed to conformably remove the first dielectric layer until a portion of the first dielectric layer located outside of the overhangs is removed. A second dielectric layer is formed on the stacked structures, wherein the second dielectric layer connects the adjacent overhangs to form an air gap between the stacked structures.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: September 2, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Tsu-Chiang Chen, Yu-Mei Liao, Cheng-Kuen Chen
  • Patent number: 8809847
    Abstract: A photoelectric conversion device includes an organic photoelectric conversion layer, and suppresses sensitivity degradation caused by the light irradiation. A photoelectric conversion device 100 is formed by stacking a first electrode layer 104, a photoelectric conversion layer 15 including an organic material, and a second electrode layer 108 on a substrate 101, in which the photoelectric conversion layer 15 has a bulk hetero structure of a P-type organic semiconductor and an N-type organic semiconductor, and a difference between an ionization potential of the P-type organic semiconductor and an apparent ionization potential of the bulk hetero structure is 0.50 eV or less. Accordingly, it is possible to suppress sensitivity degradation caused by the light irradiation.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 19, 2014
    Assignee: FUJIFILM Corporation
    Inventors: Daigo Sawaki, Katsuyuki Yofu
  • Patent number: 8790990
    Abstract: Provided is a silica-based film forming material for formation of air gaps, the material being capable of forming air gaps without employing a CVD method. A silica-based film forming material for formation of air gaps including (a) a certain siloxane polymer, (b) an alkanolamine, and (c) an organic solvent is used when a silica-based film is formed with a spin coating method. According to this silica-based film forming material for formation of air gaps, air gaps with a great degree of opening can be formed even when coated with a spin coating method, without filling the recessed parts.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: July 29, 2014
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventor: Yoshihiro Sawada
  • Publication number: 20140206164
    Abstract: A method includes performing a first planarization step to remove portions of a semiconductor region over isolation regions. The first planarization step has a first selectivity, with the first selectivity being a ratio of a first removal rate of the semiconductor region to a second removal rate of the isolation regions. After the isolation regions are exposed, a second planarization step is performed on the isolation regions and a portion of the semiconductor region between the isolation regions. The second planarization step has a second selectivity lower than the first selectivity, with the second selectivity being a ratio of a third removal rate of the portion of semiconductor region to a fourth removal rate of the isolation regions.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Yin Lin, Wan-Chun Pan, Hsiang-Pi Chang, Teng-Chun Tsai, Chi-Yuan Chen
  • Patent number: 8772941
    Abstract: A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Matthew E. Colburn, Louis C. Hsu, Wai-Kin Li
  • Patent number: 8772126
    Abstract: A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Anton Mauder
  • Patent number: 8772885
    Abstract: The present invention discloses a MEMS sensing device which comprises a substrate, a MEMS device region, a film, an adhesive layer, a cover, at least one opening, and a plurality of leads. The substrate has a first surface and a second surface opposite the first surface. The MEMS device region is on the first surface, and includes a chamber. The film is overlaid on the MEMS device region to seal the chamber as a sealed space. The cover is mounted on the MEMS device region and adhered by the adhesive layer. The opening is on the cover or the adhesive layer, allowing the pressure of the air outside the device to pressure the film. The leads are electrically connected to the MEMS device region, and extend to the second surface.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: July 8, 2014
    Assignee: PixArt Imaging Incorporation, R.O.C.
    Inventors: Chuan-Wei Wang, Ming-Han Tsai
  • Patent number: 8772153
    Abstract: In accordance with an embodiment, a semiconductor device includes a substrate, a line-and-space structure, a first film and a second film. The line-and-space structure includes line patterns arranged on the substrate parallel to one another at a predetermined distance. The first film is formed on side surfaces and bottom surfaces of the line patterns by an insulating film material. The second film is formed on the line-and-space structure across a space between the line patterns by a material showing low wettability to the first film. Space between the line patterns includes an air gap in which at least a bottom surface of the first film is totally exposed.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Furuhashi, Miyoko Shimada, Ichiro Mizushima, Shinichi Nakao
  • Patent number: 8765573
    Abstract: A method of forming air gaps between adjacent raised features on a substrate includes forming a carbon-containing material in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming a silicon-containing film over the carbon-containing material using a flowable deposition process, where the silicon-containing film fills an upper region between the adjacent raised features and extends over the adjacent raised features. The method also includes curing the carbon-containing material and the silicon-containing material at an elevated temperature for a period of time to form the air gaps between the adjacent raised features.
    Type: Grant
    Filed: September 10, 2011
    Date of Patent: July 1, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Nitin Ingle
  • Patent number: 8753955
    Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Sik Lee, Jang-Hyun You, Jee-Hoon Han, Young-Woo Park, Sung-Hoi Hur, Sang-Ick Joo
  • Patent number: 8748286
    Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Na, Young-Woo Park, Dong-Hwa Kwak, Tae-Yong Kim, Jee-Hoon Han, Jang-Hyun You, Dong-Sik Lee, Su-Jin Park
  • Patent number: 8736019
    Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 27, 2014
    Assignee: Icemos Technology Ltd.
    Inventors: Samuel Anderson, Koon Chong So
  • Patent number: 8729523
    Abstract: Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Federico Pio
  • Patent number: 8716101
    Abstract: A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chandra, Ronald G. Filippi, Wai-Kin Li, Ping-Chuan Wang, Chih-Chao Yang
  • Patent number: 8716829
    Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 6, 2014
    Assignee: Icemos Technology Ltd.
    Inventors: Samuel Anderson, Koon Chong So
  • Publication number: 20140120692
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 1, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Vinod R. Purayath, Hiroyuki Kinoshita, Tuan Pham
  • Patent number: 8703576
    Abstract: Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Paul Chang, Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight
  • Patent number: 8697535
    Abstract: A thin film transistor substrate includes a substrate, a gate electrode on the substrate, an active layer on or below the gate electrode (the active layer at least partially overlapping the gate electrode) including a first active region and a second active region, the first active region and the second active region facing each other and extending beyond the gate electrode, a source electrode electrically connected to the first active region and a drain electrode electrically connected to the second active region, wherein the active layer includes a recess region which is at least partially recessed from a surface of the active layer facing the gate electrode, and the recess region includes a portion extending between the first active region and the second active region.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae-Jin Kim, Sang-Jae Yeo, Dae-Sung Choi
  • Patent number: 8692318
    Abstract: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: April 8, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Chin-Te Kuo, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8686394
    Abstract: Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective material extends across an interface of the carbon-containing material and the oxygen-sensitive material, and does not extend to a top region of the carbon-containing material. Second protective material is formed across the top of the carbon-containing material, with the second protective material having a common composition to the first protective material. The second protective material is etched to expose an upper surface of the carbon-containing material. Some embodiments include semiconductor constructions, memory arrays and methods of forming memory arrays.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Cinzia Perrone
  • Patent number: 8685809
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Publication number: 20140077333
    Abstract: A semiconductor device includes a substrate, a conductive pattern (e.g., a contact plug) on an active region of the substrate and having respective first and second sidewalls on opposite first and second sides of the conductive pattern, and first and second conductive lines (e.g., bit lines) on the substrate on respective ones of the first and second sides of conductive pattern and separated from the respective first and second sidewalls by asymmetric first and second air spaces.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 20, 2014
    Inventor: Nak-jin Son
  • Patent number: 8659115
    Abstract: A method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material is provided. Specifically, a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating is provided.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Qinghuang Lin
  • Patent number: 8652931
    Abstract: The present invention is related to the trench manufacturing field in semiconductor, especially a manufacturing method of STI structure with difference depth which is apply to the imaging sensor including forming a dielectric layer with different thickness on the substrate which includes a first region and a second region, then forming a first type trench in the thick dielectric layer and a second type trench in the thin dielectric layer, and etching the substrate of the first region and the substrate of the second region, and thus form a first STI and a second STI with different depth which are located in the substrate of the first region and the second region respectively.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: February 18, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Fei Luo
  • Publication number: 20140042516
    Abstract: The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The semiconductor memory device includes a semiconductor substrate in which isolation regions and active regions are defined, gate lines formed on the semiconductor substrate in a direction crossing the isolation regions, a capping layer configured to define air gaps positioned higher than an upper surface of the semiconductor substrate in the isolation regions.
    Type: Application
    Filed: December 14, 2012
    Publication date: February 13, 2014
    Applicant: SK HYNIX INC.
    Inventors: Tae Kyung KIM, Jung Myoung SHIM, Myung Kyu AHN, Sung Soon KIM, Woo Duck JUNG
  • Patent number: 8629035
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming an isolation trench in a substrate, and forming an amorphous layer on a sidewall surface of the isolation trench. The method further includes forming a sacrificial layer in the isolation trench via the amorphous layer, and forming an air gap layer on the sacrificial layer. The method further includes forming an air gap in the isolation trench under the air gap layer by removing the sacrificial layer after forming the air gap layer.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Patent number: 8623742
    Abstract: A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: January 7, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Matthias Kessler, Thomas Feudel
  • Patent number: 8614145
    Abstract: A method is provided for establishing through substrate vias (TSVs) within a substrate. The method includes: forming at least one recess in a front-side of a wafer; filling, at least partially, the at least one recess with a sacrificial material from the front-side of the wafer; thinning the wafer from a back-side to reveal the at least one recess at least partially filled with the sacrificial material; removing from the back-side of the wafer the sacrificial material from the at least one recess; and filling the at least one recess from the back-side of the wafer with a conductive material to provide the at least one through substrate via.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: December 24, 2013
    Assignee: Sematech, Inc.
    Inventor: Klaus Hummler
  • Patent number: 8609507
    Abstract: A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae Kyung Kim, Min Sik Jang, Sung Deok Kim
  • Patent number: 8603889
    Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, James S. Dunn, David L. Harame, Anthony K. Stamper
  • Patent number: 8603890
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: December 10, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, George Matamis, Eli Harari, Hiroyuki Kinoshita, Tuan Pham
  • Publication number: 20130307044
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. A blocking layer can be introduced to inhibit the formation of materials in the air gaps during subsequent process steps. The blocking layer may result in selective air gap formation or varying dimension of air gaps at cell areas relative to select gate areas in the memory. The blocking layer may result in a smaller vertical dimension for air gaps formed in the isolation regions at select gate areas relative to cell areas. The blocking layer may inhibit formation of air gaps at the select gate areas in other examples. Selective etching, implanting and different isolation materials may be used to selectively define air gaps.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Inventors: Hiroyuki Kinoshita, Ming Tian, Daisuke Maekawa, Naoki Watakabe, Seiji Shimabukuro, Hiroaki Iuchi, Hitomi Nakajima
  • Patent number: 8586447
    Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 19, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
  • Patent number: 8580647
    Abstract: A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin
  • Publication number: 20130292793
    Abstract: An integrated circuit may include a semiconductor die having a trench formed in a surface of the semiconductor die. One or more circuit components may be formed on the surface of the semiconductor die. The trench can extend into the semiconductor die next to at least one circuit component. The trench may surround the circuit component partially or wholly. The trench may be filled with a material having a lower bulk modulus than the semiconductor die in which the trench is formed.
    Type: Application
    Filed: January 14, 2013
    Publication date: November 7, 2013
    Applicant: ANALOG DEVICES TECHNOLOGY
    Inventors: Patrick F. M. POUCHER, Padraig L. FITZGERALD, John Jude O'DONNELL, Oliver J. KIERSE, Denis M. O'CONNOR
  • Patent number: 8575000
    Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: November 5, 2013
    Assignee: SanDisk Technologies, Inc.
    Inventors: Vinod R. Purayath, James K. Kai, Jayavel Pachamuthu, Jarrett Jun Liang, George Matamis
  • Patent number: 8569839
    Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Morii, Yoshitaka Otsu, Kazuma Onishi, Tetsuya Nitta, Tatsuya Shiromoto, Shigeo Tokumitsu
  • Patent number: 8563421
    Abstract: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Bon-young Koo, Ki-hyun Hwang
  • Patent number: 8551839
    Abstract: Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: October 8, 2013
    Assignee: SanDisk Technologies Inc.
    Inventor: Masaaki Higashitani
  • Patent number: 8546239
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: October 1, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Eli Harari, Tuan Pham, Yupin Fong, Vinod Robert Purayath
  • Patent number: 8546909
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: October 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Noda, Hiroyuki Kutsukake, Mitsuhiro Noguchi
  • Patent number: 8541284
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hwang Sim
  • Patent number: 8541316
    Abstract: In a method of forming a dense contact-hole pattern in a semiconductor device, the method uses a self-align double patterning technique including forming a square or triangular lattice dot pattern on double layers of mask materials, forming first holes in the upper mask material and second holes wider than the first holes in the lower mask material by double patterning, additionally forming an insulating layer to a thickness such that the first holes are closed such that voids are left in the second holes, and transferring the shape of the voids to a base layer.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: September 24, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 8524569
    Abstract: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Kang, Jung-Won Lee, Bo-Un Yoon, Kun-Tack Lee
  • Patent number: 8518794
    Abstract: Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: August 27, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Woojin Chang, Hae Cheon Kim
  • Patent number: 8519491
    Abstract: The present invention discloses a MEMS sensing device which comprises a substrate, a MEMS device region, a film, an adhesive layer, a cover, at least one opening, and a plurality of leads. The substrate has a first surface and a second surface opposite the first surface. The MEMS device region is on the first surface, and includes a chamber. The film is overlaid on the MEMS device region to seal the chamber as a sealed space. The cover is mounted on the MEMS device region and adhered by the adhesive layer. The opening is on the cover or the adhesive layer, allowing the pressure of the air outside the device to pressure the film. The leads are electrically connected to the MEMS device region, and extend to the second surface.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: August 27, 2013
    Assignee: Pixart Imaging Incorporation, R.O.C.
    Inventors: Chuan-Wei Wang, Ming-Han Tsai
  • Publication number: 20130207122
    Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Patent number: 8497183
    Abstract: A method of making a device. The method comprises providing a first layer including a first material on a surface of a substrate, removing a portion of the first layer and a corresponding portion of the substrate to form an opening in the first layer and a recessed portion in the surface of the substrate, and supplying a liquid mixture to the opening and the recessed portion. The liquid mixture includes a first component having a first chemical affinity to the first material and a second component having a second chemical affinity to the first material, which is smaller than the first chemical affinity. The method also includes removing the second component and forming a second layer including the first component. The second layer covers the recessed portion and adheres to an edge portion of the first layer, such that the second layer and the recessed portion define a cavity.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: July 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Hsiang Hsiang Ko, Hung Jui Chang, Yi Ming Chen, Hsien-Wei Lin
  • Patent number: 8491799
    Abstract: A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Ki Jung