Combined With Formation Of Recessed Oxide By Localized Oxidation Patents (Class 438/425)
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Publication number: 20110101452Abstract: A trench-gate semiconductor device configuration is provided which is suitable for incorporation in integrated circuits, together with methods for its manufacture. A self-aligned drain region (12a) is provided below the device trench (18). The manufacturing methods include etching an initial trench into a semiconductor body (8), and annealing so as to cause migration of material such that a shallower trench with a cavity (36) below it are formed. The drain region is then formed in the cavity.Type: ApplicationFiled: May 20, 2009Publication date: May 5, 2011Applicant: NXP B.V.Inventors: Jan Sonsky, Eero Saarnilehto
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Patent number: 7935609Abstract: A method is provided for fabricating a semiconductor device and more particularly to a method of manufacturing a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The method includes removing a substrate from an SOI wafer and selectively removing a buried oxide layer formed as a layer between the SOI wafer and active regions of a device. The method further comprises selectively removing isolation oxide formed between the active regions, and replacing the removed buried oxide layer and the isolation oxide with radiation hardened insulators.Type: GrantFiled: August 6, 2008Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: John M. Aitken, Ethan H. Cannon
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Patent number: 7932182Abstract: A potassium hydroxide (KOH) etch process can produce deep high aspect ratio trenches in (110) oriented silicon substrates. The trenches, however, are perpendicular to the (111) direction of the silicon substrate's crystal lattice. The trenches are used to produce thermally isolating areas and through the wafer electrical connections. These structures can be produced in a cost effective manner because of the nearly ideal capabilities of the KOH etch process when it is applied to appropriate materials at appropriate orientations.Type: GrantFiled: August 19, 2005Date of Patent: April 26, 2011Assignee: Honeywell International Inc.Inventors: Yong-Fa A. Wang, Richard A. Davis, Larry A. Rehn
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Patent number: 7915137Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.Type: GrantFiled: April 30, 2008Date of Patent: March 29, 2011Assignee: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Patent number: 7892929Abstract: A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.Type: GrantFiled: July 15, 2008Date of Patent: February 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai, Jeffrey Junhao Xu
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Patent number: 7883956Abstract: Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bonding a handle wafer to the STI and SOI layer to form an intermediate structure. The intermediate structure may have a single layer including at least one STI region and at least one SOI region therein disposed between the damaged substrate and the handle wafer. The method may also include cleaving the hydrogen implanted substrate and removing any residual substrate to expose a surface of the at least one STI region and a surface of the at least one SOI region. The exposed surface of the at least one STI region forms an isolation region and the exposed surface of the at least one SOI region forms an active region, which are coplanar to each other.Type: GrantFiled: February 15, 2008Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventor: Huilong Zhu
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Patent number: 7867834Abstract: A manufacturing method of a semiconductor device according to an embodiment includes: forming a trench for a device isolation area and a semiconductor projection with a first width by etching a semiconductor substrate; forming an oxide film on the trench and the semiconductor projections; forming an insulating layer on the oxide film; exposing the upper surface of the semiconductor projection by polishing the insulating layer and the oxide film; forming a gate insulating layer at a lower region of the semiconductor projection; and etching the insulating layer and the oxide film on the substrate.Type: GrantFiled: July 18, 2007Date of Patent: January 11, 2011Assignee: Dongbu Hitek Co., Ltd.Inventors: Eun Soo Jeong, Jea Hee Kim
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Patent number: 7858489Abstract: A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor substrate such that compressive stress is applied in a channel length direction of a PMOS transistor by oxidizing the buffer layer; removing portions of the insulation layer and thereby forming an isolation layer; and forming the PMOS transistor on the PMOS region of the semiconductor substrate.Type: GrantFiled: May 9, 2008Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventor: Jun Ki Kim
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Patent number: 7855117Abstract: In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An oxide layer may be formed on a second area of the substrate while preventing or reducing an oxidation of the nitride layer by a radical oxidation process in which oxygen radicals react with the second area of the substrate and the blocking layer in the first area of the substrate. The nitride layer may ensure sufficient charge trapping sites and may have a uniform thickness without oxidation thereof in the radical oxidation process.Type: GrantFiled: October 31, 2006Date of Patent: December 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Jun Jang, Ho-Min Son, Woong Lee, Yong-Woo Hyung, Jung-Geun Jee
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Publication number: 20100295131Abstract: A buried insulating layer is buried at a position lower than a surface of a semiconductor substrate, and a cap insulating layer, which is made of a material different from the buried insulating layer, is formed on the buried insulating layer not to protrude into a shoulder portion of a step between the semiconductor substrate and the buried insulating layer.Type: ApplicationFiled: March 16, 2010Publication date: November 25, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kentaro Eda
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Patent number: 7838443Abstract: The invention concerns a method for minimizing “corner” effects in shallow silicon oxide trenches, by densifying the silicon oxide layer after it has been deposited in the trenches. Said densification is preferably carried out by irradiating the layer under luminous radiation with weak wavelength.Type: GrantFiled: June 29, 2007Date of Patent: November 23, 2010Inventors: Patrick Schiavone, Frédéric Gaillard
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Patent number: 7838370Abstract: A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein.Type: GrantFiled: December 27, 2007Date of Patent: November 23, 2010Assignee: Texas Instruments IncorporatedInventors: Narendra Singh Mehta, Wayne Anthony Bather, Ajith Varghese
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Patent number: 7795106Abstract: A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.Type: GrantFiled: October 11, 2007Date of Patent: September 14, 2010Assignees: Tokyo Electron LimitedInventors: Tadahiro Ohmi, Shigetoshi Sugawa, Katsuyuki Sekine, Yuji Saito
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Patent number: 7790567Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.Type: GrantFiled: May 30, 2008Date of Patent: September 7, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: O-Kyun Kwon, Dong-Woo Suh, Jung-Hyung Pyo, Gyung-Ock Kim
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Patent number: 7772084Abstract: A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.Type: GrantFiled: January 4, 2008Date of Patent: August 10, 2010Inventors: Roberto Bez, Alessandro Grossi
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Patent number: 7763523Abstract: A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern.Type: GrantFiled: March 10, 2008Date of Patent: July 27, 2010Assignee: Hynix Semiconductor Inc.Inventors: Sang Tae Ahn, Ja Chun Ku, Eun Jeong Kim
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Publication number: 20100181639Abstract: A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices.Type: ApplicationFiled: January 19, 2009Publication date: July 22, 2010Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wei-Tsung Huang, Pi-Kuang Chuang, Shih-Ming Chen, Hsiao-Ying Yang
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Patent number: 7759204Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.Type: GrantFiled: March 21, 2008Date of Patent: July 20, 2010Assignee: Third Dimension Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
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Publication number: 20100155881Abstract: A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation may be a LOCOS isolation. The shape of a substrate transition region between the levels may be tunably controlled. The shallow trench isolation may reduce the bird's beak effect.Type: ApplicationFiled: December 23, 2008Publication date: June 24, 2010Inventors: Roberto Colombo, Luca Di Piazza
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Patent number: 7736991Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.Type: GrantFiled: December 28, 2006Date of Patent: June 15, 2010Assignee: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee
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Publication number: 20100140714Abstract: Electronic elements (44, 44?, 44?) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62?, 62?) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36?) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65?, 65?) in the composite dielectric region (62, 62?, 62?) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78?, 78?) in the composite dielectric region (62, 62?, 62?). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65?, 65?) and silicon oxide for the dielectric material (78, 78?, 78?).Type: ApplicationFiled: December 4, 2008Publication date: June 10, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xiaowei Ren, Wayne R. Burger, Colin Kerr, Mark A. Bennett
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Patent number: 7718505Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.Type: GrantFiled: June 22, 2007Date of Patent: May 18, 2010Assignee: Infineon Technologies Austria AGInventors: Nicola Vannucci, Hubert Maier
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Patent number: 7713827Abstract: Disclosed herein is a method of making a semiconductor device. According to the method, a flowable oxide (FOX) is deposited over a semiconductor substrate, and a local active region is exposed to grow an active region, by a silicon epitaxial growth (SEG) method, to prevent generation of a void when a device isolation structure is formed by a Shallow Trench Isolation (STI) method, and to prevent formation of stress between the semiconductor substrate and the FOX.Type: GrantFiled: November 5, 2007Date of Patent: May 11, 2010Assignee: Hynix Semiconductor Inc.Inventor: Yeong Eui Hong
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Patent number: 7704855Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.Type: GrantFiled: October 29, 2007Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Charles William Koburger, III, James Albert Slinkman
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Publication number: 20100096721Abstract: A semiconductor device production method according to the present invention includes the steps of: forming a LOCOS oxide film in a surface of a silicon layer by a LOCOS method; forming an impurity region in the silicon layer by introducing an impurity into the silicon layer; and sequentially removing parts of the LOCOS oxide film and the silicon layer to form a trench for isolation of the impurity region after the formation of the LOCOS oxide film and the impurity region.Type: ApplicationFiled: October 21, 2009Publication date: April 22, 2010Applicant: ROHM CO., LTDInventor: Bungo Tanaka
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Patent number: 7696061Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.Type: GrantFiled: September 26, 2007Date of Patent: April 13, 2010Assignee: NEC Electronics CorporationInventor: Hitoshi Ninomiya
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Publication number: 20100084735Abstract: A method for forming a seal ring is disclosed. First, a substrate including a MEMS region, a logic region and a seal ring region is provided. Second, a trench is formed in the MEMS region and multiple recesses are formed in the seal ring region. An oxide fills the trench and the recesses. Later, a MOS is form in the logic region and a dielectric layer is formed on the substrate. Then, an etching procedure is carried out to partially remove the dielectric layer and simultaneously remove the oxide in the multiple recesses completely to form a seal ring space. Afterwards, a metal fills the seal ring space to from the seal ring.Type: ApplicationFiled: October 8, 2008Publication date: April 8, 2010Inventor: Chin-Sheng Yang
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Patent number: 7691721Abstract: Provided is a method for manufacturing a flash memory device, in which an oxidation process is carried out on the disclosed top surface of a semiconductor substrate to form a surface oxide film in the form of bird's beak with an appropriate width before conducting an etching process for trench. Thus, the present invention prevents the effect of thinning tunnel oxide film while reducing a critical dimension of an active region. And, it is possible to assure a normal cell operation by the Fowler-Nordheim (FN) tunneling effect owing to preventing the thinning tunnel oxide film.Type: GrantFiled: June 6, 2005Date of Patent: April 6, 2010Assignee: Hynix Semiconductor Inc.Inventor: Cha Deok Dong
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Patent number: 7687370Abstract: A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a part of the barrier layer and at least a part of the pad oxide layer are etched through the at least one opening resulting in a trench pad oxide layer. Etching of the trench pad oxide layer stops substantially at a top surface of the substrate within the isolation trench. An oxide layer is grown by diffusion on at least the top surface of the substrate corresponding to the at least one isolation trench. The method further includes etching the oxide layer and at least a portion of the substrate to form at least one isolation trench opening.Type: GrantFiled: January 27, 2006Date of Patent: March 30, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Toni D. Van Gompel, John J. Hackenberg, Rode R. Mora, Suresh Venkatesan
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Patent number: 7682929Abstract: A method of forming an integrated circuit device structure having a design rule of less than 0.13 micron. The method includes providing a substrate and forming a pad oxide layer overlying the substrate. The method includes forming a nitride layer overlying the pad oxide layer and patterning the nitride layer and pad oxide layer. A trench structure is formed within a thickness of the substrate using the patterned nitride layer and pad oxide layer as hard mask. The method forms a first thickness of liner oxide within the trench structure using at least thermal oxidation of an exposed region of the trench structure to cover the trench structure. Such thermal oxidation causes a rounding region near corners of the trench structure. The method selectively removes the thickness of liner oxide within the trench structure. The method forms a second thickness of liner oxide within the trench structure using at least thermal oxidation to cover the trench structure.Type: GrantFiled: September 28, 2006Date of Patent: March 23, 2010Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Liu Chi-Kang, Xin Wang, Ze Ki Li
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Patent number: 7682928Abstract: There is provided a method of forming an isolation layer which prevents a failure from occurring depending on a difference in the area of the isolation layer during a planarization process of the isolation layer having a shallow trench isolation (STI) structure. The present invention implements a uniform isolation layer by forming a chemical mechanical polishing (CMP) stop layer on an isolation layer having a relatively large region and performing a planarization process using the CMP stop layer.Type: GrantFiled: December 21, 2006Date of Patent: March 23, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Myung Il Kang
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Patent number: 7670895Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.Type: GrantFiled: April 24, 2006Date of Patent: March 2, 2010Assignee: Freescale Semiconductor, IncInventors: Toni D. Van Gompel, Peter J. Beckage, Mohamad M. Jahanbani, Michael D. Turner
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Publication number: 20100038744Abstract: Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a high-temperature anneal of the silicon substrate to form a buried oxide layer. The method also includes performing an etch to deepen the narrow trench to reach the buried oxide layer. The method further includes depositing a filling material to form a top filling layer in the narrow trench.Type: ApplicationFiled: August 15, 2008Publication date: February 18, 2010Applicant: QUALCOMM INCORPORATEDInventors: Xia Li, Ming-Chu King
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Patent number: 7659159Abstract: In a method of fabricating a flash memory device, a semiconductor substrate includes a tunnel insulating layer and a charge storage layer formed in an active region and a trench formed in an isolation region. A first insulating layer is formed to fill a part of the trench. A second insulating layer is formed on the first insulating layer so that the trench is filled. The first and second insulating layers are removed such that the first and second insulating layers remain on sidewalls of the charge storage layer and on a part of the trench. A third insulating layer is formed on the first and second insulating layers so that a space defined by the charge storage layer is filled. The third insulating layer is removed so that a height of the third insulating layer is lowered.Type: GrantFiled: May 24, 2007Date of Patent: February 9, 2010Assignee: Hynix Semiconductor Inc.Inventor: Sung Hoon Lee
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Publication number: 20100025741Abstract: The present invention discloses a method of fabricating a semiconductor memory device including forming sequentially a gate insulating layer and a first conductive pattern on a semiconductor substrate; forming a protective layer on surfaces of the first conductive pattern and the gate insulating layer; performing an etching process to form a trench, the etching process being performed such that the protective layer remains on side walls of the first conductive pattern to form a protective pattern; forming an isolation layer in the trench; etching the isolation layer; removing the protective pattern above a surface of the isolation layer; and forming sequentially a dielectric layer and a second conductive layer on surfaces of the isolation layer, the protective pattern and the first conductive pattern.Type: ApplicationFiled: March 18, 2009Publication date: February 4, 2010Applicant: HYNIX SEMICONDUCTOR INCInventor: Tae Un Youn
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Publication number: 20100019322Abstract: A semiconductor device and method is provided that has a stress component for increased device performance. The method integrates a stress material into a trench used typically for an isolation structure. The method includes forming an isolation trench through a SOI layer and an underlying BOX layer. The method further includes filling the isolation trench with stress material having characteristics different than the BOX layer.Type: ApplicationFiled: July 23, 2008Publication date: January 28, 2010Applicant: International Business Machines CorporationInventors: Xiangdong Chen, Haining S. Yang
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Patent number: 7648921Abstract: A method of forming a dielectric layer is provided. A first dielectric layer is formed on a substrate having metal layers formed thereon. The first dielectric layer includes overhangs in the spaces between two neighboring metal layers and voids under the overhangs. The first dielectric layer is partially removed to cut off the overhangs and expose the voids and therefore openings are formed. A second dielectric layer is formed on the dielectric layer to fill up the opening.Type: GrantFiled: September 22, 2006Date of Patent: January 19, 2010Assignee: MACRONIX International Co., Ltd.Inventors: Hsu-Sheng Yu, Shing-Ann Lo, Ta-Hung Yang
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Patent number: 7648886Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.Type: GrantFiled: January 14, 2003Date of Patent: January 19, 2010Assignee: Globalfoundries Inc.Inventors: Minh-Van Ngo, Qi Xiang, Paul R. Besser, Eric N. Paton, Ming-Ren Lin
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Publication number: 20100006973Abstract: A semiconductor device with STIs separating HOT regions is described. Processes for eliminating voids due to misalignments in boundary region STIs are described.Type: ApplicationFiled: March 12, 2009Publication date: January 14, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yusuke KOHYAMA
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Patent number: 7642139Abstract: A production method for a semiconductor device, including the steps of: forming a semiconductor layer of the first conductivity on the semiconductor substrate; forming a trench in the semiconductor layer, the trench penetrating through the semiconductor layer to reach the semiconductor substrate; filling a filling material in a predetermined bottom portion of the trench, so that a filling material portion is provided in the bottom portion of the trench up to a predetermined upper surface position which is shallower than an interface between the semiconductor substrate and the semiconductor layer; and, after the filling step, introducing an impurity of the second conductivity into a portion of the semiconductor layer exposed to an interior side wall of the trench.Type: GrantFiled: December 24, 2004Date of Patent: January 5, 2010Assignee: Rohm Co., Ltd.Inventor: Masaru Takaishi
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Patent number: 7642171Abstract: A method of annealing a substrate comprising a trench containing a dielectric material, the method including annealing the substrate at a first temperature of about 200° C. to about 800° C. in a first atmosphere comprising an oxygen containing gas, and annealing the substrate at a second temperature of about 800° C. to about 1400° C. in a second atmosphere lacking oxygen. In addition, a method of annealing a substrate comprising a trench containing a dielectric material, the method including annealing the substrate at a first temperature of about 400° C. to about 800° C. in the presence of an oxygen containing gas, purging the oxygen containing gas away from the substrate, and raising the substrate to a second temperature from about 900° C. to about 1100° C. to further anneal the substrate in an atmosphere that lacks oxygen.Type: GrantFiled: November 16, 2004Date of Patent: January 5, 2010Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Zheng Yuan, Vikash Banthia, Xinyun Xia, Hali J. L. Forstner, Rong Pan
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Publication number: 20090309160Abstract: A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate.Type: ApplicationFiled: August 20, 2009Publication date: December 17, 2009Applicant: International Business Machines CorporationInventors: Guy Moshe Cohen, Patricia May Mooney
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Patent number: 7625807Abstract: The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.Type: GrantFiled: February 23, 2007Date of Patent: December 1, 2009Assignee: Texas Instruments IncorporatedInventors: Manuel A. Quevedo-Lopez, James J. Chambers, Leif Christian Olsen
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Patent number: 7625603Abstract: A silicon oxide layer is formed by oxidation or decomposition of a silicon precursor gas in an oxygen-rich environment followed by annealing. The silicon oxide layer may be formed with slightly compressive stress to yield, following annealing, an oxide layer having very low stress. The silicon oxide layer thus formed is readily etched without resulting residue using HF-vapor.Type: GrantFiled: November 14, 2003Date of Patent: December 1, 2009Assignee: Robert Bosch GmbHInventors: Aaron Partridge, Markus Lutz, Silvia Kronmueller
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Patent number: 7625805Abstract: Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar surface formed by the isolating layers. The filling is planarized and a portion of the filling located in the trench interior is removed. A portion of the isolation layers are then removed and a portion of the filling is removed so that the filler and the isolation layers in the trenches are at about the same level. A covering layer is then deposited. The covering layer extends above the surface of the wafer and into the trenches down to the filler and the isolation layers. The covering layer is additionally planarized to about the top of the trenches.Type: GrantFiled: January 31, 2005Date of Patent: December 1, 2009Assignee: X-FAB Semiconductor Foundries AGInventors: Ralf Lerner, Uwe Eckoldt
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Patent number: 7622369Abstract: A method of forming device isolation regions on a trench-formed silicon substrate and removing residual carbon therefrom includes providing a flowable, insulative material constituted by silicon, carbon, nitrogen, hydrogen, oxygen or any combination of two or more thereof; forming a thin insulative layer, by using the flowable, insulative material, in a trench located on a semiconductor substrate wherein the flowable, insulative material forms a conformal coating in a silicon and nitrogen rich condition whereas in a carbon rich condition, the flowable, insulative material vertically grows from the bottom of the trenches; and removing the residual carbon deposits from the flowable, insulative material by multi-step curing, such as O2 thermal annealing, ozone UV curing followed by N2 thermal annealing.Type: GrantFiled: May 30, 2008Date of Patent: November 24, 2009Assignee: ASM Japan K.K.Inventors: Woo Jin Lee, Atsuki Fukazawa, Nobuo Matsuki
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Publication number: 20090286380Abstract: A method for manufacturing a semiconductor device includes forming an oxide film uniformly in a trench in the device isolation by, for example, a radical oxidation process. The method also includes increasing the thickness of the oxide film positioned at recess sidewalls by forming a gate oxide film. Manufacturing the device according to this method will prevent junction leakage and maintain a gate oxidation intensity characteristic that will improve the refresh characteristic of the device.Type: ApplicationFiled: December 23, 2008Publication date: November 19, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Seung Bum Kim, Jong Kuk Kim
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Publication number: 20090283873Abstract: A method for forming a self-align insulation of a passing gate is disclosed. First, a substrate is provided. A deep trench filled with silicon material and a shallow trench isolation adjacent to the deep trench are formed in the substrate. A patterned pad oxide and a patterned hard mask are sequentially formed on the substrate. The patterned pad oxide and the patterned hard mask together define the opening of the deep trench. Then, an oxidation step is carried out to form a first oxide layer serving as the insulation of a passing gate on the top surface of the silicon material of the deep trench. Later, a first Si layer is formed to cover the first oxide layer. Afterwards, the hard mask is removed.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Inventor: Hon-Chun Wang
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Patent number: 7612427Abstract: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.Type: GrantFiled: September 17, 2007Date of Patent: November 3, 2009Assignee: LSI CorporationInventors: Sean Christopher Erickson, Jason Dee Hudson
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Patent number: RE41696Abstract: The present invention provides a semiconductor device that reduces the junction leak current and achieves an improvement in the reliability of the gate oxide film by minimizing divot formation and the occurrence of a kink and a method of manufacturing such a semiconductor device. A pad oxide film and a silicon nitride film are formed on an Si substrate and a groove-like trench is formed through photolithography and etching. The liner oxide of the trench are oxidized through oxidizing/nitriding. Then, the trench is filled with an insulating film, the insulating film is planarized and the silicon nitride film and the pad oxide film are removed. Next, a field area is formed and a transistor is formed by following specific steps. By forming a trench liner oxide film containing nitrogen, stress is reduced.Type: GrantFiled: November 3, 2005Date of Patent: September 14, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Michiko Yamauchi