Abstract: A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation process. An oxidation process is performed that combines with the nitrided surfaces (1312) to form a nitrogen containing liner. Subsequently, the trench region is filled with dielectric material (1316) and then planarized (1318) to remove excess dielectric fill material.

Abstract: The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.

Abstract: A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised of oxide to protect an oxide layer on a semiconductor substrate. Thereafter, an exposed portion of the liner layer is converted into the subsequent material of oxide to protect the dielectric fill material within the STI opening during etching away of masking layers to prevent formation of dents in the STI structure.

Abstract: A manufacturing method of a semiconductor device having a trench is provided to form, at a corner portion of the trench, an oxide film which is greater in thickness and smaller in stress than at other portions. When the trench formed in the semiconductor substrate is oxidized, it is oxidized in an oxygen environment containing dichloroethylene at a predetermined weight percent to allow the formation of an oxide film having a greater thickness at the corner portion of the trench than thickness at other portions, whereby the semiconductor device improving dielectric breakdown characteristics can be obtained.

Abstract: A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of the first area thereby leaving a second smaller area exposed. The region underlying the second area is etched to form an isolation trench that is then filled with a dielectric. The spacers are removed to expose the perimeter region. Using the masking structure and the trench dielectric as a mask, an impurity distribution is implanted into a portion of the substrate underlying the perimeter region. The impurity distribution thus surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate. The perimeter impurity distribution dopant, in a typical case, is p-type for NMOS transistors and n-type for PMOS.

Abstract: The present invention provides a semiconductor device formed with a diode array together with bipolar transistors, which is capable of preventing the occurrence of crystal defects developed in cross patterns in deep trench regions and improving device yields, and a method of manufacturing the semiconductor device. A semiconductor device includes a LOCOS oxide film which isolates a plurality of diodes in an X direction, and deep trenches which isolate the plurality of diodes in a Y direction. The depth of each of the deep trenches is deeper than a high density layer embedded below a collector layer of each bipolar transistor. A shallow trench may be used as an alternative to the LOCOS oxide film.

Abstract: A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding area.

Abstract: An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active region. An epitaxial silicon layer extends from the active region through the insulation layer to a substrate beneath the insulation layer.

Abstract: One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a first semiconductor wafer such that the surface of the first semiconductor wafer has a number of raised areas and a number of recessed areas. A surface of a second semiconductor wafer is bonded to the raised areas of the first semiconductor wafer in an environment having a first pressure. The surface of the second semiconductor wafer is bonded to the recessed areas of the first semiconductor wafer in an environment having a second pressure. The second pressure is greater than the first pressure to influence the second semiconductor wafer into contact with the first semiconductor wafer in the recesses in the surface of the first semiconductor wafer. Other aspects are provided herein.

Abstract: Methods for forming a device isolating barrier, and methods for forming a gate electrode using the device isolation barrier are disclosed. In an illustrated method, a semiconductor device isolating barrier is formed by forming a pad oxide layer and a first nitride layer on a semiconductor substrate; forming a trench region by etching the pad oxide layer and the first nitride layer; forming spacers at sidewalls of the etched pad oxide layer and the etched first nitride layer; forming a first trench by etching the semiconductor substrate using the spacers and the etched first nitride layer as a mask; and, after forming a liner oxide layer and an oxide layer filling the trench, forming the device isolating barrier by flattening the liner oxide layer and the trench oxide layer to expose the etched first nitride layer.

Abstract: Disclosed is a method of forming the isolation film in the semiconductor device which can prevent concentration of an electric field by forming a dual slant angle at the top corner of the trench in the course of forming the trench. After a photoresist pattern containing silicon components or an amorphous silicon film is formed on a pad oxide film instead of a pad nitride film, the surface of the photoresist pattern or the amorphous silicon film is oxidized so that the oxidized portion is fused with the isolation film. Accordingly, it is possible to prevent generation of a moat in the course of removing the photoresist pattern and the pad oxide film after the trench is buried with an insulating material. Therefore, the disclosed method can improve reliability of the process and an electrical characteristic of the resulting device.

Abstract: Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of the first insulating material. These voids are filled during the application of a conductive layer and can then lead to short circuits. Inventively, a layer for closing up voids is produced before the conductive material is applied, as a result of growing a second electrically insulating material onto the surface of the remaining first insulating material. This second insulating layer closes up voids that have formed in the first insulating material so that they can no longer lead to short circuits. In particular, voids that are difficult to gain access to and open out into side walls of contact holes can in this way be closed up in a simple manner.

Abstract: A semiconductor device has an STI oxide film (106), of which surface is positioned higher than the surface of the silicon substrate (100) to prevent a pointed portion and a thin film thickness of a gate oxide film (108). The gate oxide film (106) becomes thicker toward a side wall (112) of the STI oxide film (106) to prevent the leakage current and increase the gate breakdown voltage.

Abstract: A semiconductor substrate having a front surface and a backside is prepared. A first silicon oxide layer is formed on the front surface of the semiconductor substrate and, simultaneously, forming a second silicon oxide layer on the backside of the semiconductor substrate. A first silicon nitride layer is formed on the front surface of the semiconductor substrate and, simultaneously, forming a second silicon nitride layer on the backside of the semiconductor substrate. Lithographic and etching process is performed, using the first silicon nitride layer as an etching hard mask, to etch a trench into the front surface of the semiconductor substrate. The trench is then filled with insulating material. Using the insulating material as an etching hard mask, the second silicon nitride layer on the backside of the semiconductor substrate is etched away. A densification process is then performed to densify the insulating material.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth within the semiconductor substrate forms a local oxide region within the semiconductor substrate. A portion of the substrate forms a semiconductor layer over the local oxide region. In various embodiments, the semiconductor layer is an ultra-thin semiconductor layer having a thickness of approximately 300 ? or less. The oxide growth strains the semiconductor layer. An active region, including the body region, of the transistor is formed in the strained semiconductor layer. Other aspects are provided herein.

Abstract: A method for forming an isolation layer of a semiconductor device is disclosed, which comprises the steps of: etching a silicon substrate having a cell region and a peripheral circuit region, forming a first trench having a first size in the cell region, and forming a second trench having a second size, which is larger than the first size of the first trench, in the peripheral circuit region; forming a sidewall oxide layer on surfaces of the first trench and the second trench; sequentially depositing a liner nitride layer and a liner oxide layer on a resultant substrate inclusive of the sidewall oxide layer; performing a plasma pre-heating process using O2+He with respect to the resultant substrate in an HDP CVD process chamber and selectively oxidizing a portion of the liner nitride layer remaining on a bottom of the second trench in the peripheral circuit region; continuously depositing an HDP oxide layer on the resultant substrate having been subjected to the plasma pre-heating process, thereby filling the

Abstract: A method for fabricating an isolation layer in a semiconductor device is disclosed. The method comprises the steps of: forming a pad oxide film and a pad nitride film sequentially on a semiconductor substrate defining a cell region and a peripheral region; forming a trench on the semiconductor substrate by etching the pad oxide film, the pad nitride film and the substrate; forming an oxide film of side walls on a surface of the trench; depositing an amorphous silicon film on a resultant substrate inclusive of the trench; etching the amorphous silicon film so that the trench is partly filled; depositing an insulation film on a resultant substrate so that the partly filled trench is filled completely; carrying out a CMP process of the insulation film to expose the pad nitride film; and removing the pad nitride film.

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

Abstract: A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the semiconductor substrate while maintaining portions of the doped layer on opposite sides of the groove. A gate insulating layer may be formed on a surface of the groove, and a gate electrode may be formed on the gate insulating layer in the groove.

Abstract: Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.

Abstract: A trench isolation having a sidewall and bottom implanted region located within a substrate of a first conductivity type is disclosed. The sidewall and bottom implanted region is formed by an angled implant, a 90 degree implant, or a combination of an angled implant and a 90 degree implant, of dopants of the first conductivity type. The sidewall and bottom implanted region located adjacent the trench isolation reduces surface leakage and dark current.

Abstract: A method of fabricating a trench isolation with high aspect ratio. The method comprises the steps of: providing a substrate with a trench; depositing a first isolation layer filling the trench by low pressure chemical vapor deposition; etching the first isolation layer so that its surface is lowered to the opening of the trench; depositing a second isolation layer to fill the trench without voids by high density plasma chemical vapor deposition and achieving global planarization by chemical-mechanical polishing then providing a rapidly annealing procedure. Accordingly, the present invention achieves void-free trench isolation with high aspect ratio.

Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

Abstract: In a method for fabricating a semiconductor laser device, a plurality of grooves are formed in a surface of one conductive type of an InP layer. The InP layer is thermally treated in an atmosphere including at least a gas containing phosphorus and a gas containing arsenic in a mixed state, thereby forming a plurality of active regions made of InAsP in the plurality of grooves. An other conductive type of semiconductor layer is formed after the active regions are formed.

Abstract: A method for the fabrication of an integrated semiconductor component, in which at least one isolation trench is formed, a first layer of a nonconductive material is applied by a nonconformal deposition method, and a second layer of a nonconductive material is applied by a conformal deposition method at least to the back surface of the semiconductor component.

Abstract: An improved isolation structure for use in an integrated circuit and a method for making the same is disclosed. In a preferred embodiment, an silicon dioxide, polysilicon, silicon dioxide stack is formed on a crystalline silicon substrate. The active areas are etched to expose the substrate, and sidewall oxides are formed on the resulting stacks to define the isolation structures, which in a preferred embodiment constitute dielectric boxes containing the polysilicon in their centers. Epitaxial silicon is grown on the exposed areas of substrate so that it is substantially as thick as the isolation structure, and these grown areas define the active areas of the substrate upon which electrical structures such as transistors can be formed. While the dielectric box provides isolation, further isolation can be provided by placing a contact to the polysilicon within the box and by providing a bias voltage to the polysilicon.

Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.

Abstract: A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.

Abstract: A radiation-hardened STI process includes implanting a partially formed wafer with a fairly large dose (1013 to 1017 ions/cm2) of a large atom group III element, such as B, Al, Ga or In at an energy between about 30 and 500 keV. The implant is followed by an implant of a large group V element, such as P, As, Sb, or Bi using similar doses and energies to the group III element. The group V element compensates the group III element. The combination of the two large atoms decreases the diffusivity of small atoms, such as B, in the implanted areas. Furthermore, the combination of the group III and group V elements in roughly equal proportions creates recombination sites and electron traps in the field oxide, resulting in a radiation hardened semiconductor device.

Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: A pad oxide film and a silicon nitride film are formed on a semiconductor substrate. Next, after the patterning of the silicon nitride film, by etching the pad oxide film and the substrate, a first trench is formed in a first region and a second trench is formed in a second region. After that, by performing side etching of the pad oxide film of the first region while protecting the second region with a resist, a gap is formed between the substrate and the silicon nitride film. Subsequently, the inner surfaces of the first and second trenches are oxidized. At this time, a relatively large volume of oxidizing agent (oxygen) is supplied to a top edge portion of the first trench, and the curvature of the corner of the substrate increases.

Abstract: A method of reducing trench aspect ratio. A trench is formed in a substrate. Using HDP-CVD, a conformal first oxide layer is formed on a surface of the trench. A conformal first nitride layer is formed on the first oxide layer. Part of the first nitride layer is removed to cause the first nitride layer to be lower than a top surface of the substrate. Using a BOE solution, the first nitride layer and part of the first oxide layer are removed to leave a remaining first oxide layer on the lower portion of the surface of the trench. Thus, the trench aspect ratio is reduced.

Abstract: A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.

Abstract: A semiconductor device ensuring an isolation of elements by a trench is provided. A method of manufacturing the semiconductor device includes the step of forming a silicon nitride film having an aperture, the step of selectively removing a part of a silicon substrate along aperture to form a recess defined by a side surface and a bottom surface in silicon substrate, the step of oxidizing the side surface and the bottom surface of the recess to form a thermal oxide film having a side portion and a bottom portion, and the step of selectively removing bottom portion of thermal oxide film and a part of silicon substrate by using silicon nitride film as a mask to form a trench.

Abstract: A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.

Abstract: The present invention discloses semiconductor device which comprises a metal gate electrode surrounded by polysilicon layers and a gate insulating film whose edges are thicker than the center portion formed according to a reoxidation process using a thermal process before the formation of an ion implantation region in a process for forming the metal gate electrode using a replacement process and method for manufacturing the same.

Abstract: An isolation structure having both deep and shallow components is formed in a semiconductor workpiece by etching the workpiece to define raised precursor active device regions separated by sunken precursor isolation regions. An oxidation mask is patterned to expose the precursor isolation regions, and the unmasked precursor isolation regions are exposed to oxidizing conditions to grow field oxides as the deep isolation component. Thermal growth of these field oxides creates topography which includes shallow recesses adjacent to the raised precursor active device regions. Deposition of conformal dielectric material such as high density plasma (HDP) deposited silicon oxide over the entire surface and within the recesses creates the shallow isolation component. Following planarization of the conformal dielectric material, fabrication of the device is completed by introducing conductivity-altering dopant into raised precursor active device regions.

Abstract: A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench.

Abstract: A method of forming a trench isolation in a semiconductor substrate is described, which comprises the steps of forming a trench on the substrate, forming a diffusion barrier insulating layer, forming a thermal oxide layer both sidewall and bottom of the trench contacted with the diffusion barrier insulating layer, forming a nitride liner, and forming trench isolation material to fill the trench. A multi-structure of the barrier layer and the thermal oxide layer is provided between the nitride liner and the trench, resulting in minimization of transistor characteristic deterioration. A thin thermal oxide layer is formed to achieve improved trench etching profile.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride laver and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: A provided method for manufacturing the semiconductor device includes the steps of: forming a trench in a silicon substrate on which a silicon oxide film and a silicon nitride film are sequentially stacked; oxidizing the silicon substrate by an oxidation method of not forming nearly at all a silicon oxide film on a surface of the silicon nitride film, to form a silicon oxide film on the surface of the trench and perform pullback etching on the silicon nitride film; and performing rounding oxidation by using radical oxidation to round an edge of the surface of the trench. Therefore, it is possible to perform pullback etching on the nitride film, even in case of performing rounding oxidation by using radical oxidation.

Abstract: A semiconductor component has a cavity formed in a monocrystalline silicon substrate. The wall of the cavity is covered by a cover layer, at least in an upper collar region, and a covering layer is then applied to the surface of the silicon substrate using a selective epitaxial growth method. The cavity is thereby covered in the process. The method is physically simple and can be carried out cost-effectively. In particular, the described method can be used in order to cover a trench prior to high-temperature processes during the production of a DRAM memory, and to open the trench once again after the high-temperature processes, in order to provide a trench capacitor.

Abstract: A dry silylation process involving plasma etching of a substrate (100) having an upper surface (100S) coated with a first layer (L1) of silylatable material with one or more silylated regions (S1, S2) formed therein. The plasma (66) is oxygen-based plasma having a first region (66L) with a low plasma density and high radical density, and a second region (66U) having a high plasma density and a low radical density. The process includes the steps of exposing the one or more silylated regions to the first plasma region to form respective one or more oxidized regions (OR1, OR2) from the one or more silylated regions. The next step is then exposing the substrate to the second plasma region to selectively etch the silylatable material that is directly exposed to the plasma. The process of the present invention can be used, for example, to form photoresist patterns (P) having straight (vertical) sidewalls (SW) in the fabrication of a semiconductor device.

Abstract: First, a substrate, on which a plurality of semiconductor devices is formed, is provided. Next, a first etching treatment is carried out to the substrate with a first etching gas comprising CF4 to form a base trench having a rounded-off upper edge or tapered upper edge. A second etching treatment is carried out to the substrate to form a trench region at the base trench so that the trench region has a rounded-off upper edge. And then, an insulating layer is formed on the substrate to fill up the trench region therewith.

Abstract: A semiconductor device capable of preventing a ring defect and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate having a junction region, a planarization layer having a first contact hole portion through which the junction region is exposed, an interlayer dielectric layer formed on the planarization layer and having a second contact hole portion extended from the first contact hole portion, and contact spacers formed at the sidewalls of the first and second contact hole portions. Here, the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate.

Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.

Abstract: Within a method for forming an isolation region within a semiconductor substrate, there is, prior to forming the isolation region within an isolation trench formed adjoining an active region of a semiconductor substrate, implanted a dopant into a corner of the active region. The corner of the active region is uncovered by laterally etching an isolation trench mask to form a laterally etched isolation trench mask which serves as an ion implantation mask layer when implanting the dopant into the corner of the active region. The method provides for enhanced performance, and minimal affect of a semiconductor device formed within the active region of the semiconductor substrate.

Abstract: A surface of a semiconductor substrate is selectively etched to form a first opening, which serves as the opening of a trench. A USG film is deposited on the first opening. A second opening, the width of which is smaller than that of the first opening, is formed in the USG film within the first opening. An inner section of the trench is formed by etching while using the USG film as a mask. The inner surface of the inner region is thermally oxidized to form a silicon oxide film, and a gate insulating film is made by the silicon oxide film and the USG film. A gate electrode is formed in the trench. The gate insulating film is relatively thick at the opening of the trench, so the breakdown voltage at the opening of the trench is increased.

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.