Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.

Abstract: A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.

Abstract: The polishing solution is useful for removing barrier materials in the presence of at least one nonferrous interconnect metal with limited erosion of dielectrics. The solution contains 0 to 20 weight percent oxidizer, at least 0.001 weight percent inhibitor for reducing removal rate of the nonferrous interconnect metals, 1 ppm to 4 weight percent organic-containing ammonium cationic salt formed with a quanternary ammonium structure, 1 ppm to 4 weight percent anionic surfactant, the anionic surfactant having 4 to 25 carbon atoms and the total carbon atoms in of the ammonium cationic salt plus the anionic surfactant being 6 to 40 carbon atoms, 0 to 50 weight percent abrasive and balance water; and the solution having a pH of less than 7.

Abstract: A method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein or more than one density or strain therein. The silicon oxide having at least one cavity or more than one density or strain is exposed to a gaseous mixture of NH3 and HF and heated, to substantially uniformly remove the silicon oxide. A method of removing an exposed sacrificial layer without substantially removing exposed isolation regions using the gaseous mixture of NH3 and HF and heat is also disclosed, as is an intermediate semiconductor device structure that includes a semiconductor substrate, a sacrificial layer overlying the semiconductor substrate, a diffusion barrier overlying the sacrificial layer, and exposed isolation regions.

Abstract: A manufacturing method of a semiconductor device wherein a metal pad is etched to form a trench in which a central part is concave in form, or to form a trench in the shape of a cylinder or a parallelepiped on the edge part of a metal pad. Accordingly, the contact area between a polymide isoindro quirazorindione (PIQ) or similar curable layer and the metal pad is increased and the bondability is improved. Accordingly, the technology of improving the characteristic of device by preventing the problem that the metal pad is excessively opened in a subsequent curing process and the layer of a lower portion of the metal pad is attacked is disclosed.

Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side of the cell array. A first isolation structure is formed at a first boundary region provided between the first side of the cell array and the peripheral region. A first active region is formed at a second boundary region that is provided between the second side of the cell array and the peripheral region. The first isolation structure has a first portion that has a first depth and a second portion that has a second depth.

Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.

Abstract: A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.

Abstract: A method for manufacturing a semiconductor device includes steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the main surface and in the trench; and forming a second epitaxial film on the first epitaxial film. The step of forming the first epitaxial film has a first process condition with a first growth rate of the first epitaxial film. The step of forming the second epitaxial film has a second process condition with a second growth rate of the second epitaxial film. The second growth rate is larger than the first growth rate.

Abstract: A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area.

Abstract: Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.

Abstract: Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.

Abstract: A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height.

Abstract: A method of fabricating a semiconductor device includes etching a silicon oxide film, a silicon nitride film, a polycrystalline silicone film, and a gate insulating film in a predetermined pattern including a first opening width corresponding to a first trench and a second opening width corresponding to a second trench, the second opening width being larger than the first opening width, and etching the semiconductor substrate to simultaneously form the first and second trenches so that a first depth of the first trench is equal to a second depth of the second trench, and a first angle between a first side surface and a first bottom surface of the first trench is smaller than a second angle between a second side surface and a second bottom surface of the second trench, and the first trench includes a curved portion at an upper portion of the first side surface.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the res

Abstract: Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.

Abstract: A method for forming an isolation structure in a semiconductor device including a substrate having a first region and a second region, the second region having an isolation structure formed to a larger width than a plurality of isolation structures formed in the first region, is provided. The method includes etching portions of the first and second regions of the substrate to form first and second trenches, wherein a width of the second trench is larger than that of the first trench, forming a first insulation layer to fill a portion of the first and second trenches, forming a barrier layer to fill the first and second trenches, etching portions of the first insulation layer and the barrier layer in the first region, removing the barrier layer, and forming a second insulation layer over the first insulation layer.

Abstract: Disclosed herein are flash memory devices and methods of making the same. According to one embodiment, a flash memory device includes first trenches formed in a semiconductor substrate and arranged in parallel, second trenches discontinuously formed in the semiconductor substrate and arranged between the first trenches, first isolation structures respectively formed within the first trenches, second isolation structures respectively formed within the second trenches, and active regions defined by the first isolation structures and the second isolation structures.

Abstract: In a method of forming a silicon oxide layer, a spin-on-glass (SOG) layer may be formed on an object including a recess using an SOG composition. The SOG layer may be pre-baked and then cured by contacting with at least one material selected from the group consisting of water, a basic material and an oxidant, under a pressure of from about 1.5 atm to about 100 atm. The cured SOG layer may be baked.

Abstract: A method of fabricating a semiconductor device, includes forming an element isolation trench by processing a silicon substrate and a film to be processed, and filling the element isolation trench with an insulating film by a thermal CVD method. The thermal CVD method in filling the trench is executed under a film forming condition that the insulating film filling a part of the trench that is level with or is located lower than an upper surface of the silicon substrate has a porosity set so as to be not less than 5% and that the insulating film filling a part of the trench located higher than the upper surface of the silicon substrate has a lower deposition rate than the insulating film filling said part of the trench that is level with or is located lower than the upper surface of the silicon substrate.

Abstract: A method for manufacturing a semiconductor device comprising the steps of: forming a first insulating film to be used as a mask for forming a trench region directly above a semiconductor substrate; forming the trench region on the semiconductor substrate using the mask; forming a second insulating film directly above the semiconductor substrate which includes the trench region and the first insulating film so that the second insulating film has a recess above the trench region and a protrusion above the first insulating film; removing the protrusion down to the bottom of the recess as a first removal step; and removing the first insulating film and the second insulating film in accordance with a chemical mechanical polishing method so that the step formed of the recess and protrusion is reduced to 20 nm or less as a second removal step.

Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.

Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.

Abstract: A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie that is shared between at least two FETs. A second trench may also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.

Abstract: A semiconductor device having high aspect ratio isolation trenches and a method for manufacturing the same is presented. The semiconductor device includes a semiconductor substrate, a first insulation layer, and a second insulation layer. The semiconductor substrate has a second trench that is wider than a first trench. The first insulation layer is partially formed within the wider second trench in which the first insulation layer when formed clogs the opening of the narrower first trench. A cleaning of the first insulation layer unclogs the opening of the narrower first trench in which a second insulation layer can then be formed within both the first and second trenches.

Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.

Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, forming a first liner nitride layer on an exposed surface of the trench, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills the trench to cover a bottom surface and a side surface of the trench and an upper surface of the first liner nitride layer, etching overhangs generated during the forming of the first HDP oxide layer by introducing a hydrofluoric acid (HF) solution into the semiconductor substrate, forming a second liner nitride layer over the first HDP oxide layer, removing the second liner nitride layer formed on the first HDP oxide layer while forming a second HDP oxide layer to fill the trench, and subjecting the second HDP oxide layer to planarization, so as to form a trench isolation layer.

Abstract: According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.

Abstract: Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.

Abstract: An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide.

Abstract: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.

Abstract: There is provided a method of forming an isolation layer which prevents a failure from occurring depending on a difference in the area of the isolation layer during a planarization process of the isolation layer having a shallow trench isolation (STI) structure. The present invention implements a uniform isolation layer by forming a chemical mechanical polishing (CMP) stop layer on an isolation layer having a relatively large region and performing a planarization process using the CMP stop layer.

Abstract: According to a fabrication method for an element isolation structure section, that is, STI, of the present invention, by differing the etching rate of material to be embedded in a narrow-width, that is, a small area trench section (first trench section) formed in a small isolation area, from the etching rate of a material to be embedded in a wide-width (plane shape of larger area) trench section (second trench section) formed in a large isolation area, in the etching step, dishing (recessing) that inevitably occurs in a CMP step can be reduced. Therefore, a STI having a higher level of flatness can be formed. As a result, by simple steps, deterioration of the electrical characteristics of elements that are element-isolated by STI can be reduced. That is to say, not only STI having excellent electrical characteristics, but also a semiconductor device provided with such STI, can be provided at a good level of production yield.

Abstract: A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in an array region and a second peripheral region on the semiconductor substrate, successively depositing first and second gate electrode films and first and second mask insulators on each of the first and second gate insulators, forming an isolation trench on a surface of the semiconductor substrate to correspond to each position between the array region and the first and second regions of the peripheral region, depositing a buried insulator on the entire surface, and polishing an upper surface of the buried insulator so that the upper surface can be planarized.

Abstract: Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

Abstract: A semiconductor device includes a plurality of first MOS transistors has a first gate electrode formed on a first gate insulating film provided on a semiconductor substrate, a plurality of second MOS transistors has a second gate electrode formed on a second gate insulating film which is provided on the substrate and which is smaller in thickness than the first gate insulating film. A first element isolation region has a first region and a second region, a bottom surface of the second region is deeper than that of the first region by the difference of thickness between the first gate insulating film and the second gate insulating film, and a bottom surface of the first region is equal in a bottom surface of a second element isolation region.

Abstract: A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.

Abstract: A method of forming a device isolation film of a semiconductor device is provided. The method of forming a device isolation film of a semiconductor device according to an embodiment includes forming the device isolation film by ion-implanting insulation materials inside of a trench formed on a semiconductor substrate.

Abstract: A method for an isolation structure is provided. First, a substrate with a shallow trench isolation is provided. Second, a patterned mask is formed on the substrate. Then, the substrate is etched using the patterned mask to respectively form a first deep trench and a second deep trench as well as a first undercut and a second undercut on opposite sides of the shallow trench isolation. Later, the first deep trench and the second deep trench are partially filled with Si. Afterwards, the first deep trench and the second deep trench are filled with an isolation material to form the isolation structure.

Abstract: A method of forming a semiconductor device includes etching a semiconductor substrate to form a first trench having a first width and a first depth; etching the semiconductor substrate to form a second trench having a second width and a second depth, the second trench overlapping the first trench, the second width being greater than the first width, the second depth being less than the first depth, whereby a trench having a dual structure is formed; and forming a first isolation structure within the trench having the dual structure. An embodiment of the present invention relates to a method of forming an isolation structure of a semiconductor device.

Abstract: In one embodiment, a method of fabricating one or more transistors in an integrated circuit includes an annealing step prior to a gate oxidation step. The annealing step may comprise a rapid thermal annealing (RTA) step performed prior to a gate oxidation pre-clean step. Among other advantages, the annealing step reduces a step height difference between P-doped and N-doped regions of a field oxide of a shallow trench isolation structure. The shallow trench isolation structure may be separating a PMOS transistor and an NMOS transistor in the integrated circuit.

Abstract: Semiconductor device processing and methods for dicing a semiconductor wafer into a plurality of individual dies that can have back surface metallization are described. The methods comprise providing a wafer with pre-diced streets in the wafer's front surface, applying a sidewall masking mechanism to the front surface of the wafer so as to substantially fill the pre-diced streets, thinning the back surface of the wafer so as to dice the wafer (e.g., by grinding, etching, or both) and expose a portion of the sidewall masking mechanism from the back surface of the wafer, and applying a material, such as metal, to the back surface of the diced wafer. These methods can prevent the metal from being deposited on die sidewalls and may allow the separation of individual dies without causing the metal to peel from the back surface of one or more adjacent dies. Other embodiments are also described.

Abstract: A method for fabricating a semiconductor device, includes forming a silicon nitride film on a base body, forming a silicon film on said silicon nitride film, forming at least one groove extending from said silicon film to inside of said base body, forming by high-density plasma-enhanced chemical vapor deposition a silicon-containing dielectric film in said groove and on said silicon film in such a way that a silicon-rich layer is formed at a height position spaced apart from said base body within said groove, said silicon-rich layer being higher in silicon content than remaining silicon-containing dielectric film, removing by etching a portion of said silicon-containing dielectric film above said silicon film and a portion of said remaining silicon-containing dielectric film above said silicon-rich layer, if any, and after having removed said silicon-containing dielectric film, removing by etching said silicon-rich layer and said silicon film.

Abstract: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.

Abstract: A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).

Abstract: A semiconductor device includes: a semiconductor substrate having a low voltage (LV) region and a high voltage (HV) region; a pad oxide film pattern and a pad nitride film pattern which are formed over the semiconductor substrate. Further, the semiconductor device includes a shallow trench isolation (STI) formed in the LV region and a STI in the HV region, with a step generated therebetween by ions with which the HV region on the semiconductor substrate is doped when an etching process is carried out using the pad oxide film pattern and pad nitride film pattern as a mask.

Abstract: A silicon oxide layer is formed by oxidation or decomposition of a silicon precursor gas in an oxygen-rich environment followed by annealing. The silicon oxide layer may be formed with slightly compressive stress to yield, following annealing, an oxide layer having very low stress. The silicon oxide layer thus formed is readily etched without resulting residue using HF-vapor.