Abstract: Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar surface formed by the isolating layers. The filling is planarized and a portion of the filling located in the trench interior is removed. A portion of the isolation layers are then removed and a portion of the filling is removed so that the filler and the isolation layers in the trenches are at about the same level. A covering layer is then deposited. The covering layer extends above the surface of the wafer and into the trenches down to the filler and the isolation layers. The covering layer is additionally planarized to about the top of the trenches.

Abstract: A method of forming a device isolation region in a semiconductor device is capable of completely removing an oxide layer for trench formation in a central region of the semiconductor device without forming a moat in an edge region. The method begins with forming a sacrificial oxide and sacrificial nitride layer over a semiconductor substrate. Trenches are etched in the nitride layer, the oxide layer and the substrate in the central and edge regions, respectively. The trenches are filled with an oxide layer. The oxide layer is then polished until the sacrificial nitride layer formed in the edge region is exposed, to form a first device isolation region filling a first trench and a second device isolation region pattern filling a second trench and covering the second region. A photoresist pattern is formed over the first device isolation region and the second device isolation region pattern.

Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

Abstract: A method of forming device isolation regions on a trench-formed silicon substrate and removing residual carbon therefrom includes providing a flowable, insulative material constituted by silicon, carbon, nitrogen, hydrogen, oxygen or any combination of two or more thereof; forming a thin insulative layer, by using the flowable, insulative material, in a trench located on a semiconductor substrate wherein the flowable, insulative material forms a conformal coating in a silicon and nitrogen rich condition whereas in a carbon rich condition, the flowable, insulative material vertically grows from the bottom of the trenches; and removing the residual carbon deposits from the flowable, insulative material by multi-step curing, such as O2 thermal annealing, ozone UV curing followed by N2 thermal annealing.

Abstract: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: A method for forming a multi-layer shallow trench isolation structure in a semiconductor device is described. In one embodiment, the method includes etching a shallow trench in a silicon substrate of a semiconductor device and forming a dielectric liner layer on a floor and walls of the shallow trench. The method further includes forming a first doped oxide layer in the shallow trench, the first layer formed by vapor deposition of precursors including a source of silicon, a source of oxygen, and sources of doping materials at a first processing condition and forming a second doped oxide layer above the first doped oxide layer by vapor deposition using precursors of silicon and doping materials, at a second processing condition, different from the first processing condition.

Abstract: A method for fabricating a semiconductor device can prevent a leakage current and the decrease of threshold voltage by rounding corners of a trench. The method may include the steps of forming a pad insulating layer in a semiconductor substrate defined with an active region and a device isolation region, forming a first trench, forming polymer at inner sidewalls of the first trench, forming a second trench, removing the polymer, forming an oxide layer by thermally oxidizing the semiconductor substrate, and forming insulating layers for device isolation in the first and second trenches.

Abstract: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.

Abstract: An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner layer comprising a silicon nitride layer is formed on the first and second trenches. A spin on dielectric (SOD) layer comprising polysilazane is formed on the liner layer so as to fill the first and second trenches. A portion of the SOD layer filling the second trench is removed. A portion of the silicon nitride layer, which is disposed on the second trench and is exposed after the removing of the portion of the SOD layer, is oxidized using oxygen plasma and heat generated from the plasma. A high density plasma (HDP) oxide layer is formed to fill the second trench.

Abstract: A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.

Abstract: A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

Abstract: A method of manufacturing a semiconductor device comprises providing a semiconductor substrate, forming trenches in predetermined regions of the semiconductor substrate, forming isolation structures within the trenches that separate active regions and field regions of the device, and etching exposed regions of the semiconductor substrate so that the exposed regions of possess a curved surface. In a specific embodiment of the invention, an oxidization process is performed to compensate for damage on the exposed regions of the semiconductor substrate after etching the semiconductor substrate, and a wet etch process is performed to remove an oxide layer grown by the oxidization process. In a specific embodiment of the invention, the etch process may comprise a wet or dry etch process.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device, which may reduce damage due to stress of an STI bottom corner during an ion implantation and annealing being subsequent process of an STI in a semiconductor process are provided. According to embodiments, a method may include forming a prescribed insulating layer on a substrate, forming a photoresist pattern defining a trench region on the insulating layer, dry-etching the insulating layer and the substrate using the photoresist pattern as a mask to form a first trench region, and wet-etching the substrate on which the first trench region is formed using the photoresist pattern as a mask to form a second trench region.

Abstract: A semiconductor device includes a semiconductor substrate having a first element isolation trench with a first opening width and a second element isolation trench with a second opening width larger than the first opening width, the first and second element isolation trenches having respective inner surfaces, the second element isolation trench having opposed sidewalls and bottom, a first element-isolating insulation film formed on the inner surfaces of the first and second element isolation trenches, a second element-isolating insulation film formed on the first element-isolating insulation film so as to fill the first element isolation trench and further formed on the first element-isolating insulation film formed on the sidewall of the second element isolation trench, and a third element-isolating insulation film provided on the second element-isolating insulation film and the first element-isolating insulation film formed on the bottom of the second element isolation trench, so as to fill the second elemen

Abstract: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

Abstract: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

Abstract: A method of forming a micro pattern in a semiconductor device is disclosed. An oxide film mask is divided into a cell oxide film mask and a peri oxide film mask. Therefore, a connection between the cell and the peri region can be facilitated. A portion of a top surface of a first oxide film pattern between a region in which a word line will be formed and a region in which a select source line will be formed is removed. Accordingly, the space can be increased and program disturbance in the region in which the word line will be formed can be prevented. Furthermore, a pattern having a line of 50 nm and a space of 100 nm or a pattern having a line of 100 nm and a space of 50 nm, which exceeds the limitation of the ArF exposure equipment, can be formed using a pattern, which has a line of 100 nm and a space of 200 nm and therefore has a good process margin and a good critical dimension regularity.

Abstract: A semiconductor structure with dual isolation structures is disclosed. The semiconductor structure may include a protruding isolation structure in a pixel array region of a substrate and an embedded isolation structure in a peripheral device region of the same substrate. A region of the protruding isolation structure extends from an upper surface of the substrate, while another region of the protruding isolation structure may, optionally, be embedded within the substrate. The embedded isolation structure is formed within the substrate and includes an upper surface that is substantially coplanar with the upper surface of the substrate. A method of forming the semiconductor structure with dual isolation structure is also disclosed.

Abstract: A semiconductor device such as a flash memory includes a semiconductor substrate having a surface, and a plurality of trenches formed in the substrate so as to be open at the surface of the substrate, the trenches having opening widths different from each other. The trench with a smaller opening width is formed so as to have a first depth and the trench with a larger opening width has a bottom including opposite ends each of which has a second depth deeper than the first depth and a central portion shallower than the second depth.

Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

Abstract: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form a first sub-recess having a first central axis. A second sub-recess is formed under the first sub-recess. The second sub-recess is in communication with the first sub-recess. The second sub-recess has a second central axis substantially parallel with the first central axis. The second central axis is spaced apart from the first central axis.

Abstract: A method for producing narrow trenches in semiconductor devices. The narrow trenches are formed by chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in the first dielectric layer is converted locally and becomes etchable by a first etching substance. Subsequently a second dielectric material is deposited in the patterned structure and the damaged part of the first dielectric material is removed such that small trenches are obtained.

Abstract: A method for manufacturing an LCOS device includes forming an interlayer dielectric layer overlying a surface region of a substrate. The interlayer dielectric layer is patterned to form a plurality of recessed regions. Each of the recessed regions corresponds to a pixel element for a LCOS device and is isolated by a portion of dielectric material defining a border for each of the recessed regions. An aluminum material or aluminum alloy material is deposited within each of the recessed regions. A photomask is formed overlying the aluminum material and patterned to expose the recessed regions while protecting the border regions. Exposed regions of the aluminum material is removed while the border regions with the photomask is protected. The method continues the removing until the aluminum material has been removed to a vicinity of an upper region of the border regions. The patterned photomask is stripped to expose protruding aluminum material.

Abstract: A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches; and etching an active region of the substrate defined by the upper and lower trenches to a predetermined depth to form a recess pattern for a gate.

Abstract: Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant.

Abstract: In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.

Abstract: A semiconductor device comprising a trench device isolation layer and a method for fabricating the semiconductor device are disclosed. The method comprises forming a plurality of first trenches on a first region of a semiconductor substrate, filling the first trenches with a first insulation material to form first device isolation layers, forming a plurality of second trenches on a second region of the semiconductor substrate, and filling the second trenches with a second insulation material different from the first insulation material to form second device isolation layers, wherein the first trenches and the second trenches are formed using different respective processes.

Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Abstract: A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.

Abstract: A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer.

Abstract: Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the first width. The underlying layer is etched using the preliminary hard mask patterns as etch masks to thereby form preliminary underlying patterns. The preliminary hard mask patterns are pulled back, thereby forming hard mask patterns on the preliminary underlying patterns. An overlayer is formed on the substrate exposing top surfaces of the hard mask patterns. The hard mask patterns and the preliminary underlying patterns disposed below the hard mask patterns are etched using the overlayer as an etch mask, thereby forming underlying patterns having a second pitch smaller than the first pitch, and the overlayer is removed.

Abstract: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

Abstract: A three layer film (116/114/112), such as nitride/oxide/nitride for a CMP stop layer (110). A gap filling material (120) is polished, stopping on the first film (112). The first film (112) is then stripped using an etch chemistry that is selective against removing the second film (114). CMP is then continued stopping on the third film (116).

Abstract: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a mask including a first silicon nitride film over a semiconductor substrate, forming a trench in a surface of the semiconductor substrate using the mask, forming a silicon oxide film over the mask to embed the silicon oxide film in the trench, performing a first nitriding treatment to selectively convert a portion of the silicon oxide film above the trench into an oxynitride film, performing a second nitriding treatment of the silicon oxide and oxynitride film to form a second silicon nitride film, and planarizing the first silicon nitride film and second silicon nitride film.

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract: A device isolation structure of semiconductor device includes a semiconductor substrate having a cell region, a low voltage region and a high voltage region defined therein. A cell trench isolation region is disposed in the cell region. A low voltage trench isolation region is disposed in the low voltage region and extends deeper into the substrate than the cell trench isolation region. A first high voltage trench isolation region is disposed in the high voltage region and extends deeper into the substrate than the low voltage trench isolation region. A second high voltage trench isolation region is disposed in the high voltage region and extends deeper into the substrate than the low voltage trench isolation region but shallower than the first high voltage trench isolation region.

Abstract: A method of fabricating a semiconductor device includes forming a pad oxide film and a nitride film on a semiconductor substrate; exposing the semiconductor substrate by selectively etching the pad oxide film and the nitride film; forming a trench in the exposed semiconductor substrate; forming a gap-fill dielectric film in the trench; exposing an active area of the semiconductor substrate by removing the pad oxide film and the nitride film; forming an epitaxial layer including a dopant in the exposed active area; forming a gate electrode on the epitaxial layer; and forming source and drain regions in the active area beside the gate electrode. The semiconductor device can prevent surface damage of a semiconductor substrate, may occur when performing ion implantation for threshold voltage control, and does not require annealing after ion implantation.

Abstract: A method for fabricating a semiconductor device with a step gated asymmetric recess is provided.

Abstract: A method for manufacturing a semiconductor substrate comprises: forming a silicon on insulator (SOI) area and an element isolation film on a semiconductor base; forming a first semiconductor layer on the semiconductor base in the SOI structure area; forming a second semiconductor layer having an etching selection ratio smaller than an etching selection ratio of the first semiconductor layer on the first semiconductor layer; removing a part of the second semiconductor layer and a part of the first semiconductor layer in the SOI structure area so as to form a recess exposing the semiconductor base and supporting a support; forming a support forming layer on the semiconductor base so as to bury the recess and cover the second semiconductor layer; etching an area excluding the recess, the element area, and an area covering the element isolation film so as to form the support and an opening face exposing a part of end parts of the first semiconductor layer and the second semiconductor layer, the opening face being

Abstract: In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height.

Abstract: A high purity, high precision pump capable of pumping more than one type of chemistry or process fluid without requiring cleaning or changing of surfaces contacting the processing fluid. The pump employs a single drive mechanism coupled in parallel with multiple pumping chambers, each capable of handling a different type of manufacturing fluid. The pump can be utilized as part of a single stage or multi-stage pump system.

Abstract: A method of fabricating a structure including a low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer is described herein. The method includes applying a coating of a polymeric preceramic precursor, converting the polymeric preceramic precursor into a low-k sublayer, applying a coating of an air barrier sublayer and exposing the air barrier sublayer to a reactive plasma.

Abstract: A method for manufacturing a semiconductor device includes subjecting a semiconductor substrate to thermal treatment at a temperature ranging from 770 to 830° C. to fix channel ions then forming a HTO film. The method thereby prevents a threshold voltage of a gate from changing due to diffusion of channel ions.

Abstract: A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.

Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.

Abstract: A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second dielectric layer having a dielectric constant higher than that of the first dielectric layer. The second dielectric layer is formed on both the first region and a second region.

Abstract: A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinting a first pattern into the hard mask to define an open end of a first trench, imprinting a second pattern into the hard mask to define an open end of a second trench, and etching into the film stack the first trench to a first depth and the second trench to a second depth such that the first trench and the second trench each define a blind aperture in the surface of the film stack.