Abstract: A method of forming a shallow trench isolation structure is provided. A substrate having a pad oxide layer and a first insulating layer formed thereon is provided. A first trench with a small size and a second trench with a large size are formed in the substrate. A first dielectric layer and a second insulating layer are formed on the substrate sequentially. The second insulating layer is defined to form a dummy pattern to occupy a part of the second trench. A second dielectric layer is formed on the first dielectric layer and to fill into the remaining space of the second trench. A CMP process is performed to complete the shallow trench isolation trench structure.

Abstract: The present invention provides a process for fabricating a semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.

Abstract: A method for fabricating a semiconductor device and a semiconductor formed by this method, the method including, the steps of sequentially forming a pad oxide film, a polysilicon film, and an antioxidation film on an active region of a semiconductor substrate such that a field region is exposed; etching an exposed portion of the surface of the substrate to a predetermined thickness to form a trench within the substrate; forming a first insulation film along the inner face of the trench by using an oxidation process; forming a stress buffer film on the entire surface of the resultant structure; forming a second insulation film on the stress buffer film such that the trench is sufficiently filled; making the second insulation film planar such that the remaining antioxidation film has a predetermined thickness on the active region of the substrate so as to form a shallow trench isolation within the trench; and sequentially removing the remaining antioxidation film, the polysilicon film, and the pad oxide film.

Abstract: A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrates. Oxide is deposited as a trench liner in the trench using high temperature high density plasma (HDP) deposition. As the high temperature HDP oxide deposition is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overreach at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

Abstract: A method of forming trench isolation which protects a nitride liner in the trench during subsequent plasma processing, by forming a high temperature oxide layer, such as an HTO oxide layer or LP-TEOS oxide layer. A trench mask is formed on a semiconductor substrate to define a trench forming region, the semiconductor substrate is etched using the trench mask to form a trench, a thermal oxide layer is formed on a bottom and sidewalls of the trench to remove substrate damage caused by the etching, a material layer is formed on the thermal oxide layer to prevent the bottom and sidewalls of the trench from being oxidized, a protection layer is formed on the oxidation barrier layer, the bottom and sidewalls of the trench are plasma processed, and the trench is then filled with a trench fill material uniformly with respect to the bottom and sidewalls.

Abstract: A method of manufacturing a semiconductor device having a microminiture trench isolation in which an insulating film is embedded by an HDP-CVD method comprising: a step of pre-planarization by conducting a dry etching selectively with respect to the insulating film laminated excessively on the surface of substrate, which is to be an active region, and a step of polishing by a CMP method in order to improve a surface planarity of the insulating film, wherein an etching mask used at the time of opening a trench opening portion has a multi-layer structure including a silicon nitride film and a polycrystal silicon film; the polycrystal silicon film is used as an etching stopper at the time of pre-planarization; and the silicon nitride film is used as an etching stopper at the time of polishing by a CMP method in order to remove simultaneously the excessive insulating film and the polycrystal silicon film to expose and a surface of the substrate, which is the active region, whereby the trench isolation having a sa

Abstract: Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.

Abstract: The present invention provides a method to form a dishing-free insulator in trench isolation without repeated formations of silicon sidewall spacers and thermal oxidation of the silicon sidewall spacers. Using Ion-Metal Plasma (IMP) process to deposit silicon film directionally in the trenchs of the substrate is the key point of the present invention.

Abstract: A trench isolation structure including high density plasma enchanced silicon dioxide trench filling (122) with chemical mechanical polishing removal of non-trench oxide.

Abstract: In an example embodiment, a method for manufacturing a semiconductor device having shallow trench isolation comprises forming a trench region in a substrate having a substantially planar bottom, a first and second sidewall. In the trench region, the method forms a dielectric liner on the bottom and the first and second sidewalls. The dielectric liner is a silicon nitride compound. The dielectric liner minimizes the anomalous increases in threshold voltage with width (Vt versus W) owing to transient enhanced up-diffusion of the channel profile induced by source/drain implant damage. In addition, the anomalous increase in Vt versus W associated with the formation of an interstitial gradient in sub-micron devices is reduced. By using a nitrided liner, Vt roll off due to boron segregation is also minimized.

Abstract: A trench isolation structure can be formed in a stack trench capacitor fabrication process by forming a trench region (18) through a buffer layer (16) and an interface layer (12) and into a semiconductor substrate (14). A trench wall layer (20) is grown on inner walls of the trench region (18) and in contact with the interface layer (12). A trench filler layer (28) is formed on the buffer layer (16) and on the trench wall layer (20) within the trench region (18). The trench filler layer (28) is removed from the buffer layer (16) but remains within the trench region (18). A storage dielectric (30) is deposited on the buffer layer (16) and on the trench filler layer (28) within the trench region (18). A field plate layer (32) is deposited on the storage dielectric (30) and within the trench region (18). The field plate layer (32), the storage dielectric (30), the buffer layer (16), and the interface layer (12) lying outside the trench region (18) are removed.

Abstract: A method of forming a shallow-deep trench isolation (SDTI) is provided that includes the steps of forming a pair of deep trenches through a silicon on insulator (SOI) layer without substantially disturbing an underlying buried oxide (BOX) layer. Once the deep trenches are formed, the trenches are filed with suitable electrical isolating materials, such as undoped poly-silicon or dielectric material, and etched back to obtain a substantially planarized top surface. Subsequently, an active nitride layer is deposited on the planarized top surface, and then a pair of shallow trenches are formed. The shallow trenches are formed using a low selectivity etch to uniformly etch a deep trench liner oxide, the SOI layer and the electrical isolating material which have interfaces at non-perpendicular angles with respect to the direction of the etching. Once the shallow and deep trenches are formed, subsequent processing including filling the shallow trench, annealing and chemical-mechanical polishing can be performed.

Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench—trench short circuiting.

Abstract: A method of manufacturing semiconductor devices or precursors to semiconductor devices by hydrophobically modifying a device layer to thereby decrease the rate of polishing of the layer by at least 15%. The hydrophobically modified layer can be used as a stop layer to thereby allow for improved planarization of at least one layer of the device.

Abstract: A method of trench polishing. A semiconductor substrate is provided. A photo-mask with a pattern is provided. The method of fabricating the photo-mask further comprising providing an original pattern which comprises a plurality of active regions with individual size. The original pattern is enlarged outwards to connect and merge some of the active regions. The active regions is diminished inwards until some small active regions eliminate, the diminished line width being denoted as B. A reverse treatment is performed to obtain a reverse pattern. The reverse pattern is enlarged with a line width C. The reverse pattern is combined with the original pattern. The substrate is patterned with the photo-mask with the combined pattern. An insulation layer is formed on the substrate. The insulation layer is polished.

Abstract: A polycrystalline silicon film is formed on a surface of a trench and on a surface of a silicon nitride film. A silicon substrate covered with a polycrystalline silicon film is thermally oxidized at 900 to 1100° C. in an oxygen ambient to provide an uneven interface between a thermally oxidized silicon film and the silicon substrate. Thus a semiconductor device can be obtained capable of reducing a compressive stress caused in the semiconductor substrate near an element isolating trench region to minimize formation of crystal defect.

Abstract: A method for filling a trench is provided. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench. A processing line includes a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.

Abstract: An improved method of forming the buried plate regions in deep trench capacitors used in DRAM memory semiconductor circuits in which the polymer used in the deep trench is etched down to the desired depth in a reactive ion etch tool using an O2/CF4 chemistry. Since optical/interferometric etch end-point detection system can be used to monitor the etch back step in its totality, the quantity of the polymer remaining in deep trenches can be very accurately controlled, which in turn will produce a well controlled buried plate region during the out-diffusion step of the arsenic dopant contained in the arsenic doped silicon glass layer.

Abstract: A method for manufacturing a shallow trench isolation structure. A pad oxide layer and a mask layer are formed over a substrate. Portions of the mask layer, the pad layer and substrate are removed forming a trench. Oxidation of the substrate within the trench forms a linear oxide layer. The substrate at the bottom of the trench is exposed by removing a portion of the linear oxide layer at the bottom of the trench. A polysilicon layer, deposited completely over the mask, fills the trench as well. The polysilicon layer on the mask layer and outside the trench is removed, leaving polysilicon within the trench, which forms a polysilicon plug. A thin conformal barrier layer is formed over the substrate. An insulator layer is deposited above the barrier layer. The isolation layer and barrier layer on top of the mask as well as outside the trench are removed using a chemical mechanical polishing method. The mask is removed.

Abstract: The invention includes semiconductor processing methods, including trench isolation. In one implementation, an oxide layer is deposited over a substrate. The deposited oxide layer is exposed to a chlorine containing gas effective to getter metals outwardly therefrom. In one implementation, a dielectric layer, for example silicon dioxide, is plasma enhanced chemical vapor deposited over a substrate within a chamber comprising an internal metal surface under conditions effective to incorporate metal from the chamber surface within the dielectric layer. The dielectric layer is then exposed to a chlorine containing gas effective to getter at least some of said metal outwardly therefrom. In one implementation, a trench isolation method comprises forming a series of isolation trenches into a semiconductive substrate. Silicon dioxide is chemical vapor deposited to within the trenches, with the silicon dioxide comprising metal impurity therein.

Abstract: Methods of fabricating an isolation structure on a substrate are provided. In one aspect, a method of fabricating an isolation structure on a substrate is provided that includes forming a first insulating layer on the substrate wherein the first insulating layer has a first sidewall. A trench is formed in the substrate that has a second sidewall. A second insulating layer is formed in the trench. The second insulating layer displaces the second sidewall laterally. The first insulating layer is densified by heating to liberate gas therefrom and thereby move the first sidewall into substantial vertical alignment with the second sidewall. The risk of substrate attack due to trench isolation structure pullback is reduced. Trench edges are covered by thick isolation material.

Abstract: A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.

Abstract: A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrate. Oxide is deposited as a trench liner in the trench using low pressure chemical vapor deposition (LPCVD) high temperature oxidation (HTO). As LPCVD is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overetch at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

Abstract: The invention provides a method of forming shallow trench isolation. In the method, a first mask and a second mask layer are made of polysilicon and silicon oxide, respectively. Part of the first mask layer is oxidized into a protective oxide layer during thermal oxidation for forming a liner oxide layer. The protective oxide layer can protect the top corner of a trench from he formation of pits during subsequent etching for removing a pad oxide layer, thereby preventing a kink effect. Furthermore, after forming the liner oxide layer and before filling the trench with an insulting layer, a buffer layer formed over a substrate not only prevents the sidewalls of the trench from oxidizing, but also prevents a lateral etching damage during subsequent etching for removing the pad oxide layer.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a composite dielectric layer having etched via contact holes in which via poisoning is attenuated. There is provided a substrate employed within a microelectronics fabrication. There is formed upon the substrate a patterned microelectronics layer. There is then formed upon the substrate a blanket silicon containing dielectric layer employing high density plasma chemical vapor deposition (HDP-CVD). There is then formed upon the blanket silicon containing glass dielectric layer a low dielectric constant dielectric layer over which is formed a silicon oxide dielectric cap layer to form a composite inter-level metal dielectric (IMD) layer. There is then etched through the composite IMD dielectric layer a series of via contact holes. The method of formation, surface profile and properties of the blanket silicon containing glass dielectric layer provides attenuated via poisoning after via hole etching.

Abstract: A method of manufacturing shallow trench isolation structure comprising the steps of forming a polysilicon mask layer over a substrate, and then patterning the polysilicon mask layer and the substrate to form a trench. Thereafter, a silicon nitride layer is formed covering the sidewalls of the trench. Next, a high-density chemical vapor deposition method is used to deposit oxide material into the trench. Finally, the surface is polished to remove a portion of the oxide layer and the silicon nitride layer until the polysilicon mask layer is exposed. The shallow trench isolation structure can avoid subthreshold kink effect and reduce subthreshold leakage current.

Abstract: A first trench having a first width and a second trench having a width which is smaller than the first width are formed on a major surface of a semiconductor substrate. A first isolation insulator having an outer side wall is formed to fill up the first trench. A second isolation insulator having an outer side wall is formed to fill up the second trench. The first isolation insulator includes a side wall insulator film forming the outer side wall and an internal insulator film enclosed with the side wall insulator film for filling up the first trench. The second isolation insulator includes an internal insulator film forming the outer side wall for filling up the second trench. Thus obtained are a highly reliable semiconductor device comprising isolation insulators having different widths and a method of fabricating the same.

Abstract: Semiconductor device fabrication techniques which integrate the formation of trench isolation areas and gate insulating layers are provided. The fabrication techniques include forming one or more sacrificial layers, such as nitrided oxide layers, over regions of the substrate adjacent to a trench isolation region. The sacrificial layers are then removed prior to gate insulating layer formation. The formation of the sacrificial layers improves the trench structure and also improves the substrate surface for the subsequent formation of the gate insulating layer and gate electrode.

Abstract: The present invention provides a process for manufacturing a semiconductor structure comprising the steps of: (a) forming a first SiN film on a semiconductor substrate; (b) patterning the first SiN film, etching the resulting substrate using the first SiN film as a mask to form a plurality of first trenches and at least one second trench, so as to form a first islands group and at least one second island-like region; (c) depositing a SiO2 film to fill the first and second trenches with the SiO2 film; (d) forming a second SiN film over the resulting surface; (e) polishing the second SiN film and the SiO2 film by a CMP method using a first slurry until the surface of the first SiN film on the second island-like region is exposed; (f) polishing the second SiN film and the SiO2 film by a CMP method using a second slurry until the surface of the first SiN film on the first island-like region is exposed; (g) etching a predetermined amount of the SiO2 film; and (h) removing the second and first SiN films.

Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: The stress dislocations formed in a substrate by semiconductor processing are significantly reduced, if not eliminated, by subjecting the substrate to a high temperature post sacrificial oxide anneal that causes viscous flow of the oxide over the substrate. In one example embodiment, a method of forming a semiconductor structure includes forming a first oxide layer over a substrate and forming a first dielectric material layer over the first oxide layer. An opening is then etched in the oxide and dielectric layers thereby exposing the substrate. A trench is formed with a desired depth in the substrate in the opening provided, followed by a deposition of an insulator material in the trench. The first dielectric layer and a portion of the insulator material is then removed leaving a portion of the insulator material within the trench. Applications include logic circuits having embedded-DRAM and circuits directed to stand-alone logic or stand-alone DRAM.

Abstract: A method for fabricating a shallow trench isolation structure is described, in which a pad oxide layer, a silicon oxy-nitride layer and the silicon nitride layer are sequentially formed on the substrate. Photolithography and etching are further conducted to form a trench in the substrate. A liner oxide layer is then formed on the exposed substrate surface in the trench, followed by removing portions of the silicon nitride layer and the silicon oxy-nitride layer by wet etching. After this, the trench is filled with an oxide material d the excessive oxide material is removed by using the silicon nitride layer as barrier layer. The remaining silicon nitride layer and the silicon oxy-nitride layer are further removed to complete the fabrication of a shallow trench isolation structure.

Abstract: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. A fluorinated silicate glass (FSG) layer is formed on the liner layer by using high density plasma chemical vapor deposition (HDPCVD). A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.

Abstract: The present invention relates to a shallow trench isolation method of a semiconductor wafer for filling dielectric material in each shallow trench between components on the surface of the semiconductor wafer to isolate the components electrically and prevent dishing when the chemical-mechanical polishing is performed on the surface of dielectric material in each shallow trench.

Abstract: In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the non-trench area, similar amounts of material are removed in both the trench area and non-trench area in a subsequent etching process. Consequently, formation of notches and grooves in the semiconductor structure is minimized. A sacrificial oxide layer may be made depositing a layer of a suitable material on the surface of a semiconductor structure. By depositing sacrificial oxide layer instead of thermally growing a sacrificial oxide layer, grooves and the notches in the trench areas are filled by the deposited material.

Abstract: A method of fabricating shallow trench isolations (STI) which forms a substrate with a patterned first oxide layer and a patterned silicon nitride layer thereon, so that active regions are defined with openings formed between the active regions. The openings are then over etched to form trenches for fabricating the STI, followed by forming a second oxide layer that conforms to a profile of the trenches. A third oxide layer is globally formed over the second oxide layer, sidewalls of the first oxide layer, and the silicon nitride layer. A thermal process is performed to densify a portion of the third oxide layer, so that a top portion of the third oxide layer is harder than a lower portion of the third oxide layer. The excessive portion of the third oxide layer above the silicon nitride layer is removed by performing chemical mechanical polishing, which planarizes a top surface of the third oxide layer in order to complete the manufacture of the STI.

Abstract: A method for forming spacers for preventing formation of parasitic corner devices in transistors includes etching trenches into a semiconductor substrate to form an active area region, lining the trenches and the active area region with a first dielectric material and forming shallow trench isolation regions adjacent to the active area region by filling the trenches with a second dielectric material. The first dielectric material is removed from the active area region, and a gate oxide is formed over the active area region wherein divots form between the active area region and the shallow trench isolation regions. Dopants are implanted into the active area region to form a source and drain of the transistor. After the step of implanting, a spacer layer formed from a third dielectric material is deposited over the gate oxide layer to fill the divots.

Abstract: A method of fabricating a shallow isolation. The method comprises the step of forming a pad oxide layer and a mask layer over a substrate in turn. The mask layer is patterned. The pad oxide layer and the substrate are anisotropically etched by using the patterned mask layer as a hard mask in order to form a trench in the substrate. A rapid thermal processing annealing process under the N2 or NH3 is proceeding in order to form a silicon nitride layer on the substrate in the trench. The trench is filled with oxide to form the shallow trench isolation.

Abstract: A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias is applied. An argon flow with a high speed of etching/deposition is provided to form a second oxide layer. While forming the second oxide layer a triangular or trapezium profile is formed due to an etching effect to the corner. An argon flow with a low speed of etching/deposition is provided to form a third oxide layer. The gap filling is completed.

Abstract: A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate under the patterned region and the trench is filled with insulator to form an insulation plug, which is a shallow trench isolation. A dielectric layer is formed on the whole substrate surface to cover the device region and the insulation plug.

Abstract: Shallow trench isolation in which trenches having varying dimensions have been formed in a hard surface such as silicon nitride can lead to dishing inside the larger trenches. To overcome this, the trenches were first over-filled with a layer of HDPCVD oxide followed by the deposition of a relatively soft dielectric layer, using a conformal deposition method. CMP was then used to remove both the added layer and most of the original HDPCVD oxide, a small thickness of the latter being left in place. Because of the earlier influence of the added layer the resulting surface was planar and a conventional wet or dry etch could be used to remove the remaining oxide, thereby exposing the top surface and fully filling the trenches without any dishing.

Abstract: A semiconductor device with the trench isolation structure is provided, in which the leakage current problem does not occur. This device is comprised ofa semiconductor substrate, an isolation trench formed in a surface region of the substrate and filled with first and second isolation dielectrics, an interlayer dielectric layer formed on the surface region of the substrate to cover the isolation trench, and a conductive layer formed on the interlayer dielectric layer to be overlapped with the isolation trench. The interlayer dielectric layer has a contact hole located near the isolation trench. The contact hole is formed by etching. The conductive layer is contacted with and electrically connected to a region of the substrate through the contact hole of the interlayer dielectric layer. The first isolation dielectric serves as a primary insulator. The second isolation dielectric serves as a secondary insulator.

Abstract: A method is disclosed to form a shallow trench isolation (STI) having reduced junction leakage by avoiding undercutting near the shoulder of the trench. This is accomplished by using the pad oxide as a screen oxide and not removing it by wet dip etch as is normally practiced. Instead, an extra layer of low temperature oxide is added through thermal growth, and then the resulting composite is removed together with minimal undercutting at the shoulder corners of the trench. Subsequently, gate oxide is grown thermally to complete the forming of the STI.

Abstract: A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer with an enough thickness is deposited on the surface of the semiconductor substrate to overfill the trench. At least one dimple is undesirably developed on the polycrystalline silicon layer during the polycrystalline silicon deposition. Then, an oxide layer with an enough thickness is formed on the polycrystalline silicon layer to overfill the at least one dimple. Next, the polycrystalline silicon layer is partially oxidized so as to transform the upper portion thereof into a polysilicon oxide layer. As a result of a non-uniform distribution of the oxidization rate, the bottom surface of the polysilicon oxide layer, i.e. the interface between the polysilicon oxide layer and the non-oxidized portion of the polycrystalline silicon layer, is substantially planar.

Abstract: This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to an improved method of filling shallow trenches, in shallow trench isolation, STI sub-quarter micron technology. The present method relates to a process for forming trench gap filling with chemically vapor deposited (CVD) silicon dioxide layers within trenches within substrates employed in integrated circuit fabrication. There is first provided a silicon substrate having a trench formed therein. There is then formed a silicon dioxide layer through tetraethylorthosilicate (TEOS) and ozone reaction, at either sub-atmospheric, or atmospheric pressure, with enhanced surface sensitivity features, which lines the trench providing corner rounding. Then there is a thermal oxidation to form within the trench a thermal silicon dioxide layer underneath the TEOS-ozone trench silicon dioxide liner.

Abstract: A method for forming shallow trench isolation region. The method includes the steps of forming spacers on the sidewalls of a patterned mask layer and a pad oxide layer, and then etching the substrate to form a trench using the mask layer and the spacers as a mask. Thereafter, a buffer layer conformal to the surface profile of the device is formed over the substrate, and then an insulation layer is formed inside the trench. The spacers can prevent the etching of the insulation layer to form recess cavities at the upper corners of the trench when the pad oxide layer is removed in an etching operation. Hence, the kink effect is prevented. The buffer layer can prevent the oxidation of trench sidewalls when the insulation layer is densified in an oxygen-filled atmosphere. Moreover, the buffer layer can also prevent sideways etching of the insulation layer when the pad oxide layer is etched.

Abstract: An improved method for forming shallow trench isolation structure is described. The present method comprises the steps of providing a pad oxide layer and a mask layer on a semiconductor substrate and forming a trench structure therein. Next, a liner oxide layer is formed on the surface of the trench structure in the semiconductor substrate and is extensively formed on the side surface of the mask layer exposed therein and the top surface of the mask layer by wet oxidation. A dielectric material is deposited on the liner oxide layer and fills the trench structure. The dielectric material layer is planarized. The mask layer and the pad oxide layer are then removed to form the isolation structures. The method for forming the shallow trench structures on a semiconductor structure in accordance with the present invention can eliminate the kink effect that occurs in the conventional method.

Abstract: A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then, a first silicon nitride layer is patterned on the first silicon dioxide layer, over the top of the polysilicon layer. Then, a second silicon nitride layer is formed on the first silicon dioxide layer and the first silicon nitride layer. Next, a second silicon dioxide layer is formed on the second silicon nitride layer. Then, an etching technique is used to form the side-wall spacers. The side-wall spacers composed of silicon nitride layer and silicon dioxide layer. A dielectric layer is formed on the cap layer, side-wall spacers and silicon dioxide layer. An etch with high selectivity is used to etch the dielectric layer to create a contact hole.

Abstract: Shallow trench isolation regions in a semiconductor device are formed by utilizing sacrificial spacers such as polysilicon spacers having a rounded shape to form trench isolation areas. The spacer shape is transferred into a semiconductor substrate during an etching process to define the profile of the trench, resulting in a trench with substantially rounded upper and lower corners in the substrate. An oxide filler material is deposited in the trench and over the substrate to form a covering layer. The covering layer is then polished back to form a filled trench region which electrically isolates active areas in the substrate. The polishing step can be performed by a blanket dry etching procedure, or by a combination of chemical/mechanical planarization and wet etching. The rounded shape of the trench improves the electrical characteristics of the trench such that current leakage is decreased, and also provides a more optimized trench profile for filling the trench with the filler material.