Abstract: One aspect of the present invention relates to a method of forming trench isolation regions within a semiconductor substrate, involving the steps of forming trenches in the semiconductor substrate; depositing a semi-conformal dielectric material over the substrate, wherein the semi-conformal dielectric material has valleys positioned over the trenches; forming an inorganic conformal film over the semi-conformal dielectric material; polishing the semiconductor substrate whereby a first portion of the inorganic conformal film is removed thereby exposing a portion of the semi-conformal dielectric material, and a second portion remains over the valleys of the semi-conformal dielectric material; removing the exposed portions of the semi-conformal dielectric material; and planarizing the substrate to provide the semiconductor substrate having trenches with a dielectric material therein.

Abstract: A method for filling a trench extending through a microelectromechanical system (MEMS) device patterned on a wafer is disclosed. The method involves simultaneously depositing a trench-fill layer of insulating material over a first side of the wafer, over a second side of the wafer, and into the trench extending from the first side to the second side. Further, the width of the trench at the first side of the wafer and/or the second side of the wafer is variable to adjust the rate at which the trench fills.

Abstract: A method of forming a shallow trench isolation structure. A pad oxide layer and a mask layer are sequentially formed over a substrate. A portion of the pad oxide layer, mask layer and substrate are removed to form a trench in the substrate. A first stage high-density plasma chemical vapor deposition having a high etching/deposition ratio is conducted to form a layer of insulation material over the substrate. A second stage high-density plasma chemical vapor deposition having a lower etching/deposition rate is conducted to form a second layer of insulation material over the substrate and completely fills the trench. Insulating material outside the trench region is removed. Finally, the mask layer and the pad oxide layer are sequentially removed to form a complete STI structure.

Abstract: A non-volatile semiconductor memory device includes a plurality of trenches for element-isolation formed on the main surface of a semiconductor substrate, a nitrided silicon layer formed along the wall surface of the trench, a silicon oxide film for element-isolation formed in the trench, a thermal oxide film extending from the aforementioned main surface located at the periphery of the nitrided silicon layer onto the nitrided silicon layer, the thickness of a portion located on the nitrided silicon layer of which is not less than the thickness of a portion located at the periphery of nitrided silicon layer, a floating gate electrode formed on the thermal oxide film, an insulating film, and a control gate electrode.

Abstract: A method of fabricating shallow trench isolation. A liner silicon nitride layer and a liner silicon oxide layer are used as a hard mask to etch a semiconductor substrate, forming a shallow trench. Then, after forming a thermal oxide film on the inner wall of the shallow trench, a silicon rich oxide is formed using HDPCVD with no bias application. A silicon oxide layer is then formed to fill the shallow trench using HDPCVD with bias application.

Abstract: A trench is etched through the layers of pad oxide and silicon nitride that have been deposited on a substrate, the patterned layer of photoresist is left in place. A tilt angle nitrogen implant is performed into the surface of the substrate, a deep shallow STI trench is etched into the surface of the substrate. An oxygen implant of moderate intensity is performed in the created STI trench, the photoresist is removed. An anneal is performed on the implanted oxygen. A liner oxide is grown within the opening, High Density Plasma (HDP) oxide is deposited inside the opening and the top surface of the remaining silicon oxide. CMP is performed to the surface of the HDP oxide down to the surface of the pad oxide that completes the formation of the STI region under the first embodiment of the invention. The invention can be further extended by creating a LOCOS layer at the bottom of the STI opening or by further etching the bottom of the STI opening.

Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

Abstract: A shallow trench isolated integrated circuit may be formed by creating an oxidation enhancing region at the corner between a semiconductor structure surface and the trench. This region may be formed by ion implantation or solid source diffusion in a way which decreases crystallographic defects. As a result, oxidation at the trench may be enhanced without adverse effects on leakage currents. In some embodiments, the impurity laden region is formed first and the trench is etched through the region leaving an impurity laden remnant at the corner between the trench and the structure surface.

Abstract: A silicon-containing polymer is deposited in a recess on the surface of the substrate. The substrate is then heated to a given temperature. The surface of the substrate, heated to the given temperature and having the silicon-containing polymer deposited thereon, is subjected to gas or vapor activated by a plasma or other electromagnetic radiation which is distinct from a source of heat used to heat the substrate to the given temperature.

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by forming a trench isolation structure with a void-free trench plug (36). In one embodiment, a polysilicon layer (28) is formed within a trench (22) and then subsequently oxidized to form a first dielectric layer (30). The first dielectric layer (30) is then etched and a second dielectric layer (34) is subsequently formed over the etched dielectric layer (32). A portion of the second dielectric layer (34) is then removed using chemical-mechanical polishing to form a void-free trench plug (36) within the trench (22). In addition, reliability is also improved by minimizing subsequent etching of trench plug (36) after it has been formed.

Abstract: A highly reliable semiconductor device is provided. A silicon nitride film having an opening is formed on a main surface of a silicon substrate. The opening is formed with a side surface. The silicon substrate is etched using the silicon nitride film as a mask to form a trench. The side surface of the silicon nitride film is altered in quality to form a silicon oxide film. A silicon oxide film filling the trench is formed in contact with the silicon oxide film. The silicon nitride film is removed with the silicon oxide film in contact with the silicon oxide film remaining.

Abstract: The elements and the trenches are arranged alternately, in repetition, on the main surface of a semiconductor substrate, each of the plurality of elements arranged alternately, in repetition, with the trenches has a configuration (for example, STM) which operates in the same operational mode, and an insulating layer, which is filled into the trenches, and doesn't have a void at a position (the position shallower than the broken line L) shallower than the pn junction to which the largest electric field in the element is applied. Thereby, a semiconductor device and a process for the same, where voids inside of the trenches can be reduced and the film thickness of the insulating film, for filling in the trenches which remain on the surface of the semiconductor substrate, can be made thinner, can be gained through a simple method.

Abstract: A method for manufacturing shallow trench isolation (STI) structures in semiconductor device manufacturing including a method for minimizing divot formation in a shallow trench isolation process is disclosed. A trench liner oxide is deposited and then removed and recessions adjacent a trench are formed to be replaced by an etching resistant layer which covers the recessions to form a protective collar over the trench opening corners.

Abstract: To reduce dislocations produced in the formation of shallow trench isolation regions in a semiconductor substrate, the semiconductor substrate is annealed in N2 ambient pressure with an O2 partial pressure of less than about 10−4 at a temperature between about 950 C.° and about 1055 C.°. In addition, a method to reduce crystalline defects in semiconductor manufacturing in which a metal is deposited on an insulator to form metal silicide is provided. The method provides for etching the insulator to create an overhang by an amount equal to at least one half of the thickness of the metal, thereby creating a void between the surface of the semiconductor substrate and the insulator. The metal is deposited on the first insulator and on the surface of the semiconductor substrate and the semiconductor substrate is heated thereby forming metal silicide on the surface of the substrate.

Abstract: The present invention provides a method of retarding oxidation rate of a side-wall of an isolation device. The method comprises providing a semiconductor substrate having at least a trench structure thereon. The trench structure is filled with an insulating material to form the isolation device and then the isolation device is subjected to dry oxidation whereby retards the oxidation rate of the side-wall of the isolation device. The stress and encroachment effects on the active regions nearby the isolation device can be reduced because of the retarded oxidation rate.

Abstract: STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings.

Abstract: A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.

Abstract: A method of manufacturing semiconductor device is provided which can minimize the thinning of a nitride layer in the planarization process and inhibit the peripheral area of the nitride layer from being excessively polished. The method of manufacturing semiconductor device includes the steps of: forming a nitride layer on a semiconductor substrate; patterning the nitride layer and etching the semiconductor substrate while masking with a pattern of the nitride layer to form a trench; depositing an oxide layer to fill the trench and cover the nitride layer; patterning a resist layer on the oxide layer; etching the oxide layer on the nitride layer; and planarizing the oxide layer, wherein the step of etching the oxide layer permits a thickness of the oxide layer to be left on the nitride layer.

Abstract: A method for filling an isolation trench in a semiconductor substrate includes the steps of forming a first silicon oxide layer on sidewalls and the floor of each trench by an oxidation step, forming a second silicon oxide layer on the sidewalls and floor of the trench by a first high-density plasma-chemical vapor deposition process without applying an RF voltage to a wafer so that the ratio of depositing to etching is extremely high and then forming a third silicon oxide layer by a second high-density plasma-chemical vapor deposition process having an RF voltage applied to the wafer so that the ratio of depositing to etching is much lower than in the first-mentioned process.

Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Abstract: A method for forming a trench having upper rounded corners comprising the following steps. A substrate having an oxide layer formed thereover is provided. A hard mask layer is formed over the oxide layer. A patterned patterning layer is formed over the hard mask layer leaving one or more portions of the hard mask layer exposed. The hard mask layer is patterned using the patterned patterning layer as a mask to form a patterned hard mask layer having one or more openings exposing one or more portions of the oxide layer. The patterned patterning layer is removed. The oxide layer is patterned using the patterned hard mask layer as a mask using a first trench etching process to etch through the oxide layer at the one or more exposed portions of the oxide layer and into the substrate to form one or more shallow trenches within the substrate having upper rounded corners at the respective interfaces between substrate and patterned oxide layer.

Abstract: A transparent substrate with a multilayer antireflection film having electrical conductivity is disclosed. On a polycarbonate substrate (a refractive index of 1.58).with a hard coat, a first thin-film layer whose main Component is SiO2 is formed with a thickness of 142.5 nm (approx. &lgr;/4 for a wavelength of 550 nm). A second thin-film layer whose main component is TiO2 is formed with a thickness of 124.0 nm on the first thin-film layer. Furthermore, a third thin-film layer whose main component is indium tin oxide (ITO) is formed with a thickness of 150.0 nm on the second thin-film layer.

Abstract: A trench is formed on a primary surface of a semiconductor substrate, and is filled with trench material to separate the surface region of the semiconductor substrate into plural active regions. At least a portion of the surface of the trench material adjoining the semiconductor substrate is depressed by a predetermined depth with reference to the primary surface of the semiconductor device. Thus, prevented is a decrease in a drain current of a semiconductor device having a trench isolation structure.

Abstract: A method for forming an isolation layer in a semiconductor device, to avoid the occurrence of an angular formation phenomenon at the edge portions of the upper and lower portions of the trench during formation of a shallow trench isolation layer (STI), so that malfunction of the device and the deterioration of its performance due to a parasitic transistor and leakage current, can be prevented. Advantageously, silicon nitride films are formed at the side wall of the pad oxide film and the surface of trench silicon through a nitrogen (N+) plasma nitrification process, after a trench etching process, for formation of STI, so that the generation of a moat is inhibited and deterioration of the device is prevented.

Abstract: A method of manufacturing a semiconductor device including a plurality of active regions of different area and device isolation regions formed between the active regions, the method including the steps of: forming a first insulating film and a second insulating film in sequence on a semiconductor substrate; forming a plurality of openings through the first and second insulating films at desired positions; forming trenches in the semiconductor substrate in the openings to define active regions of different area and device isolation regions between the active regions; depositing a third insulating film on the semiconductor substrate so that the trenches are filled with the third insulating film; flattening the third insulating film by CMP until the second insulating film is exposed in the active regions; and removing the third insulating film remaining in the active regions because of a difference in polishing rate derived from variation in deposit density in the third insulating film and simultaneously reducin

Abstract: A method for forming an isolation trench in a semiconductor substrate is provided. An isolation trench is formed in a semiconductor substrate using a trench etch mask pattern. Sidewall spacers are formed on the sidewalls of the trench. A nitride liner is formed over the sidewall spacers. The trench is filled with a trench isolation material. Because the nitride liner is protected, for example, by the sidewall spacers, the formation of a dent in the nitride liner can be prevented.

Abstract: Disclosed is a method of filling an isolation trench etched through a silicon nitride layer down into a silicon substrate, comprising performing a first pullback of said nitride layer away from said trench so as to expose trench comers of said trench so as to optimize comer rounding as desired, provided a silicon oxide trench liner for said trench, performing a second pullback of said silicon nitride layer away from said trench so as to expose a sufficient amount of underlying layer adjacent to said trench comers to effectively protect said trench comers with a subsequent protective fill, providing said protective fill of sufficient thickness to fill said trench and cover said substrate adjacent to said trench corners.

Abstract: A semiconductor device including an insulating film (6) embedded in a concave portion, such as a trench (T) formed on a semiconductor substrate (1) is disclosed. A method of forming a trench isolation structure may include forming a mask layer having a predetermined opening pattern. The mask layer may include a nitride film (3). A trench (T) may be formed through etching using a mask layer as a mask. A thermal oxide film (4) may be formed on an inner wall of a trench (T). An insulating film (11) may be formed on an entire main surface of a semiconductor substrate (1). Insulating film (11) may provide an etching barrier. A nitride film liner (5) may be formed on an insulating film (11). An embedding insulating film (6) may be formed so as to essentially fill trench (T). A planarization treatment may be conducted so as to expose nitride film (3). Nitride film (3) may then be removed by isotropic etching.

Abstract: A semiconductor device including an insulating film (6) embedded in a concave portion is disclosed. A nitride film liner (3) may be formed inside a concave portion formed in a semiconductor substrate (1). An anti-static insulating film (10) may be formed on nitride film liner (3) by a thermal chemical vapor deposition (CVD) method. Embedded insulating film (6) may be formed on the anti-static insulating film (10) by a high-density plasma CVD method so as to essentially fill the concave portion. In this way, peeling off of insulating film (6) may be reduced and a formation of a groove in a trench isolation structure may be suppressed.

Abstract: A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

Abstract: A method for shallow trench isolation formation having a thick un-biased HDP USG liner layer to reduce HDP-CVD induced defects is described. Trenches are etched through an etch stop layer into a semiconductor substrate. The semiconductor substrate is thermally oxidized to form a thermal liner layer within the isolation trenches. The isolation trenches are filled using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein the HDP-CVD process comprises: first depositing a first liner layer overlying the thermal liner layer wherein no bias power is supplied during the first depositing step and wherein the first liner layer has a thickness of between 200 and 400 Angstroms, second depositing a second liner layer using low bias power, and third depositing a gap filling layer overlying the second liner layer to fill the isolation trenches. The gap filling layer is polished back overlying the etch stop layer.

Abstract: The present invention provides a method of rounding the corner of the shallow trench isolation region, comprising the steps of: etching silicon substrate using a patterned mask layer and a pad oxide layer as an etch mask to form a trench in the silicon substrate, then removing part of the pad oxide layer, forming silicon dioxide on the surface of the silicon substrate in the trench, then removing part of the pad oxide layer and the silicon dioxide on the surface of the silicon substrate in the trench, repeating the step of oxidizing the surface of the silicon substrate and removing part of the pad oxide layer and silicon dioxide to round the corner of the trench, then performing the subsequent steps to form the shallow trench isolation region.

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. The upper regions are covered by a masking layer of nitride having a predetermined thickness. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to a thickness terminating within that of the thickness of the nitride layer. The raised regions of the filler material are then selectively removed in a single planarizing step without removing the filler material in the lowered regions using a fixed abrasive hard polishing pad, as opposed to an abrasive slurry.

Abstract: The present invention is the first one to disclose using of a polysilicon layer in lieu of a silicon nitride (Si3N4) layer, and forming a spacer as a buffering layer by oxidation of polysilicon in oxidation of shallow trenches to protect insulation corners of the shallow trenches (STI corners). This not only omits the process to form and to remove a polymer spacer, but also protects insulation comers of the shallow trenches by forming the polysilicon spacer by oxidation, thereby avoids exposing of the STI comers which results abnormal electricity conductivity.

Abstract: A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.

Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

Abstract: A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends out from the surface. A second substrate portion is disposed on the insulator region, and a second active region is disposed in the second substrate portion. Thus, by disposing a portion of the substrate on the isolation region, the usable substrate area is dramatically increased.

Abstract: A method for forming shallow trench isolation is disclosed. A pad oxide layer and a mask layer are sequentially formed on a substrate. Afterwards, an opening is formed through the mask layer and the pad oxide layer such that regions of the substrate are exposed. Thereafter, the exposed regions are etched to form trenches inside said substrate. Next, nitrogen ions are implanted into the sidewall of the trenches to form a silicon nitride layer, and then a siliconoxynitride layer is formed inside the sidewall of the trenches. Subsequently, a silicon oxide layer is formed on the siliconoxynitride layer and on the mask layer. The excess portion of the silicon oxide layer over said mask layer is removed to expose the mask layer, and then the mask layer is removed away. Finally, the pad oxide layer is removed by using hydrofluoric acid (HF).

Abstract: A method of providing a substantially planar trench isolation region having substantially rounded corners, said method comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a nitride layer; (b) patterning said film stack to form at least one trench within said substrate, wherein said patterning exposes sidewalls of said oxide layer, polysilicon layer and nitride layer; (c) oxidizing the at least one trench and said exposed sidewalls of said oxide layer and said polysilicon layer so as to thermally grow a conformal oxide layer in said trench and on said exposed sidewalls of said oxide layer and said polysilicon layer; (d) filling said trench with a trench dielectric material; and (e) planarizing to said surface of said substrate.

Abstract: The formation of the isolating region includes ion implantation in the voluminal part, followed by annealing of said implanted voluminal part (7) of the substrate (1).

Abstract: Microelectronic substrate assemblies are planarized using methods, planarizing solutions and planarizing machines according to various embodiments of the present invention. A substrate is assembly pressed against a planarizing surface of a fixed-abrasive polishing pad, covering an operative portion of the planarizing surface with a non-abrasive planarizing solution, and moving the substrate assembly and/or the polishing pad with respect to the other. The fixed-abrasive polishing pad includes a body having a suspension medium and abrasive particles fixedly attached to the suspension medium at the planarizing surface. The substrate assembly is a stop-on-feature device including a substrate, a polish-stop layer formed over the substrate to conform to a topography of features on the substrate, and a cover layer formed over the polish-stop layer.

Abstract: The present invention provides a method of forming a shallow trench isolation structure in a substrate. The method comprises the steps of: forming an isolation silicon oxide film which comprises an upper portion extending over a silicon oxide film over a silicon nitride film and a lower portion extending in a trench in a silicon substrate; and carrying out an isotropic etching to said upper portion of said isolation silicon oxide film and said silicon oxide film, thereby forming an isolation trench structure without divots in said trench in said silicon substrate.

Abstract: A method for forming a high performance photodiode with tightly-controlled junction profile for CMOS image sensor with STI process. The following steps are performed: providing a substrate; forming a hard mask layer for defining a pattern on the substrate; etching the substrate on the surface of the substrate not covered by the hard mask layer to form a shallow trench; growing an oxide lining in the shallow trench by a thermal oxidation process; performing a first thermal annealing; defining an n-well region in the shallow trench; implanting the n-well region; performing a second thermal annealing; forming a silicon oxide layer on the substrate to fill in the shallow trench; removing a portion of the silicon oxide layer on the substrate such that the portion in the shallow trench remains; removing the hard mask layer; and forming a transistor on the substrate, wherein the transistor comprises a gate structure, a source region, and a drain region.

Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of: defining an isolation region on a layer of silicon oxide overlying a silicon layer; selectively etching the silicon to provide the isolation region; growing thermal oxide over the interior surfaces of the isolation structure; depositing dielectric conformingly; and oxidizing the deposited dielectric.

Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.

Abstract: In an SOI integrated circuit employing shallow trench isolation, the walls of the transistor active area have a nitridized oxide layer grown on them, thereby preventing the diffusion of dopants out of the transistor body and preventing a shift in threshold voltage.

Abstract: A method to form shallow trench isolations with reduced substrate defects by using a nitrogen anneal is achieved. A silicon substrate is provided. The silicon substrate is etched where not protected by a photoresist mask to form shallow trenches where shallow trench isolations are planned. A liner oxide layer is grown on the interior surfaces of the shallow trenches. The silicon substrate and the liner oxide layer are annealed to reduce or eliminate defects, dislocations, interface traps, and stress in the silicon substrate. An isolation oxide layer is deposited overlying the liner oxide layer and completely filling the shallow trenches. The isolation oxide layer is etched down to the top surface of the silicon substrate and thereby forms the shallow trench isolations. The integrated circuit device is completed.