Abstract: Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

Abstract: A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.

Abstract: A method and a corresponding device for bonding a first substrate with a second substrate at mutually facing contact faces of the substrates. The method includes holding of the first substrate to a first holding surface of a first holding device and holding of the second substrate to a second holding surface of a second holding device. A change in curvature of the contact face of the first substrate and/or a change in curvature of the contact face of the second substrate are controlled during the bonding.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.

Abstract: Provided a manufacturing method of a semiconductor light emitting device including forming a plurality of light emitting cells that are separated on a first substrate, forming a first planarization layer by providing an insulating material on the plurality of light emitting cells, forming a second planarization layer by providing a photoresist on the first planarization layer to have a flat upper surface, and soft baking the photoresist, and dry etching the second planarization layer to a predetermined depth to expose a portion of the first planarization layer provided on the plurality of light emitting cells, and a portion of the second planarization layer remaining between the plurality of light emitting cells on the first planarization layer, wherein forming the second planarization layer and dry etching are repeated at least once to remove the portion of the second planarization layer provided between the plurality of light emitting cells.

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory level, where the first memory level includes a first thinned single crystal substrate; a second memory level, the second memory level disposed on top of the first memory level, where the second memory level includes a second thinned single crystal substrate; and a memory control level disposed on top of the second memory level, where the memory control level is bonded to the second memory level, and where the bonded includes oxide to oxide and conductor to conductor bonding.

Abstract: In fabricating a semiconductor structure, a group IV substrate and a group III-V chiplet are provided. The group III-V chiplet is bonded to the group IV substrate, and patterned to produce a patterned group III-V device. A blanket dielectric layer is formed over the patterned group III-V device. A first contact hole is formed in the blanket dielectric layer over a first portion of the patterned group III-V device. A first liner stack and a first filler metal are subsequently formed in the first contact hole. A second contact hole is formed in the blanket dielectric layer over a second portion of the patterned group III-V device. A second liner stack and a second filler metal are subsequently formed in the second contact hole. A first bottom metal liner of the first liner stack can be different from a second bottom metal liner of the second liner stack.

Abstract: A method and apparatus for delaminating a polymer film from a carrier plate is disclosed. The carrier plate is at least partially transparent and has deposited on it a pixelated pattern layer of light-absorptive material, upon which is deposited a layer of light-reflective material. A polymer film, which is to be delaminated, is deposited on the light-reflecting material layer. Next, a pulsed light source is utilized to irradiate through the carrier plate from the side opposite the polymer film to heat the light-absorptive material layer. The heated areas of the light-absorptive material layer, in turn, heat the polymer film through conduction at the interface between the light-absorptive material layer and the polymer film, thereby generating gas from the polymer film by its thermal decomposition, which allows the polymer film to be released from the carrier plate.

Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes an antenna layer having a feeding region and an insulating layer disposed on the antenna layer. The insulating layer has a first portion in contact with the antenna layer and a second portion on the first portion. The first portion and the second portion of the insulating layer define a stepped structure exposing the feeding region of the antenna layer. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: A method for transferring a superficial layer from a detachable structure comprises the following steps: a) supplying the detachable structure comprising: •a support substrate, •a detachable layer arranged on the support substrate along a main plane and comprising a plurality of walls that are separated from one another, each wall having at least one side that is perpendicular to the main plane; •a superficial layer arranged on the detachable layer along the main plane; b) applying a mechanical force configured to cause said walls to bend, along a direction that is secant to said side, until causing the mechanical rupture of the walls, in order to detach the superficial layer from the support substrate.

Abstract: Provided herein is a method including forming a MEMS cap. A cavity is formed in the MEMS cap wafer, and a bond material is deposited on the MEMS cap wafer, wherein the bond material lines the cavity after the depositing. The MEMS cap wafer is bonded to a MEMS device wafer, wherein the bond material forms a bond between the MEMS cap wafer and the MEMS device wafer. A MEMS device is formed in the MEMS device wafer. The bond material is removed from the cavity.

Abstract: A method of healing defects generated in a semiconducting layer by implantation of species made in a substrate to form therein an embrittlement plane separating a solid part of the substrate from the semiconducting layer, the semiconducting layer having a front face through which the implanted species pass. The method comprises local annealing of the substrate causing heating of the semiconducting layer, the intensity of which decreases from the front face towards the embrittlement plane. The local annealing may comprise a laser irradiation of a front surface of the substrate.

Abstract: A wafer/support arrangement, including a wafer, a support system, which includes a support and an elastomer layer, and a connecting layer, wherein the connecting layer is a sol-gel layer. The invention further relates to a coated wafer for a wafer/support arrangement according to the invention, wherein a sol-gel layer is used as a connecting layer for a corresponding wafer/support assembly, and to a method for processing the back side of a wafer.

Abstract: A backlight module having a surface light source, a liquid crystal display panel, and a welding method of a light-emitting diode chip are provided. The backlight module having a surface light source including: a first pad and a second pad disposed on a substrate; a plurality of pad holes disposed in the first pad and the second pad; a magnetic film layer disposed in the plurality of pad holes; a solder paste disposed both on the first pad and the second pad; a light-emitting diode chip, wherein a plurality of pins disposed on two sides of the light-emitting diode chip are absorbed on the magnetic film layer and are connected to both the first pad and the second pad respectively by the solder paste.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: A physical quantity sensor includes a first substrate, an electrode provided on the first substrate, a diaphragm made of semiconductor material, a second substrate fixed to the first substrate, a dielectric film provided on the diaphragm, and a wall provided between the dielectric film and the electrode. The second substrate supports the diaphragm such that the diaphragm has an opposing surface facing the electrode across a space. The dielectric film is provided on the opposing surface of the diaphragm. The dielectric film has a surface facing the electrode across the space. The wall includes a first protrusion and a second protrusion. The first protrusion protrudes toward the electrode from the surface of the dielectric film. The second protrusion protrudes toward the electrode from the first protrusion, and contacts the electrode. The second protrusion is made of material which is different from material of the dielectric film.

Abstract: A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding.

Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.

Abstract: According to one embodiment, a controller is configured to calculate a matching rate of grid shapes between each semiconductor wafer of a first semiconductor wafer group and each semiconductor wafer of a second semiconductor wafer group, and generate pairing information, into which combinations of semiconductor wafers used in calculation of matching rates are registered when the matching rates fall within a predetermined range. Further, the controller is configured to select a first semiconductor wafer to be held by a first semiconductor wafer holder from the first semiconductor wafer group, and select a second semiconductor wafer from semiconductor wafers of the second semiconductor wafer group, which are paired with the first semiconductor wafer, with reference to the pairing information.

Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.

Abstract: A method to perform hybrid bonding of two semiconductor wafers without using a dedicated tool for thermo-compression is disclosed. According to the herein disclosed technique, the semiconductor wafers to be bonded together may be placed in an oven simply staying one upon the other without applying any additional compression between them besides their own weight. This outstanding result has been attained using of a particular type of thermosetting materials, namely siloxane polymers of the type that shrink when cured. Among these siloxane polymers, the siloxane polymers of the type SC-480, siloxane polymers of the series SC-200, SC-300, SC-400, SC-500, SC-700, SC-800 and mixtures thereof are particularly suitable.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.

Abstract: A packaging paperboard is provided that includes two or more layers with an antenna pattern printed on one layer of the two or more layers, and an RFIC element adhered to the other layer of the two or more layers. In a laminate having the layers stuck together, the RFIC element and the antenna pattern are interposed between the layers to configure an RFIC device in which the RFIC element and the antenna pattern are electrically connected.

Abstract: A method of manufacturing the flexible device includes: forming a photosensitive film on a hard base substrate, the photosensitive film including a photosensitive resin material containing azide; forming a base including an inorganic material on the photosensitive film; forming an electronic device functional layer on the base; forming an encapsulation layer on the electronic device functional layer; irradiating the photosensitive film at a side of the base substrate away from the encapsulation layer; and peeling off an entire structure including the base, and the electronic device functional layer and the encapsulation layer that have been formed on the base from the photosensitive film.

Abstract: A system includes a structure bonding layer and a sensor. The structure bonding layer is disposed on a structure. The structure bonding layer is a metallic alloy. The sensor includes a non-metallic wafer and a sensor bonding layer disposed on a surface of the non-metallic wafer. The sensor bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer.

Abstract: An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalk form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalk and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.

Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.

Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected within the broken via pillar to the second continuous via pillar portion. Each of the plural chips has one or more of the bridges. Each bridge connects, within the respective chip, the first continuous via pillar portion in a column and the second continuous via pillar portion in another column.

Abstract: A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

Abstract: The present invention provides a method for manufacturing a backlight source. The method for manufacturing a backlight source according to the present invention forms a plurality of tin soldering pattern groups on a substrate. Each tin soldering pattern group includes tin soldering patterns spaced from one another, and the tin soldering patterns are in a closed ring shape. The Mini-LEDs are disposed on the tin soldering pattern groups respectively. The substrate is placed in the space having a varying magnetic field. The circuit of the tin soldering patterns in the tin soldering pattern groups generates the induced current for rapid heating and melting, to solder the Mini-LEDs on the substrate. The soldering speed is improved, the process efficiency is high, the process cost is low, and the light effect of the backlight source is effectively ensured.

Abstract: A stretchable display device includes a stretchable substrate including a plurality of island areas that are separated from each other and a hinge area connecting the plurality of island areas, a plurality of display units respectively located in each of the plurality of island areas, a wiring part connecting the plurality of display units and located at the hinge area, and an insulating layer between the stretchable substrate and the plurality of display units. The insulating layer includes an opening overlapping the hinge area.

Abstract: Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

Abstract: A process includes the successive steps of: a) providing first and second substrates, each including a first surface and an opposite, second surface, lateral edges connecting the first and second surfaces, b) bonding the first substrate to the second substrate by direct bonding with the first surfaces of the first and second substrates so as to form a bonding interface (IC), and making the lateral edges of the first and second substrates hydrophobic on either side of the bonding interface (IC).

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.

Abstract: A device for bonding of a second substrate onto a first substrate, comprising a receiving apparatus for receiving the first substrate which has been coated with a bond layer and the second substrate which is held on the bond layer, and an action apparatus for applying a bond force to the second substrate on one action side of the second substrate, which side faces away from the bond layer proceeding from an initial zone A, which lies within an edge zone R of the action side as far as action on the entire action side. Furthermore, this invention relates to a corresponding method.

Abstract: A substrate bonding apparatus for bonding a first substrate to a second substrate includes: a first bonding chuck including: a first base; a first deformable plate provided on the first base to support the first substrate; and a first pneumatic adjustor configured to deform the first deformable plate by adjusting a first pressure in a first cavity formed between the first deformable plate and the first base; and a second bonding chuck including: a second base; a second deformable plate provided on the second base to support the second substrate; and a second pneumatic adjustor configured to deform the second deformable plate by adjusting a second pressure in a second cavity formed between the second deformable plate and the second base.

Abstract: A method for manufacturing a display device is disclosed, the method at least includes the following step: Firstly, a temporary substrate is provided, a hydrogen containing structure is formed on the temporary substrate, a polymer film is formed on the hydrogen containing structure, and a display element is formed on the polymer film. Afterwards, a laser beam process is performed, to focus a laser beam on the hydrogen containing structure, and the temporary substrate is then removed.

Abstract: A method for processing a silicon carbide wafer includes implanting ions into the silicon carbide wafer to form an absorption layer in the silicon carbide wafer. The absorption coefficient of the absorption layer is at least 100 times the absorption coefficient of silicon carbide material of the silicon carbide wafer outside the absorption layer, for light of a target wavelength. The silicon carbide wafer is split along the absorption layer at least by irradiating the silicon carbide wafer with light of the target wavelength to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

Abstract: An electronic-component manufacturing method is for simultaneously manufacturing a plurality of electronic components each including an element body and a conductor. The electronic-component manufacturing method includes the steps of forming laminates to be the plurality of electronic components on a plurality of regions set apart from each other on a surface of a first substrate, releasing the laminates from the plurality of regions, and performing heat treatment to the laminates. The forming the laminates includes a first step of forming element-body patterns on the plurality of regions and a second step of forming conductor patterns on the plurality of regions. The element-body patterns contain a constituent material of the element bodies and are patterned for the plurality of regions. The conductor patterns contain a constituent material of the conductors and are patterned for the plurality of regions.

Abstract: A bonded wafer including an ion implantation step using a batch processing ion implanter, wherein the ion implantation step is performed by irradiating a bond wafer with a light element ion beam without forming an insulator film on the bond wafer surface or through an insulator film having a thickness of 50 nm or less formed on the bond wafer surface at an implantation angle inclined from a crystal axis of the bond wafer; and the bond wafer surface is irradiated with the center of the light element ion beam shining at a position on the bond wafer surface shifted from the center of the bond wafer parallel to the center of a rotor by a predetermined amount providing a bonded wafer to prevent degradation of the radial uniformity of ion implantation depth and manufacture a bonded wafer with excellent radial uniformity of thickness of a thin film after delamination.

Abstract: In a method of debonding a carrier substrate from a device substrate, an ultraviolet (UV) light may be irradiated to an adhesive tape through the carrier substrate, which may be attached to a first surface of the device substrate having a connection post using the adhesive tape, to weaken an adhesive force of the adhesive tape. An outskirt portion of the carrier substrate may be masked to concentrate the UV light on the adhesive tape.

Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.

Abstract: In a general aspect, a vapor cell is presented that includes a dielectric body. The dielectric body has a surface that defines an opening to a cavity in the dielectric body. The vapor cell also includes a vapor or a source of the vapor in the cavity of the dielectric body. An optical window covers the opening of the cavity and has a surface bonded to the surface of the dielectric body to form a seal around the opening. The seal includes metal-oxygen bonds formed by reacting a first plurality of hydroxyl ligands on the surface of the dielectric body with a second plurality of hydroxyl ligands on the surface of the optical window.

Abstract: Methods and apparatus for use in the manufacture of a display element. Some embodiments include a method for selective pick up of a subset of a plurality of electronic devices adhered to a handle layer. The method comprises modifying a level of adhesion between one or more electronic devices of the plurality of electronic devices adhered to the handle layer, such that the subset of the plurality of electronic devices has a level of adhesion to the handle layer that is less than a force applied by a pick up tool, PUT. This enables selective pick up of the subset of the plurality of electronic devices from the handle layer by the PUT.

Abstract: A semiconductor wafer comprising single-crystal silicon has defined concentrations of oxygen, nitrogen and hydrogen; the semiconductor wafer further contains BMD seeds having a density averaged over the radius of not less than 1×105 cm?3 and not more than 1×107 cm?3; surface defects having a density averaged over the radius of not less than 1100 cm?2; and BMDs, whose density is not lower than a lower limit of 5×108/cm3. The semiconductor wafers are produced by a process which enables obtention of the required ranges of concentrations of oxygen, nitrogen, hydrogen, BMD seeds, and BMD's.

Abstract: A 3D semiconductor device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a trap-rich layer disposed between the first level and the second level; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the plurality of connection paths includes vertical connections connecting from the first interconnections to the second interconnections, where the third layer includes crystalline silicon, and where the second level is bonded to the first level.

Abstract: A composite includes a component and a glass or glass ceramic material. The component has a first coefficient of expansion ?1 and the glass or the glass ceramic material has a second coefficient of expansion ?2. The glass or the glass ceramic material has a surface with a thickness and thickness differences (TTV) within the surface, and thickness fluctuations (LTV). The composite has a residual stress in the glass or the glass ceramic material (WARP), and a geometric and material-physical degree of compatibility KG?4.

Abstract: An electronic device according to certain embodiments includes a housing, a first glass plate coupled to the housing and defining an inner space, the first glass plate including a peripheral portion including: a first, second, third, fourth, and fifth surface forming an edge of the glass plate, the first and fifth surfaces being substantially parallel and the third surface being substantially perpendicular to the first and fifth surfaces, a decorative layer formed of a first material, disposed on a first area of the fifth surface such that a second area disposed between the fourth surface and the first area is uncovered by the decorative layer, and a protective layer formed of a second material, covering the second surface, the third surface, the fourth surface, the second area of the fifth surface, and a part of the decorative layer.