Abstract: Methods of forming a graphene-based device are provided. According to an embodiment, a graphene-based device can be formed by subjecting a substrate having a dielectric formed thereon to a chemical vapor deposition (CVD) process using a cracked hydrocarbon or a physical vapor deposition (PVD) process using a graphite source; and performing an annealing process. The annealing process can be performed to temperatures of 1000 K or more. The cracked hydrocarbon of the CVD process can be cracked ethylene. In accordance with one embodiment, the application of the cracked ethylene to a MgO(111) surface followed by an annealing under ultra high vacuum conditions can result in a structure on the MgO(111) surface of an ordered graphene film with an oxidized carbon-containing interfacial layer therebetween. In another embodiment, the PVD process can be used to form single or multiple monolayers of graphene.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract: A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation.

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins.

Abstract: A method and apparatus for depositing a film on a substrate includes introducing a material and a carrier gas into a heated chamber. The material may be a semiconductor material, such as a cadmium chalcogenide. A resulting mixture of vapor and carrier gas containing no unvaporized material is provided. The mixture of vapor and carrier gas are remixed to achieve a uniform vapor/carrier gas composition, which is directed toward a surface of a substrate, such as a glass substrate, where the vapor is deposited as a uniform film.

Abstract: Techniques for crack-free growth of GaN, and related, films on larger-size substrates via spatially confined epitaxy are described.

Abstract: A standard wafer is provided including a substrate; a first layer of semiconductor material formed on the substrate; a bar formed over the first layer of semiconductor material with an interlayer interposed therebetween; and a first sidewall spacer and a second sidewall spacer formed on the opposite sides of the bar respectively, in which the bar and the first layer of semiconductor material are formed of a same semiconductor material, and the interlayer interposed between the first layer of semiconductor material and the bar is formed of a first oxide, and the first sidewall spacer and the second sidewall spacer are formed of a second oxide. A corresponding fabrication method of the standard wafer is also provided.

Abstract: A method is for the synthesis of an array of metal nanowires (w) capable of supporting localized plasmon resonances. A metal film (M) deposited on a planar substrate (D) is irradiated with a defocused beam of noble gas ions (IB) under high vacuum, so that, with increasing ion doses a corrugation is produced on the metal film surface, formed by a mutually parallel nanoscale self-organized corrugations (r). Subsequently, the height of the self-organized corrugations peaks is increased relative to the valleys (t) interposed therebetween. Then the whole the metal film is eroded so as to expose the substrate at the valleys, and to mutually disconnect the self-organized corrugations, thereby generating the array of metal nanowires. Finally, the transversal cross-section of the nanowires is reduced in a controlled manner so as to adjust the localized plasmon resonances wavelength which can be associated thereto. The nanowires array constitutes an electrode of an improved photonic device.

Abstract: A method for forming a U-shaped vertically long groove in a region where a channel portion of a transistor is formed to make a channel length longer than an apparent channel length additionally requires a photolithography process for forming a groove; therefore, it has a problem in terms of costs and yield. By forming a three-dimensional channel region with the use of a gate electrode or a structure having an insulating surface, a channel length is made three times or more, preferably five times or more, further preferably ten times or more as long as a channel length when seen from the above.

Abstract: An angled implantation process is used in implanting semiconductor fins of a semiconductor device and provides for covering some but not necessarily all of semiconductor fins of a first type with patterned photoresist, and implanting using an implant angle such that all semiconductor fins of a second type are implanted and none of the semiconductor fins of the first type, are implanted. A higher tilt or implant angle is achieved due to the reduced portions of patterned photoresist, that are used.

Abstract: A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: A method of manufacturing of a semi-conductor element, comprising the following steps: providing a substrate, the substrate having a surface, the surface being partially coated with a coating and having at least one uncoated area, and growing a truncated pyramid of gallium nitride on the uncoated area, wherein the method comprises the following step: growing at least one gallium nitride column on the truncated pyramid.

Abstract: A catalyst film (2) is formed over a substrate (1). A graphene (3) is grown on the catalyst film (2). A gap through which a lower surface of the catalyst film (2) is exposed is formed. The catalyst film (2) is removed through the gap.

Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

Abstract: A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO2 or other oxides, over the polished surface to provide an intermediate structure; and re-polishing the material formed on the intermediate structure to a second degree of smoothness smoother than the first degree of smoothness. The diamond is bonded to the semiconductor structure, such as GaN, by providing a structure having bottom surfaces of a semiconductor on an underlying material; forming grooves through the semiconductor and into the underlying material; separating semiconductor along the grooves into a plurality of separate semiconductor structures; removing the separated semiconductor structures from the underlying material; and contacting the bottom surface of at least one of the separated semiconductor structures to the diamond substrate.

Abstract: Embodiments of the invention provide a crystalline aluminum carbide thin film, a semiconductor substrate having the crystalline aluminum carbide thin film formed thereon, and a method of fabricating the same. Further, the method of fabricating the AlC thin film includes supplying a carbon containing gas and an aluminum containing gas to a furnace, to growing AlC crystals on a substrate.

Abstract: Methods of forming a laminate comprising a sheet of semiconductor material utilize a system. The system comprises a fibrous sheet, a guide member for guiding the fibrous sheet, and a melt of a semiconductor material. The sheet of semiconductor material and a laminate comprising the fibrous sheet and the sheet of semiconductor material are also included.

Abstract: A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide layer of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.

Abstract: A method of manufacturing a semiconductor crystal substrate, includes forming a nitride layer by supplying a gas including a nitrogen component to a substrate formed of a material including silicon and nitriding a surface of the substrate; and forming an AlN layer on the nitride layer by supplying the gas including the nitrogen component and a source gas including Al.

Abstract: Graphene layers can be formed on a dielectric substrate using a process that includes forming a copper thin film on a dielectric substrate; diffusing carbon atoms through the copper thin film; and forming a graphene layer at an interface between the copper thin film and the dielectric substrate.

Abstract: Methods of forming a graphene-based device are provided. According to an embodiment, a graphene-based device can be formed by subjecting a substrate having a dielectric formed thereon to a chemical vapor deposition (CVD) process using a cracked hydrocarbon or a physical vapor deposition (PVD) process using a graphite source; and performing an annealing process. The annealing process can be performed to temperatures of 1000 K or more. The cracked hydrocarbon of the CVD process can be cracked ethylene. In accordance with one embodiment, the application of the cracked ethylene to a MgO(111) surface followed by an annealing under ultra high vacuum conditions can result in a structure on the MgO(111) surface of an ordered graphene film with an oxidized carbon-containing interfacial layer therebetween. In another embodiment, the PVD process can be used to form single or multiple monolayers of graphene.

Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern.

Abstract: A method of connecting to a first metal layer in a semiconductor flow process. Disclosed embodiments connect to the first metal layer by etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer, depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole, and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer.

Abstract: The invention relates to a method for manufacturing a semiconductor on insulator type substrate for radiofrequency applications, comprising the following steps in sequence: (a) provision of a silicon substrate (1) with an electrical resistivity of more than 500 Ohm·cm, (b) formation of a polycrystalline silicon layer (4) on said substrate (1), said method comprising a step between steps a) and b) to form a dielectric material layer (5), different from a native oxide layer, on the substrate (1), between 0.5 and 10 nm thick.

Abstract: The present invention provides a method for producing a Group III nitride semiconductor. The method includes forming a groove in a surface of a growth substrate through etching; forming a buffer film on the groove-formed surface of the growth substrate through sputtering; heating, in an atmosphere containing hydrogen and ammonia, the substrate to a temperature at which a Group III nitride semiconductor of interest is grown; and epitaxially growing the Group III nitride semiconductor on side surfaces of the groove at the growth temperature. The thickness of the buffer film or the growth temperature is regulated so that the Group III nitride semiconductor is grown primarily on the side surfaces of the groove in a direction parallel to the main surface of the growth substrate.

Abstract: An electronic device includes IV material grown on a silicon substrate. The device includes a crystalline silicon substrate and a rare earth structure epitaxially grown on the silicon substrate. The rare earth structure includes a layer of a rare earth oxide with electrical insulating characteristics so that the rare earth structure provides electrical insulation from the silicon substrate. A single crystal IV material film is epitaxially grown on the rare earth structure. The single crystal IV material film includes one of crystal lattice matching or crystal lattice mismatching the IV material film to the rare earth structure.

Abstract: A method for producing a nanoporous layer comprises applying a plating base with adhesion strengthening onto a substrate, depositing a layer made of gold and silver onto the substrate, the composition being in the range of 20% to 40% gold and 80% to 60% silver, and selectively removing the silver in order to produce a nanoporous gold layer.

Abstract: An apparatus (100) for fabricating a semiconductor thin film includes: substrate surface pretreatment means (101) for pretreating a surface of a substrate; organic layer coating means (102) for coating, with an organic layer, the substrate thus pretreated; focused light irradiation means (103) for irradiating, with focused light, the substrate coated with the organic layer, and for forming a growth-mask layer while controlling layer thickness; first thin film growth means (104) for selectively growing a semiconductor thin film over an area around the growth-mask layer; substrate surface treatment means (105) for, after exposing the surface of the substrate by removing the growth-mask layer, modifying the exposed surface of the substrate; and second thin film growth means (106) for further growing the semiconductor thin film and growing a semiconductor thin film over the modified surface of the substrate.

Abstract: Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

Abstract: A method of producing an inorganic multi-layered thin film structure includes providing a substrate. A patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process. A second inorganic thin film material layer is selectively deposited on the region of the substrate where the thin film deposition inhibiting material layer is not present using an atomic layer deposition process.

Abstract: Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.

Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.

Abstract: The method of manufacturing a graphene device includes forming an insulating material layer on a substrate, forming first and second metal pads on the insulating material layer spaced apart from each other, forming a graphene layer having a portion defined as an active area between the first and second metal pads on the insulating material layer, forming third and fourth metal pads on the graphene layer spaced apart from each other with the active area therebetween, the third and fourth metal pads extending above the first metal pad and the second metal pad, respectively, forming a first protection layer to cover all the first and second metal pads, the graphene layer, and the third and fourth metal pads, and etching an entire surface of the first protection layer until only a residual layer made of a material for forming the first protection layer remains on the active area.

Abstract: Direct growth of black Ge on low-temperature substrates, including plastics and rubber is reported. The material is based on highly dense, crystalline/amorphous core/shell Ge nanoneedle arrays with ultrasharp tips (˜4 nm) enabled by the Ni catalyzed vapor-solid-solid growth process. Ge nanoneedle arrays exhibit remarkable optical properties. Specifically, minimal optical reflectance (<1%) is observed, even for high angles of incidence (˜75°) and for relatively short nanoneedle lengths (˜1 ?m). Furthermore, the material exhibits high optical absorption efficiency with an effective band gap of ˜1 eV. The reported black Ge can have important practical implications for efficient photovoltaic and photodetector applications on nonconventional substrates.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: The invention provides a method for producing a flexible barrier sheet (200) comprising a barrier layer (103) and metallic elements (104), said method comprising: a) providing a metallic layer (102) applied on a polymeric support layer (101), the metallic layer having a first surface (105) facing the polymeric support layer and a second surface (106) facing away from said polymeric support layer; b) providing metallic elements on the second surface of the metallic layer; c) providing a barrier layer covering said second surface of the metallic layer and said metallic elements, the barrier layer having a first surface facing the metallic layer and a second surface facing away from the metallic layer; d) releasing the polymeric support layer from the metallic layer; and e) removing the metallic layer from the metallic elements and the barrier layer.

Abstract: The present invention discloses a method for manufacturing a high mobility material layer, comprising: forming a plurality of precursors in/on a substrate; and performing a pulse laser processing such that the plurality of precursors react with each other to produce a high mobility material layer. Furthermore, the present invention also provides a method for manufacturing a semiconductor device, comprising: forming a buffer layer on an insulating substrate; forming a first high mobility material layer on the buffer layer using the method for manufacturing the high mobility material layer; forming a second high mobility material layer on the first high mobility material layer using the method for manufacturing the high mobility material layer; and forming trench isolations and defining active regions in the first and second high mobility material layers.

Abstract: Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods of their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. In embodiments, the non-planar nanowires and nanowire networks can be used for cantilever oscillation, switching and transistor actions.

Abstract: An object of the present invention is to provide more inexpensive high purity crystalline silicon which can satisfy not only a quality required to a raw material of silicon for a solar cell but also a part of a quality required to silicon for an up-to-date semiconductor and a production process for the same and provide high purity silicon tetrachloride used for production of high purity crystalline silicon and a production process for the same. The high purity crystalline silicon of the present invention has a boron content of 0.015 ppmw or less and a zinc content of 50 to 1000 ppbw. The production process for high purity crystalline silicon according to the present invention is characterized by that a silicon tetrachloride gas and a zinc gas are supplied to a vertical reactor to react them at 800 to 1200° C.

Abstract: A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.

Abstract: A surface of a sapphire (0001) substrate is processed so as to have recesses and protrusions so that protrusion tops are made flat and have a given plan-view pattern. An initial-stage AlN layer is epitaxially grown on the surface of the sapphire (0001) substrate so that new recesses are formed over the recesses, by performing C axis orientation control so that a C+ axis oriented AlN layer grows on flat surfaces of the protrusion tops, excluding edges. A first ELO layer including an AlN (0001) layer is epitaxially grown on the initial-stage AlN layer by an epitaxial lateral overgrowth method, and stops growing before a recess upper region above the new recesses is completely covered with the first ELO layer that is laterally grown from a protrusion upper surface of the initial-stage AlN layer. A second ELO layer including an AlxGa1-xN (0001) layer (1>x>0) is epitaxially grown on the first ELO layer by an epitaxial lateral overgrowth method.

Abstract: A method of fabricating a thin film transistor includes forming an active layer on an insulating substrate; forming a gate insulation film on the insulating substrate; forming source, drain, and body contact regions which are separated by a channel region in the active layer; forming a gate on the gate insulation film; forming an interlayer insulation film on the insulating substrate; and forming source and drain electrodes electrically connected with the source and drain regions, respectively, wherein a voltage is applied to the channel region of the active layer through the body contact region, and the body contact region is connected to the source or drain electrode.

Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.

Abstract: A composition includes a chemical reaction product defining a first surface and a second surface, characterized in that the chemical reaction product includes a segregated phase domain structure including a plurality of domain structures, wherein at least one of the plurality of domain structures includes at least one domain that extends from a first surface of the chemical reaction product to a second surface of the chemical reaction product. The segregated phase domain structure includes a segregated phase domain array. The plurality of domain structures includes i) a copper rich. indium/gallium deficient Cu(In,Ga)Se2 domain and ii) a copper deficient, indium/gallium rich Cu(In,Ga)Se2 domain.

Abstract: In one embodiment, a method of forming a plug includes providing a base layer, providing an intermediate oxide layer above an upper surface of the base layer, providing an upper layer above an upper surface of the intermediate oxide layer, etching a trench including a first trench portion extending through the upper layer, a second trench portion extending through the oxide layer, and a third trench portion extending into the base layer, depositing a first material portion within the third trench portion, depositing a second material portion within the second trench portion, and depositing a third material portion within the first trench portion.

Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.

Abstract: Provided is a method for manufacturing a nitride semiconductor device, including the steps of: forming an AlNO buffer layer containing at least aluminum, nitrogen, and oxygen on a substrate; and forming a nitride semiconductor layer on the AlNO buffer layer, wherein, in the step of forming the AlNO buffer layer, the AlNO buffer layer is formed by a reactive sputtering method using aluminum as a target in an atmosphere to and from which nitrogen gas and oxygen gas are continuously introduced and exhausted, and the atmosphere is an atmosphere in which a ratio of a flow rate of the oxygen gas to a sum of a flow rate of the nitrogen gas and the flow rate of the oxygen gas is not more than 0.5%.

Abstract: Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX. Nanowire cores and pads are etched in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial shells are formed surrounding each of the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores/epitaxial shells, wherein the portions of the nanowire cores/epitaxial shells surrounded by the gate stack serve as channels of the device, and wherein the pads and portions of the nanowire cores/epitaxial shells that extend out from the gate stack serve as source and drain regions of the device.