On Insulating Substrate Or Layer Patents (Class 438/479)
  • Patent number: 8790999
    Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor crystal layer. The method can include forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer. The silicon crystal layer is provided on a base body. The silicon crystal layer has a second thickness before the forming the nitride semiconductor crystal layer. The second thickness is thinner than the first thickness. The forming the nitride semiconductor crystal layer includes making at least a portion of the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Tomonari Shioda, Shinya Nunoue
  • Patent number: 8790979
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a fin in an upper surface of a semiconductor substrate to extend in a first direction, forming a mask film, making a plurality of first trenches in the mask film to extend in a second direction to reach the fin, filling sidewall members into the first trenches, making a second trench by removing the mask film from a portion of a space between the sidewall members, forming a gate insulating film and a gate electrode on a surface of a first portion of the fin disposed inside the second trench, making a third trench by removing the mask film from the remaining space between the sidewall members, and causing a second portion of the fin disposed inside the third trench to become a conductor.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Patent number: 8791023
    Abstract: A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 29, 2014
    Assignee: Eastman Kodak Company
    Inventors: Carolyn R. Ellinger, David H. Levy, Shelby F. Nelson
  • Patent number: 8790998
    Abstract: Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-ha Hong, Kyoung-won Park, Jai-kwang Shin, Jong-seob Kim, Hyuk-soon Choi
  • Patent number: 8790959
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Publication number: 20140203325
    Abstract: A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.
    Type: Application
    Filed: January 22, 2013
    Publication date: July 24, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Purakh Raj VERMA, Guowei ZHANG, Kah Wee ANG
  • Publication number: 20140206126
    Abstract: A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.
    Type: Application
    Filed: March 25, 2014
    Publication date: July 24, 2014
    Applicant: Solar-Tectic LLC
    Inventors: Karin Chaudhari, Pia Chaudhari, Ashok Chaudhari
  • Patent number: 8785294
    Abstract: A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: July 22, 2014
    Assignee: GTAT Corporation
    Inventors: Venkatesan Murali, Steve Babayan, Christopher J. Petti
  • Patent number: 8785302
    Abstract: A crystal silicon film forming method according to the present invention includes: forming a metal film; forming an insulating film on the metal film, and forming a crystal silicon film made of polycrystal Si on the insulating film. In the forming of an insulating film, the insulating film is formed within a film thickness range of 160 nm to 190 nm. The forming of a crystal silicon film includes forming an amorphous silicon film made of a-Si on the insulating film, within a film thickness range of 30 nm to 45 nm, and forming the crystal silicon film from the amorphous silicon film by irradiating the amorphous silicon film with a light of a green laser.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: July 22, 2014
    Assignee: Panasonic Corporation
    Inventor: Yasuo Segawa
  • Publication number: 20140199825
    Abstract: A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects.
    Type: Application
    Filed: September 19, 2012
    Publication date: July 17, 2014
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Jiantao Bian, Zhongying Xue, Zengfeng Di, Miao Zhang
  • Patent number: 8779546
    Abstract: A semiconductor memory system and method of manufacture thereof including: a base wafer; an isolation region on the base wafer; an ion implanted region on the base wafer separated by the isolation region; a bit line contact plug over the ion implanted region; an isolation sidewall on the sides of the bit line contact plug; a resistor or capacitor on the isolation sidewall opposite the bit line contact plug between the bit line contact plug and another of the bit line contact plug; and a bit line over the resistor or capacitor and on the bit line contact plug.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 15, 2014
    Assignee: Sony Corporation
    Inventors: Masanori Tsukamoto, Satoru Mayuzumi
  • Patent number: 8778745
    Abstract: A method for manufacturing a semiconductor device comprises the steps of forming a seed over the insulating film by introducing hydrogen and a deposition gas into a first treatment chamber under a first condition and forming a microcrystalline semiconductor film over the seed by introducing hydrogen and the deposition gas into a second treatment chamber under a second condition: a second flow rate of the deposition gas is periodically changed between a first value and a second value; and a second pressure in the second treatment chamber is higher than or equal to 1.0×102 Torr and lower than or equal to 1.0×103 Torr.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryu Komatsu, Yasuhiro Jinbo, Hidekazu Miyairi
  • Patent number: 8779437
    Abstract: According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8778719
    Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 15, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Toshihiro Nakamura, Nobuaki Orita, Hisashi Koaizawa, Kenkichi Suzuki, Hiroshi Kuraseko, Michio Kondo
  • Patent number: 8778784
    Abstract: Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.
    Type: Grant
    Filed: October 29, 2011
    Date of Patent: July 15, 2014
    Assignee: RiteDia Corporation
    Inventors: Chien-Min Sung, Ming Chi Kan, Shao Chung Hu
  • Patent number: 8779512
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: July 15, 2014
    Assignees: NEC Corporation, NLT Technologies, Ltd.
    Inventor: Shigeru Mori
  • Publication number: 20140191319
    Abstract: A diode for integration with finFET devices is disclosed. An in-situ doped epitaxial silicon region is grown on the cathode or anode of the diode to increase the surface area of the junction and overall silicon volume for improved heat dissipation during an ESD event.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicants: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shom Ponoth, Balasubramanian Pranatharthiharan, Theodorus Eduardus Standaert, Tenko Yamashita, Robert J. Miller
  • Publication number: 20140193966
    Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.
    Type: Application
    Filed: March 7, 2014
    Publication date: July 10, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byung-Kwan YOU, Kwang-Soo SEOL, Young-Woo PARK, Jin-Soo LIM
  • Publication number: 20140183541
    Abstract: A thin film transistor and a manufacturing method for the same, an array substrate, and a display device are disclosed. The thin film transistor comprises: a substrate (1) and a gate (2), a first gate insulating layer (3) and an active layer (4) which are disposed in order on the substrate, the first gate insulating layer (3) covers the gate (2), the active layer (4) covers the first gate insulating layer (3), and a material for the first gate insulating layer comprises aluminum oxide.
    Type: Application
    Filed: November 13, 2012
    Publication date: July 3, 2014
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Dongfang Wang
  • Publication number: 20140183700
    Abstract: A method of producing a template material for growing semiconductor materials and/or devices, comprises the steps of: (a) providing a substrate with a dielectric layer on the substrate; and (b) forming a pixelated pattern on the dielectric layer, the pattern comprising a plurality of discrete groups of structures.
    Type: Application
    Filed: November 7, 2011
    Publication date: July 3, 2014
    Inventor: Wang Nang Wang
  • Publication number: 20140187024
    Abstract: Provided is a method of forming a seed layer as a seed of a thin film on an underlayer, which includes: forming a first seed layer on a surface of the underlayer by heating the underlayer, followed by supplying an aminosilane-based gas onto the surface of the heated underlayer; and forming a second seed layer on the surface of the underlayer with the first seed layer formed thereon by heating the underlayer, followed by supplying a disilane or higher order silane-based gas onto the surface of the heated underlayer.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tomoyuki OBU, Takahiro MIYAHARA, Tomoyuki NAGATA
  • Patent number: 8766337
    Abstract: A first thin film diode (100A) has a first semiconductor layer (10A) and a first light blocking layer (12A) disposed on the substrate side of the first semiconductor layer. A second thin film diode (100B) has a second semiconductor layer (10B) and a second light blocking layer (12B) disposed on the substrate side of the second semiconductor layer. An insulating film (14) is formed between the first semiconductor layer (10A) and the first light blocking layer (12A) and between the second semiconductor layer (10B) and the second light blocking layer (12B). A thickness D1 of a portion of the insulating film (14) positioned between the first semiconductor layer (10A) and the first light blocking layer (12A) is different from a thickness D2 of a portion of the insulating film (14) positioned between the second semiconductor layer (10B) and the second light blocking layer (12B).
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: July 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroshi Aichi
  • Publication number: 20140175549
    Abstract: A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.
    Type: Application
    Filed: February 26, 2014
    Publication date: June 26, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 8759194
    Abstract: Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Gauthier, Jr., Jeffrey B. Johnson, Junjun Li
  • Publication number: 20140167162
    Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Junli Wang, Chun-chen Yeh, Yunpeg Yin
  • Publication number: 20140170839
    Abstract: One illustrative method disclosed herein includes forming a silicon/germanium fin in a layer of insulating material, wherein the fin has a first germanium concentration, recessing an upper surface of the layer of insulating material so as to expose a portion of the fin, performing an oxidation process so as to oxidize at least a portion of the fin and form a region in the exposed portion of the fin that has a second germanium concentration that is greater than the first germanium concentration, removing the oxide materials from the fin that was formed during the oxidation process and forming a gate structure that is positioned around at least the region having the second germanium concentration.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: David P. Brunco
  • Publication number: 20140167230
    Abstract: [Problem] To provide a composite substrate which includes a silicon substrate having few lattice defects. [Solution] A composite substrate (50) that comprises a first substrate (10), which is constituted of a semiconductor material, a second substrate (40), which is constituted of an insulating material, and an oxide layer (30) and a semiconducting epitaxial layer (20) which have been disposed between the substrates (10) and (40) in this order from the second substrate (40) side, the oxide layer (30) having oxygen atoms arranged on the side thereof which faces the epitaxial layer (20).
    Type: Application
    Filed: June 26, 2012
    Publication date: June 19, 2014
    Applicant: KYOCERA CORPORATION
    Inventors: Masanobu Kitada, Tomofumi Honjo
  • Patent number: 8753968
    Abstract: A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: June 17, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kuang-Hung Huang, Po-Jui Liao, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang
  • Patent number: 8754478
    Abstract: An organic thin-film transistor includes: a semiconductor layer made of an organic material; a gate electrode; a source electrode and a drain electrode each at least partially provided above the semiconductor layer; and a conductive layer containing an oxide having conductivity that changes due to reduction, the conductive layer being provided in each of a first region and a second region facing the source electrode and the drain electrode provided above the semiconductor layer, respectively.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 17, 2014
    Assignee: Sony Corporation
    Inventor: Shinichi Ushikura
  • Publication number: 20140158987
    Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Applicant: HRL LABORATORIES, LLC
    Inventor: HRL Laboratories, LLC
  • Publication number: 20140158976
    Abstract: III-N semiconductor-on-silicon integrated circuit structures and techniques are disclosed. In some cases, the structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer including a 3-D GaN layer on the nucleation layer and having a plurality of 3-D semiconductor structures, and a 2-D GaN layer on the 3-D GaN layer. The structure also may include a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer. Another structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer comprising a 2-D GaN layer on the nucleation layer, and a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Robert S. Chau
  • Patent number: 8748298
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
  • Patent number: 8748294
    Abstract: There is provided an SOS substrate with reduced stress. The SOS substrate is a silicon-on-sapphire (SOS) substrate comprising a sapphire substrate and a monocrystalline silicon film on or above the sapphire substrate. The stress of the silicon film of the SOS substrate as measured by a Raman shift method is 2.5×108 Pa or less across an entire in-plane area of the SOS substrate.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: June 10, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoji Akiyama
  • Patent number: 8748240
    Abstract: Oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film are reduced and electric characteristics of a transistor including the oxide semiconductor film are improved. Further, a highly reliable semiconductor device including the transistor including the oxide semiconductor film is provided. In the transistor including the oxide semiconductor film, at least one insulating film in contact with the oxide semiconductor film contains excess oxygen. By the excess oxygen included in the insulating film in contact with the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced. Note that the insulating film including the excess oxygen has a profile of the excess oxygen concentration having two or more local maximum values in the depth direction.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8748889
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
  • Publication number: 20140151636
    Abstract: Briefly described, embodiments of the present disclosure relate to structures including single-walled carbon nanotube/quantum dot networks, devices including the structures, and methods of making devices including the single-walled carbon nanotube/quantum dot networks.
    Type: Application
    Filed: December 5, 2013
    Publication date: June 5, 2014
    Inventors: Marcus D. Lay, Pornnipa Vichchulada, Darya Asheghali
  • Publication number: 20140151802
    Abstract: A method comprises: forming a tensile SSOI layer on a buried oxide layer on a bulk substrate; forming a plurality of fins in the SSOI layer; removing a portion of the fins; annealing remaining portions of the fins to relax a tensile strain of the fins; and merging the remaining portions of the fins.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Ali Khakifirooz, Pranita Kerber, Alexander Reznicek
  • Patent number: 8741748
    Abstract: Group III-nitride epilayers can be grown directly on copper substrates using intermediate passivation layers. For example, single crystalline c-plane GaN can be grown on Cu (110) substrates with MOCVD. The growth relies on a low temperature AlN passivation layer to isolate any alloying reaction between Ga and Cu.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 3, 2014
    Assignee: Sandia Corporation
    Inventors: Qiming Li, George T. Wang, Jeffrey T. Figiel
  • Patent number: 8741747
    Abstract: A method for processing a glass substrate is disclosed. A glass substrate including a first surface, a second surface, and a side surface between the first surface and the second surface is provided. An opaque conductive layer is formed on the second surface and a part of the side surface close to the second surface. Thereafter, a semiconductor process is performed on the first surface. Thereafter, the opaque conductive layer on the second surface and the part of the side surface close to the second surface is removed. The problem of transporting a transparent glass substrate by some semiconductor tools is solved without increasing tool cost by enabling the sensing and transportation of glass substrates with optical sensor and/or electrical chuck. The fabrication of devices with a glass substrate is also achieved.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xuanjie Liu, Herb Huang, Guoan Liu
  • Publication number: 20140145295
    Abstract: Methods and structures having increased fin density are disclosed. Structures with two sets of fins are provided. A lower set of fins is interleaved with an upper set of fins in a staggered manner, such that the lower set of fins and upper set of fins are horizontally and vertically non-overlapping.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 29, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Publication number: 20140147995
    Abstract: A method of manufacturing a p type nitride semiconductor layer doped with carbon in a highly reproducible manner with an increased productivity is provided. The method includes supplying an III-group material gas for a predetermined time period T1, supplying a V-group material gas containing a carbon source for a predetermined time period T2 when a predetermined time period t1 (t1+T2>T1) elapses after the supply of the III-group material gas begins, repeating the step of supplying the III-group material gas and the step of supplying the V-group material gas when a predetermined time period t2 (t1+T2?t2>T1) elapses after the supply of the V-group material gas begins, and thus forming an AlxGa1-xN semiconductor layer (0<x?1) at a growth temperature of 1190° C.˜1370° C. or a growth temperature at which a substrate temperature is 1070° C.˜1250° C. using a chemical vapor deposition method or a vacuum evaporation method. Nitrogen sites within the semiconductor layer are doped with carbon.
    Type: Application
    Filed: April 18, 2013
    Publication date: May 29, 2014
    Applicant: Seoul Semiconductor Co., Ltd.
    Inventor: Hideo KAWANISHI
  • Publication number: 20140145147
    Abstract: A nitride semiconductor structure of the present invention is obtained by growing an h- or t-BN thin film (12) and a wurtzite-structure AlxGa1-xN (x>0) thin film (14) as buffer layers and forming a single-crystal wurtzite-structure AlGaInBN thin film (13) thereon. While GaN, AlGaN, AlN, and the like have the wurtzite structure with sp3 bonds, h-BN or t-BN has the graphite structure with sp2 bonds, and has a completely different crystal structure. Accordingly, it has heretofore not been considered that a wurtzite-structure AlGaInBN thin film can be grown on a graphite-structure h-BN thin film. However, when a wurtzite-structure AlxGa1-xN (x>0) thin film (14) is formed as a buffer layer on a graphite-structure boron nitride thin film (12), a wurtzite-structure AlGaInBN (13) nitride semiconductor structure such as GaN can be grown on the buffer layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: May 29, 2014
    Inventors: Yasuyuki Kobayashi, Kazuhide Kumakura, Tetsuya Akasaka, Toshiki Makimoto
  • Publication number: 20140145310
    Abstract: A method of manufacturing a thin film device, the method includes: forming a functional film having a predetermined pattern on a surface of a first substrate; covering the surface of the first substrate and the functional film with an insulating film; and transferring the insulating film and the functional film from the first substrate to a second substrate.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 29, 2014
    Applicant: Sony Corporation
    Inventor: Ryuto Akiyama
  • Publication number: 20140145238
    Abstract: Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Marcello Mariani, Carlo Pozzi
  • Publication number: 20140138696
    Abstract: A method of manufacturing a polycrystalline silicon film includes: depositing a catalyst layer including nickel and depositing nickel nanoparticles on a substrate; exposing the catalyst layer and the nanoparticles to at least silane gas; and heat treating the substrate coated with the catalyst layer and the nanoparticles during at least part of the exposing to silane gas in growing a silicon based film on the substrate.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: GUARDIAN INDUSTRIES CORP.
    Inventors: Vijayen S. VEERASAMY, Martin D. BRACAMONTE
  • Publication number: 20140141600
    Abstract: A method of preparing graphene includes forming a silicon carbide thin film on a substrate, forming a metal thin film on the silicon carbide thin film, and forming a metal composite layer and graphene on the substrate by heating the silicon carbide thin film and the metal thin film.
    Type: Application
    Filed: June 14, 2013
    Publication date: May 22, 2014
    Inventors: Dong Wook LEE, Hyeon-jin SHIN, Seong-jun PARK, Kyung-eun BYUN, David SEO, Hyun-jae SONG, Yun-sung WOO, Jae-ho LEE, Hyun-jong CHUNG, Jin-seong HEO
  • Publication number: 20140141601
    Abstract: A method is provided for producing field effect transistors (FETs) for display applications. The method involves low temperature deposition of semiconductor films on inexpensive substrates such as ordinary soda-lime glass or borosilicate glass.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 22, 2014
    Applicant: Solar-Tectic LLC
    Inventors: Karin Chaudhari, Pia Chaudhari, Ashok Chaudhari
  • Publication number: 20140138772
    Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.
    Type: Application
    Filed: May 13, 2013
    Publication date: May 22, 2014
    Applicant: Samsung Display Co., Ltd
    Inventors: Hyun Jae NA, Yoon Ho KHANG, Sang Ho PARK, Dong Hwan SHIM, Se Hwan YU, Yong Su LEE, Myoung Geun CHA
  • Patent number: 8728917
    Abstract: A carbon nanotube forming method including providing a target substrate to be processed, a catalytic metal layer being formed on a surface of the target substrate; producing catalytic fine metal particles whose surfaces are oxidized by action of an oxygen plasma on the catalytic metal layer at a temperature T1; and activating the oxidized surfaces of the catalytic fine metal particles by reducing the oxidized surfaces of the catalytic fine metal particles by action of a hydrogen plasma on the catalytic fine metal particles at a temperature T2 higher than the temperature T1. The method further includes growing a carbon nanotube on the activated catalytic fine metal particles by thermal CVD at a temperature T3.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: May 20, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Matsumoto, Osayuki Akiyama, Kenjiro Koizumi
  • Publication number: 20140131771
    Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Matthias Kessler, Jan Hoentschel