Abstract: Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer.

Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.

Abstract: A method of removing trace levels of arsenic-containing impurities from raw triethylphosphate (TEPO) is disclosed. The method uses adsorption, or adsorption followed by a flash distillation. The method comprises contacting raw triethylphosphate (TEPO) with an adsorbent which selectively adsorbs the arsenic-containing impurities in the raw triethylphosphate (TEPO). The adsorbent is a base promoted alumina containing adsorbent represented by a formula: ZxWy; where x is the weight percentage of Z in the adsorbent ranging from 30% to 99.999%; y is the weight percentage of W in the adsorbent, and x+y=100%; Z is selected from the group consisting of alumina (Al2O3), magnesium-alumina based layered double hydroxide (MgO—Al2O3), alumina-zeolite, and mixtures thereof; and W is selected from the group consisting of at least one basic metal oxide, at least one basic metal carbonate, and mixtures thereof.

Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.

Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does not cover a second region and a third region thereon; oxidizing the silicon substrate to thicken the first silicon oxide film formed on the first region, and to form a second silicon oxide film on the second region and the third region; forming a first silicon film which covers the first region and the second region, but which does not cover the third region; etching and removing the second silicon oxide film formed on the third region by using the first silicon film as a mask; and forming a third silicon oxide film on the third region, the third silicon oxide film being thinner than the second silicon oxide film.

Abstract: A substrate is exposed to a plasma generated from a gas containing an impurity, thereby doping a surface portion of the substrate with the impurity and thus forming an impurity region. A predetermined plasma doping time is used, which is included within a time range over which a deposition rate on the substrate by the plasma is greater than 0 nm/min and less than or equal to 5 nm/min.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

Abstract: The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer.

Abstract: To provide a low-cost high performance semiconductor device and a method for manufacturing the semiconductor device, a separate single-crystal semiconductor layer having a first region and a non-single-crystal semiconductor layer having a second region are provided over a substrate. Further, it is preferable that a cap film is formed over either the separate single-crystal semiconductor layer or the non-single-crystal semiconductor layer, and the first region and the second region are irradiated with a laser beam by applying the laser beam from above the cap film.

Abstract: This invention provides methods for fabricating high speed TFTs from silicon-on-insulator and bulk single crystal semiconductor substrates, such as Si(100) and Si(110) substrates. The TFTs may be designed to have a maximum frequency of oscillation of 3 GHz, or better.

Abstract: An object of an embodiment of the present invention to be disclosed is to prevent oxygen from being taken in a single crystal semiconductor layer in laser irradiation even when crystallinity of the single crystal semiconductor layer is repaired by irradiation with a laser beam; and to make substantially equal or reduce an oxygen concentration in the semiconductor layer after the laser irradiation comparing before the laser irradiation. A single crystal semiconductor layer which is provided over a base substrate by bonding is irradiated with a laser beam, whereby the crystallinity of the single crystal semiconductor layer is repaired. The laser irradiation is performed under a reducing atmosphere or an inert atmosphere.

Abstract: The invention concerns a method for forming a growth mask on the surface of an initial crystalline substrate, comprising the following steps: formation of a layer of second material on one of the faces of the initial substrate of first material, formation of a pattern in the thickness of the layer of second material so as to expose the zones of said face of the initial substrate, said zones forming growth windows on the initial substrate, the method being characterized in that the formation of the pattern is obtained by ion implantation carried out in the surface layer of the initial substrate underlying the layer of second material, the implantation conditions being such that they cause, directly or after a heat treatment, on said face of the initial substrate, the appearance of exfoliated zones of first material leading to the localized removal of the zones of second material covering the exfoliated zones of first material, thereby locally exposing the initial substrate and forming growth windows on

Abstract: The present invention involves a system and method of remotely detecting the presence of a wafer comprising, a passive RFID circuit, wherein the RFID circuit is attached to an end of a transfer arm located inside a vacuum chamber of an ion implantation system, a reader located outside the vacuum chamber, and wherein the RFID tag provides an indication relating to whether or not a wafer is secured by the transfer arm.

Abstract: There is disclosed a method for forming a gallium nitride layer of which resistivity is 1×106 ?·cm or more, including steps of: forming a gallium nitride layer containing iron on a substrate; and heating said gallium nitride layer formed on said substrate.

Abstract: A SIMOX wafer is produced by implanting an oxygen ion, in which a hydrogen ion is implanted at a dose of 1015-1017/cm2 before or after the step of the oxygen ion implantation.

Abstract: A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract: Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.

Abstract: A method of producing a semiconductor structure having a buried insulating layer having a thickness between 2 and 25 nm, by: forming at least one insulating layer on a surface of a first or second substrate, or both, wherein the surfaces are free from an insulator or presenting a native oxide layer resulting from exposure of the substrates to ambient conditions; assembling the first and second substrates; and thinning down the first substrate, in order to obtain the semiconductor structure. In this method, the insulating layer forming stage is a plasma activation based on an oxidizing or nitriding gas.

Abstract: A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.

Abstract: A wafer includes a wafer frontside and a region adjacent to the device surface, wherein the region includes vacancy-oxygen complexes and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property.

Abstract: This method for manufacturing a SIMOX wafer includes: forming a mask layer on one surface side of a silicon single crystal wafer, which has an opening on a region where a BOX layer is to be formed; implanting oxygen ions through the opening of the mask layer into the silicon single crystal wafer to a predetermined depth, and locally forming an oxygen implantation region; annealing the silicon single crystal wafer with the mask layer, and oxidizing the oxygen implantation region so as to form the BOX layer; and removing a coated oxide film that covers the whole silicon single crystal wafer which is formed in the annealing of the silicon single crystal wafer, wherein the mask layer has a lamination comprising an oxide film and either one or both of a polysilicon film and an amorphous silicon film.

Abstract: The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.

Abstract: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having no oxide film wherein hydrogen ions are implanted into a wafer for active layer having no oxide film on its surface to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer.

Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.

Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.

Abstract: A method of forming an impurity-introduced layer is disclosed. The method includes at least a step of forming a resist pattern on a principal face of a solid substrate such as a silicon substrate (S27); a step of introducing impurity into the solid substrate through plasma-doping in ion mode (S23), a step of removing a resist (S28), a step of cleaning metal contamination and particles attached to a surface of the solid substrate (S25a); a step of anneal (S26). The step of removing a resist (S28) irradiates the resist with oxygen-plasma or brings mixed solution of sulfuric acid and hydrogen peroxide water, or mixed solution of NH4OH, H2O2 and H2O into contact with the resist. The step of cleaning (S25a) brings mixed solution of sulfuric acid and hydrogen peroxide water, or mixed solution of NH4OH, H2O2 and H2O into contact with the principal face of the solid substrate.

Abstract: A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.

Abstract: A semiconductor layer is prepared in which a silicon substrate, a BOX layer and an SOI layer are laminated in this order. A silicon diode section used as an infrared detection portion is formed in the SOI layer. Further, an isolation portion is formed so as to extend from the SOI layer to a predetermined depth of the silicon substrate via the BOX layer. The isolation portion is formed so as to surround an area in which the silicon diode section is formed, and have the form of a circle or a regular polygon more than a regular pentagon in shape. A protective film is formed on the surface of the SOI layer. Thereafter, etching holes that penetrate the protective film, the SOI layer and the BOX layer are formed. The silicon substrate corresponding to each area surrounded by the isolation portion is etched using the etching holes.

Abstract: A system and method for producing a single-crystal germanium layer on a dielectric layer by producing a germanium-on-insulator assembly between the surface portions of the third material. The choice of location for these surface portions therefore makes it possible to define the zone on which it is desired to produce the germanium-on-insulator layer. The wafer may be freely chosen between a pure single-crystal silicon wafer and a silicon-on-insulator wafer. A single-crystal germanium first layer is produced on the surface portion of the silicon. The RPCVD produces a partially crystalline germanium first layer. The layer thus comprises various nuclei that have crystallized in possibly different lattices. After carrying out a recrystallization annealing operation, which makes the layer monocrystalline by recrystallizing the various nuclei in one and the same crystal lattice. Thus, the layers are continuous with the single-crystal silicon lattice.

Abstract: A method for electroplating low-resistance metal wire for resolving the problem to fabricate the metal wire on large-area substrate through the technology of photolithographing and etching in the prior art. Then the invention improves the RC-delay characteristic of circuit on large-area substrate and reduces the number of masks for processing of a structure of gate overlap lightly-doped drain (source) (GOLDD).

Abstract: This patent relates to a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an insulating layer formed in a semiconductor substrate, trenches formed within the insulating layer, silicon layers formed within the trenches, gates formed on the silicon layers, and junctions formed in the silicon layers at both sides of the gates.

Abstract: The present invention is directed to a method for fabricating a thermal management substrate having a Silicon (Si) layer on a polycrystalline diamond film, or on a diamond-like-carbon (DLC) film. The method comprises acts of fabricating a separation by implantation of oxygen (SIMOX) wafer; depositing a polycrystalline diamond film onto the SIMOX wafer; and removing various layers of the SIMOX wafer to leave a Si overlay layer that is epitaxially fused with the polycrystalline diamond film. In the case of the DLC film, the method comprises acts of ion-implanting a Si wafer; depositing an amorphous DLC film onto the Si wafer; and removing various layers of the Si wafer to leave a Si overlay structure epitaxially fused with the DLC film.

Abstract: An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.

Abstract: In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to increased seasoning layer thickness. This is accomplished by first plasma-discharging residual electrostatic charge from the thick seasoning layer. The number of wafers which can be processed using the same seasoning layer is further increased by fractionally supplementing the seasoning layer after each wafer is processed, which may be followed by a brief plasma discharging of the supplemented seasoning before processing the next wafer.

Abstract: A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer.

Abstract: A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Preferably, the first face region of the thickness of material is joined to the second face region of the second substrate. The substrate has an interface region formed between the first face region of the thickness of material and the second face region of the second substrate. A plurality of particles are implanted within a portion of the thickness of the material and a portion of the interface region to electrically couple a portion of the thickness of material to a portion of the second substrate.

Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.

Abstract: Methods of fabricating SOI wafers are provided including providing a donor wafer and forming a hydrogen ion implantation layer in the donor wafer. A circumference portion of one side of the donor wafer is recessed to form a height difference. The one side of the donor wafer and a handle wafer are bonded to form a bonded wafer. The bonded wafer is heat treated to separate the bonded wafer along the hydrogen ion implantation layer.

Abstract: An SOI design layout is converted to a bulk design layout. According to a method of converting a first semiconductor design layout based on an Silicon-on-Insulator (SOI) process to a second semiconductor design layout based on a bulk process, an insulator layer of the SOI process beneath active devices in the first semiconductor design layout is removed. A conductive sub-surface structure for routing voltage is added to the first semiconductor design layout. Further, the active devices from the SOI process are converted to the bulk process to form the second semiconductor design layout without requiring a relayout of the first semiconductor design layout on a semiconductor surface. The bulk design layout is utilized to fabricate a semiconductor device having a plurality of active devices.

Abstract: Systems and methods for and products of a semiconductor-on-insulator (SOI) structure including subjecting at least one unfinished surface to a laser annealing process. Production of the SOI structure further may include subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to an insulator substrate; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing at least one cleaved surface; and subjecting the at least one cleaved surface to the laser annealing process.

Abstract: A surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region, an insulating layer is formed over the surface of the single crystal semiconductor substrate, and a surface of a substrate having an insulating surface is made to be in contact with a surface of the insulating layer to bond the substrate having an insulating surface to the single crystal semiconductor substrate. Then, the single crystal semiconductor substrate is separated at the damaged region by performing heat treatment to form a single crystal semiconductor layer over the substrate having an insulating surface, and the single crystal semiconductor layer is patterned to form a plurality of island-shaped semiconductor layers. One of the island-shaped semiconductor layers is irradiated with a laser beam which is shaped to entirely cover the island-shaped semiconductor layer.

Abstract: The invention concerns a method for forming a growth mask on the surface of an initial crystalline substrate, comprising the following steps: formation of a layer of second material on one of the faces of the initial substrate of first material, formation of a pattern in the thickness of the layer of second material so as to expose the zones of said face of the initial substrate, said zones forming growth windows on the initial substrate, the method being characterised in that the formation of the pattern is obtained by ion implantation carried out in the surface layer of the initial substrate underlying the layer of second material, the implantation conditions being such that they cause, directly or after a heat treatment, on said face of the initial substrate, the appearance of exfoliated zones of first material leading to the localised removal of the zones of second material covering the exfoliated zones of first material, thereby locally exposing the initial substrate and forming growth windows on the

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract: A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of the

Abstract: A method of forming a localized region of relaxed Si in a layer of strained Si arranged within a strained silicon directly on insulator (SSDOI) semiconductor substrate is provided by the invention. The strained Si layer is formed on a buried oxide (BOX) layer disposed on a Si substrate base. The method includes depositing a nitride hard mask pattern above a region of the strained Si layer in which enhanced electron mobility is desired, leaving an unmasked region within the strained Si layer, and carrying out various other processing steps to modify and relax the unmasked portion of the strained region. The method includes growing an EPI SiGe region upon the unmasked region using pre-amorphization implantation, and forming a buried amorphous SiGe region in a portion of the EPI SiGe region, and an amorphous Si region, below the amorphous SiGe region. Then, using SPE regrowth, modifying the amorphous SiGe and amorphous Si regions to realize an SPE SiGe region and relaxed SPE Si layer.

Abstract: The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer.

Abstract: The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.