Including Implantation Of Ion Which Reacts With Semiconductor Substrate To Form Insulating Layer Patents (Class 438/480)
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Patent number: 7485551Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.Type: GrantFiled: January 5, 2006Date of Patent: February 3, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Xavier Hebras
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Patent number: 7475102Abstract: Random number generating method for generating random numbers in accordance with multivariate non-normal distributions based on the Yuan and Bentler method I on computer. The method includes application steps for applying n-dimensional multivariate non-normal distributions to n-dimensional experience distribution by using computer and steps for generating random numbers including pseudo-random numbers, quasi-random numbers, low discrepancy sequences, and physical random numbers by methods including additive generator method, M-sequence, generalized feedback shift-register method, and Mersenne Twister, and excluding congruential method, by using computer. The application steps use predetermined relationship equations for the third and fourth order moments to perform application associated with the third and fourth order moments of the empirical distributions. Moreover, by using random numbers generation method, parameters are estimated by maximum likelihood method.Type: GrantFiled: March 14, 2003Date of Patent: January 6, 2009Inventor: Yuichi Nagahara
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Patent number: 7465612Abstract: A thin film transistor substrate and its fabrication method are discussed. According to an embodiment, the fabricating method of a thin film transistor substrate includes forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode, the gate insulating film having a groove in an area corresponding to an area where an active layer of a thin film transistor is to be formed; forming the active layer of the thin film transistor by use of a nanowire in the groove of the gate insulating film; and forming a source electrode and a drain electrode on the active layer.Type: GrantFiled: December 21, 2005Date of Patent: December 16, 2008Assignee: LG Display Co., Ltd.Inventors: Gee Sung Chae, Mi Kyung Park
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Patent number: 7466907Abstract: A device for use in a thermal annealing process for a wafer (T) of material chosen among the semiconductor materials for the purpose of detaching a layer from the wafer at an weakened zone. During annealing, the device applies (1) a basic thermal budget to the wafer, with the basic thermal budget being slightly inferior to the budget necessary to detach the layer, this budget being distributed in an even manner over the weakened zone; and (2) an additional thermal budget is also applied to the wafer locally in a set region of the weakened zone so as to initiate the detachment of the layer in this region.Type: GrantFiled: May 16, 2006Date of Patent: December 16, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Walter Schwarzenbach, Jean-Marc Waechter
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Publication number: 20080280424Abstract: After the plurality of single-crystal semiconductor layers are provided adjacent to each other with a certain distance over a glass substrate which is a support substrate, heat treatment is performed on the glass substrate. The support substrate shrinks by this heat treatment, and the adjacent single-crystal semiconductor layers are in contact with each other due to the shrink. Energy beam irradiation is performed with the plurality of single-crystal semiconductor layers being in contact with each other, the plurality of single-crystal semiconductor layers are integrated, and thus a continuous single-crystal semiconductor layer is formed.Type: ApplicationFiled: March 31, 2008Publication date: November 13, 2008Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuyuki Arai
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Publication number: 20080265331Abstract: In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm?3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.Type: ApplicationFiled: April 16, 2008Publication date: October 30, 2008Inventors: Junichi Sakano, Kenji Hara, Shinji Shirakawa, Taiga Arai, Mutsuhiro Mori
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Publication number: 20080265328Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does not cover a second region and a third region thereon; oxidizing the silicon substrate to thicken the first silicon oxide film formed on the first region, and to form a second silicon oxide film on the second region and the third region; forming a first silicon film which covers the first region and the second region, but which does not cover the third region; etching and removing the second silicon oxide film formed on the third region by using the first silicon film as a mask; and forming a third silicon oxide film on the third region, the third silicon oxide film being thinner than the second silicon oxide film.Type: ApplicationFiled: April 22, 2008Publication date: October 30, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshito Suwa, Masataka Takebuchi
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Patent number: 7442586Abstract: An improved semiconductor-on-insulator (SOI) substrate is provided, which has a substantially planar upper surface and comprises at least first and second patterned buried insulator layers. Specifically, the first patterned buried insulator layer has a first thickness and is located in the SOI substrate at a first depth from the substantially planar upper surface, and the second patterned buried insulator layer has a second, different thickness and is located in the SOI substrate at a second, different depth from the substantially planar upper surface. The first and second patterned buried insulator layers are separated from each other by one or more interlayer gaps, which provide body contacts for the SOI substrate. The SOI substrate of the present invention can be readily formed by a method that includes at least two independent ion implantation steps.Type: GrantFiled: March 31, 2006Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: Thomas W. Dyer, Zhijiong Luo
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Patent number: 7439092Abstract: A method of fabricating thin films of semiconductor materials by implanting ions in a substrate composed of at least two different elements at least one of which can form a gaseous phase on bonding with itself and/or with impurities includes the following steps: (1) bombarding one face of the substrate with ions of a non-gaseous heavy species in order to implant those ions in a concentration sufficient to create in the substrate a layer of microcavities containing a gaseous phase formed by the element of the substrate; (2) bringing this face of the substrate into intimate contact with a stiffener; and (3) obtaining cleavage at the level of the microcavity layer by the application of heat treatment and/or a splitting stress.Type: GrantFiled: May 19, 2006Date of Patent: October 21, 2008Assignee: Commissariat A l'Energie AtomiqueInventor: Aurélie Tauzin
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Patent number: 7432122Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.Type: GrantFiled: January 6, 2006Date of Patent: October 7, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, Michael G. Khazhinsky
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Publication number: 20080213982Abstract: Provided is a method of fabricating a semiconductor wafer. The method includes preparing a substrate wafer having a non-single-crystalline thin layer; disposing at least one single crystalline pattern adjacent to the non-single-crystalline thin layer on the substrate wafer; and forming a material layer contacting the single crystalline pattern on the non-single-crystalline thin layer.Type: ApplicationFiled: February 28, 2008Publication date: September 4, 2008Inventors: Young-Soo Park, Young-Sam Lim, Young-Nam Kim, Dae-Lok Bae, Joon-Young Choi, Gi-Jung Kim
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Publication number: 20080135949Abstract: A method of forming a stacked silicon-germanium nanowire structure on a support substrate is disclosed. The method includes forming a stacked structure on the support substrate, the stacked structure comprising at least one channel layer and at least one interchannel layer deposited on the channel layer; forming a fin structure from the stacked structure, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing the fin portion of the fin structure thereby forming the silicon-germanium nanowire being surrounded by a layer of oxide; and removing the layer of oxide to form the silicon-germanium nanowire. A method of forming a gate-all-around transistor comprising forming a stacked silicon-germanium nanowire structure that has been formed on a support substrate is also disclosed. A stacked silicon-germanium nanowire structure and a gate-all-around transistor comprising the stacked silicon-germanium nanowire structure are also disclosed.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Applicant: Agency for Science, Technology and ResearchInventors: Guo Qiang Lo, Lakshmi Kanta Bera, Hoai Son Nguyen, Navab Singh
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Publication number: 20080128807Abstract: In fabricating a semiconductor device, an element forming surface formation step of forming a plurality of element forming surfaces of different heights on a semiconductor layer to have different levels, a semiconductor element formation step of forming a plurality of semiconductor elements and, one in each of a corresponding number of regions of the semiconductor layer, each region including an associated one of the plurality of element forming surfaces, a level-difference compensation insulating film formation step of forming a level-difference compensation insulating film on the semiconductor layer to cover the semiconductor elements and have a surface with different levels along the element forming surfaces, a release layer formation step of forming a release layer in the semiconductor layer by ion-implanting a peeling material through the level-difference compensation insulating film into the semiconductor layer, and a separation step of separating part of the semiconductor layer along the release layerType: ApplicationFiled: November 15, 2005Publication date: June 5, 2008Inventors: Yasumori Fukushima, Yutaka Takafuji, Masao Moriguchi
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Patent number: 7375035Abstract: A host and ancillary tool interface methodology for distributed processing is described. The host tool manages a process, except for the generation of a product used in the process. To generate the product, the host tool provides an indication to an ancillary tool that the product is to be generated, and the ancillary tool generates the product after detection of the indication with no further intervention by the host tool. To provide the indication, the host tool preferably activates a control line whose voltage is monitored by the ancillary tool, or alternatively, sets one or more bits in a memory which is periodically checked by the ancillary tool.Type: GrantFiled: April 29, 2003Date of Patent: May 20, 2008Assignee: Ronal Systems CorporationInventors: Craig R. Heden, Albert R. DePetrillo, Robert M. McGuire
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Patent number: 7354786Abstract: A micromechanical sensor element and a method for the production of a micromechanical sensor element that is suitable, for example in a micromechanical component, for detecting a physical quantity. Provision is made for the sensor element to include a substrate, an access hole and a buried cavity, at least one of the access holes and the cavity being produced in the substrate by a trench etching and/or, in particular, an isotropic etching process. The trench etching process includes different trenching (trench etching) steps which may be divided into a first phase and a second phase. Thus, in the first phase, at least one first trenching step is carried out in which, in a predeterminable first time period, material is etched out of the substrate and a depression is produced. In that trenching step, a typical concavity is produced in the wall of the depression.Type: GrantFiled: September 8, 2005Date of Patent: April 8, 2008Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Stefan Finkbeiner, Matthias Illing, Frank Schaefer, Simon Armbruster, Gerhard Lammel, Christoph Schelling, Joerg Brasas
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Patent number: 7352034Abstract: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.Type: GrantFiled: August 25, 2005Date of Patent: April 1, 2008Assignee: International Business Machines CorporationInventors: Roger Allen Booth, Jr., Jack Allan Mandelman, William Robert Tonti
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Patent number: 7348253Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.Type: GrantFiled: May 27, 2004Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Keith E. Fogel, Richard J. Murphy, Devendra K. Sadana
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Publication number: 20070278599Abstract: A semiconductor device and method of forming the same are provided. The example semiconductor device may include a gate pattern including a gate electrode and a capping layer pattern on a semiconductor substrate, a spacer covering first and second sidewalls of the gate pattern, an impurity injection region formed in the semiconductor substrate adjacent to the gate pattern and an etch stopping layer covering a surface of the semiconductor substrate adjacent to the spacer, the etch stopping layer substantially not covering the first and second sidewalls of the spacer and an upper surface of the capping layer pattern.Type: ApplicationFiled: April 17, 2007Publication date: December 6, 2007Inventor: Ki-Jae Hur
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Patent number: 7285480Abstract: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.Type: GrantFiled: April 7, 2006Date of Patent: October 23, 2007Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Louis C. Hsu, Oleg Gluschenkov
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Patent number: 7268065Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.Type: GrantFiled: June 18, 2004Date of Patent: September 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Patent number: 7183172Abstract: A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer. The diffusion barrier layer serves to prevent impurities implanted into the SOI layer from being diffused into the buried oxide layer or the semiconductor substrate.Type: GrantFiled: March 26, 2003Date of Patent: February 27, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Il Lee, Geum-Jong Bae, Ki-Chul Kim, Hwa-Sung Rhee, Sang-Su Kim
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Patent number: 7125458Abstract: A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.Type: GrantFiled: September 12, 2003Date of Patent: October 24, 2006Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Kwang Su Choe, Keith E. Fogel, Devendra K. Sadana
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Patent number: 7094668Abstract: A device and method for annealing a wafer. The preferred embodiment includes applying a basic thermal budget to a weakened zone of a wafer, substantially evenly over the weakened zone. The basic thermal budget is insufficient to detach a detachment layer from a remainder of the wafer at the weakened zone. An additional thermal budget is applied locally in an initiation region of the weakened zone to initiate the detachment of the detachment layer at the weakened zone.Type: GrantFiled: November 20, 2003Date of Patent: August 22, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Walter Schwarzenbach, Jean-Marc Waechter
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Patent number: 7084050Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.Type: GrantFiled: January 19, 2005Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi
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Patent number: 7071080Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.Type: GrantFiled: July 5, 2005Date of Patent: July 4, 2006Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Jeffrey L. Libbert
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Patent number: 7067402Abstract: A Separation by Implanted Oxygen (“SIMOX”) substrate and method for making thereof are provided. The SIMOX substrate can be produced by employing an oxygen ion implantation amount in a low dose range. The substrate is a high quality SOI substrate having an increased thickness of a BOX layer. More specifically, the SIMOX substrate and method for making the same are provided such that a buried oxide layer and a surface silicon layer are formed by applying the implantation of oxygen ions in a silicon substrate and a high temperature heat treatment thereafter. A buried oxide layer is provided by applying a high temperature heat treatment after an oxygen ion implantation; then applying an additional oxygen ion implantation so that the peak position of the distribution of implanted oxygen is located at a portion lower than the interface between the buried oxide layer, already formed, and the substrate thereunder. Then, another high temperature heat treatment is applied.Type: GrantFiled: March 28, 2002Date of Patent: June 27, 2006Assignee: Nippon Steel CorporationInventors: Atsuki Matsumura, Keisuke Kawamura, Yoichi Nagatake, Seiji Takayama
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Patent number: 7052981Abstract: Disclosed is an ion implantation method capable of preventing a channeling phenomenon caused by a lattice structure of a semiconductor substrate. The ion implantation method includes the steps of forming a predetermined mask pattern on the semiconductor substrate, performing an ion implantation process with respect to the semiconductor substrate exposed by the predetermined mask without forming a tilt angle, thereby forming an impurity area in the semiconductor substrate, and applying vibration to a lattice structure of the semiconductor substrate when the ion implantation process is carried out with respect to the semiconductor substrate.Type: GrantFiled: June 29, 2004Date of Patent: May 30, 2006Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Bong Soo Kim
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Patent number: 7037794Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.Type: GrantFiled: June 9, 2004Date of Patent: May 2, 2006Assignee: International Business Machines CorporationInventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Byeong Y. Kim
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Patent number: 7037806Abstract: A method of fabricating a semiconductor-on-insulator semiconductor substrate is disclosed that includes providing first and second semiconductor substrates. Either oxygen or nitrogen is introduced into a region adjacent the surface of the first semiconductor substrate and a rare earth is introduced into a region adjacent the surface of the second semiconductor substrate. The surface of the first semiconductor substrate is bonded to the surface of the second semiconductor substrate in a process that includes annealing to react either the oxygen or the nitrogen with the rare earth to form an interfacial insulating layer of either rare earth oxide or rare earth nitride. A portion of either the first semiconductor substrate or the second semiconductor substrate is removed and the surface polished to form a thin crystalline active layer on the insulating layer.Type: GrantFiled: February 9, 2005Date of Patent: May 2, 2006Assignee: Translucent Inc.Inventor: Petar B. Atanackovic
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Patent number: 7029991Abstract: The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a single layer of insulating material, a break at the sectional plane, so as to obtain an intermediate semiconductor substrate on the single insulating material layer; then, 2) in a second phase which consists in forming in the intermediate semiconductor substrate an additional insulating material layer adjacent to the single insulating material and topped with an upper layer of a final semiconductor substrate.Type: GrantFiled: June 21, 2001Date of Patent: April 18, 2006Assignee: STMicroelectronics S.A.Inventors: Vincent Le Goascoz, Herve Jaouen
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Patent number: 7008860Abstract: This invention provides a method of manufacturing a substrate having a thin buried insulating film. An insulating layer (12) is formed on a single-crystal Si substrate (11). Ions are implanted into the substrate (11) through the insulating layer (12) to form an ion-implanted layer (13). The insulating layer (12) is thinned down to form a thin insulating layer (12a). A thus prepared first substrate is placed on a second substrate (20) to form a bonded substrate stack (30). After that, the bonded substrate stack (30) is split at the ion-implanted layer (13).Type: GrantFiled: February 17, 2004Date of Patent: March 7, 2006Assignee: Canon Kabushiki KaishaInventors: Yasuo Kakizaki, Masataka Ito
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Patent number: 7005363Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.Type: GrantFiled: March 18, 2005Date of Patent: February 28, 2006Assignee: United Microelectronics Corp.Inventors: Joey Lai, Water Lur
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Patent number: 6967376Abstract: A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.Type: GrantFiled: April 26, 2004Date of Patent: November 22, 2005Assignee: International Business Machines CorporationInventors: Stephen R. Fox, Neena Garg, Kenneth J. Giewont, Junedong Lee, Devendra K. Sadana
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Patent number: 6959029Abstract: A wide-slit lateral growth projection mask, projection system, and corresponding crystallization process are provided. The mask includes an opaque region with at least one a transparent slit in the opaque region. The slit has a width in the range of 10X to 50X micrometers, with respect to a X:1 demagnification system, and a triangular-shaped slit end. The triangular-shaped slit end has a triangle height and an aspect ratio in the range of 0.5 to 5. The aspect ratio is defined as triangle height/slit width. In some aspects, the triangular-shaped slit end includes one or more opaque blocking features. In another aspect, the triangular-shaped slit end has stepped-shaped sides. The overall effect of the mask is to promote uniformly oriented grain boundaries, even in the film areas annealed under the slit ends.Type: GrantFiled: July 22, 2004Date of Patent: October 25, 2005Assignee: Sharp Laboratories of America, Inc.Inventors: Apostolos T. Voutsas, Mark A. Crowder, Yasuhiro Mitani
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Patent number: 6924216Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.Type: GrantFiled: May 19, 2003Date of Patent: August 2, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Thomas Feudel, Manfred Horstmann, Rolf Stephan
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Patent number: 6911379Abstract: A method of forming a strained-silicon-on-insulator substrate is disclosed. A target wafer includes an insulator layer on a substrate. A donor wafer includes a bulk semiconductor substrate having a lattice constant different from a lattice constant of silicon and a strained silicon layer formed on the bulk semiconductor substrate. The top surface of the donor wafer is bonded to the top surface of the target wafer. The strained silicon layer is then separated from the donor wafer so that the strained silicon layer adheres to the target wafer. The bond between the strained silicon layer and the target wafer can then be strengthened.Type: GrantFiled: March 5, 2003Date of Patent: June 28, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia Yeo, Wen-Chin Lee
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Patent number: 6861326Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.Type: GrantFiled: November 21, 2001Date of Patent: March 1, 2005Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Er-Xuan Ping
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Patent number: 6849526Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.Type: GrantFiled: February 17, 2004Date of Patent: February 1, 2005Assignee: Macronix International Co., Ltd.Inventors: Jiun-Ren Lai, Chun-Yi Yang, Shi-Xian Chen, Gwen Chang
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Patent number: 6846727Abstract: Methods for forming a patterned SOI region in a Si-containing substrate are provided which has geometries of about 0.25 ?m or less. The methods disclose each utilize a patterned dielectric mask that includes at least one opening having a size of about 0.25 ?m or less which exposes a portion of a Si-containing substrate. Oxygen ions are implanted through the opening using at least a base ion implantation process which is carried out at an oxygen beam energy of about 120 keV or less and an oxygen dosage of about 4E17 cm?2 or less. These conditions minimize erosion of the vertical edges of the patterned dielectric mask and minimize formation of lateral straggles.Type: GrantFiled: May 21, 2001Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Keith E. Fogel, Mark C. Hakey, Steven J. Holmes, Devendra K. Sadana, Ghavam G. Shahidi
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Publication number: 20040266213Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.Type: ApplicationFiled: June 30, 2004Publication date: December 30, 2004Inventors: Li Li, Pai-Hung Pan
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Publication number: 20040259338Abstract: In accordance with one embodiment of the present invention, a method of forming an etch stop layer in a semiconductor structure is provided. A polysilicon layer on the semiconductor substrate and ions are implanted into the polysilicon layer to form an etch stop layer. An oxide layer can be provided between the semiconductor substrate and the polysilicon layer.Type: ApplicationFiled: July 19, 2004Publication date: December 23, 2004Inventor: Vishnu K. Agarwal
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Publication number: 20040235273Abstract: Disclosed are an SOI substrate and a method for manufacturing the same. The SOI substrate comprises a silicon substrate including an active region defined by a field region. The field region includes a first oxygen-ion-injected isolation region having a first thickness and being formed under the active region. The center of the first region is at a first depth from a top surface of the silicon substrate. The field region of the SOI substrate further includes a second oxygen-ion-injected region having a second thickness greater than the first thickness. The second region is formed at sides of the active region and is also formed from a top surface of the silicon substrate. The center of the second ion injected region is at a second depth from the top surface of the silicon substrate. The first and second ion injected regions surround the active region for device isolation. The SOI substrate is formed by implementing two sequential ion injecting processes.Type: ApplicationFiled: June 22, 2004Publication date: November 25, 2004Applicant: Samsung Electronics Co., Ltd.Inventor: Tae-Ho Jang
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Patent number: 6821710Abstract: A mask including a material, which has heat resistance and light absorptivity, is selectively formed on a crystalline silicon film containing a catalytic element. Next, by using the mask, phosphorus is implanted into the silicon film and an implanted portion of the silicon film is transformed into amorphous. Then the silicon film is heated by a rapid thermal annealing (RTA) method, so that the temperature of the portion covered with the mask becomes higher than other portions. As a result, the catalytic element moves from the high temperature portion covered with the mask to the lower temperature amorphous portion in which phosphorus has been implanted and which has a large gettering capacity. Thus, the concentration of the catalytic element in the portion covered with the mask is lowered, and a semiconductor device is manufactured by using the film.Type: GrantFiled: April 19, 2000Date of Patent: November 23, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani
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Patent number: 6818529Abstract: A silicon on insulator substrate apparatus for fabricating an active-matrix liquid crystal display is described herein. The silicon on insulator substrate may include a handle substrate and a plurality of crystalline silicon donor portions bonded to the handle substrate. The crystalline silicon donor portions may be bonded to the handle substrate by providing a plurality of donor substrates and forming a separation layer within each donor substrate. The donor substrates may be arranged across a surface of the handle substrate and subsequently bonded to the handle substrate. The donor substrates may then be cleaved at their respective separation layers and removed from the handle substrate, thereby leaving a donor portion of each donor substrate attached the handle substrate.Type: GrantFiled: September 12, 2002Date of Patent: November 16, 2004Assignee: Applied Materials, Inc.Inventors: Robert Bachrach, Kam Law
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Publication number: 20040197972Abstract: A multi-pattern shadow mask, shadow mask laser annealing system, and a multi-pattern shadow mask method for laser annealing are provided. The method comprises: supplying a silicon substrate; supplying a multi-pattern shadow mask with a plurality of aperture patterns; creating substrate alignment marks; with respect to the alignment marks, laser annealing a substrate region in a plurality of aperture patterns; forming a corresponding plurality of polysilicon regions; and, forming a corresponding plurality of transistor channel regions in the plurality of polysilicon regions. In some aspects of the method laser annealing in a plurality of aperture patterns includes: laser annealing a first area in a substrate region with a first aperture pattern; and, stepping and repeating the laser annealing in a second area, adjacent the first area, in the substrate region.Type: ApplicationFiled: April 23, 2004Publication date: October 7, 2004Applicant: Sharp Laboratories of America, Inc.Inventors: Masahiro Adachi, Apostolos T. Voutsas
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Patent number: 6794264Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.Type: GrantFiled: April 30, 2002Date of Patent: September 21, 2004Assignee: Ibis Technology CorporationInventors: Robert P. Dolan, Bernhardt F. Cordts, III, Maria J. Anc, Micahel L. Alles
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Publication number: 20040180518Abstract: A method for forming a, single-crystal silicon layer on a transparent substrate. A transparent substrate having an amorphous silicon layer formed thereon and a silicon wafer having a hydrogen ion layer formed therein are provided. The silicon wafer is then reversed and laminated onto the amorphous silicon layer so that a layer of single-crystal silicon is between the hydrogen ion layer and the amorphous silicon layer. The laminated silicon wafer and the amorphous silicon layer are then subjected to laser or infrared light to cause chemical bonding of the single crystal silicon layer and the amorphous silicon layer and inducing a hydro-cracking reaction thereby separating the silicon wafer is and the transparent substrate at the hydrogen ion layer, and leaving the single-crystal silicon layer on the transparent substrate.Type: ApplicationFiled: July 28, 2003Publication date: September 16, 2004Applicant: Industrial Technology Research InstituteInventors: Chich Shang Chang, Chi-Shen Lee, Shun-Fa Huang, Jung Fang Chang, Wen-Chih Hu, Liang-Tang Wang, Chai-Yuan Sheu
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Patent number: 6774018Abstract: A plasma is produced in a treatment space by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes separated by a dielectric material, a vapor precursor is mixed with the plasma, and a substrate material is coated by vapor deposition of the vaporized substance at atmospheric pressure in the plasma field. The use of vaporized silicon-based materials, fluorine-based materials, chlorine-based materials, and organo-metallic complex materials enables the manufacture of coated substrates with improved properties with regard to moisture-barrier, oxygen-barrier, hardness, scratch- and abrasion-resistance, chemical-resistance, low-friction, hydrophobic and/or oleophobic, hydrophilic, biocide and/or antibacterial, and electrostatic-dissipative/conductive characteristics.Type: GrantFiled: August 26, 2002Date of Patent: August 10, 2004Assignee: Sigma Laboratories of Arizona, Inc.Inventors: Michael G. Mikhael, Angelo Yializis, Richard E. Ellwanger
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Patent number: 6774016Abstract: Disclosed are an SOI substrate and a method for manufacturing the same. The SOI substrate comprises a silicon substrate including an active region defined by a field region. The field region includes a first oxygen-ion-injected isolation region having a first thickness and being formed under the active region. The center of the first region is at a first depth from a top surface of the silicon substrate. The field region of the SOI substrate further includes a second oxygen-ion-injected region having a second thickness greater than the first thickness. The second region is formed at sides of the active region and is also formed from a top surface of the silicon substrate. The center of the second ion injected region is at a second depth from the top surface of the silicon substrate. The first and second ion injected regions surround the active region for device isolation. The SOI substrate is formed by implementing two sequential ion injecting processes.Type: GrantFiled: February 13, 2002Date of Patent: August 10, 2004Assignee: Samsung Electronics Co., Ltd.Inventor: Tae-Ho Jang
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Patent number: 6774017Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.Type: GrantFiled: July 3, 2002Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Jr., Randy William Mann, Steven Howard Voldman