Deposition Utilizing Plasma (e.g., Glow Discharge, Etc.) Patents (Class 438/485)
  • Patent number: 10294110
    Abstract: [Problem] To provide a novel production method for pentachlorodisilane and to obtain pentachlorodisilane having a purity of 90 mass % or more by carrying out this production method. [Solution] A production method provided with: a high-temperature reaction step in which a raw material gas containing vaporized tetrachlorosilane and hydrogen is reacted at a high temperature in order to obtain a reaction product gas containing trichlorosilane; a pentachlorodisilane generation step in which the reaction product gas obtained in the high-temperature reaction step is brought into contact with a cooling liquid obtained by circulative cooling of a condensate that is generated by cooling the reaction product gas, the reaction product gas is quickly cooled, and pentachlorodisilane is generated within the condensate; and a recovery step in which the generated pentachlorodisilane is recovered.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 21, 2019
    Assignees: DENKA COMPANY LIMTIED, L'AIR LIQUIDE SOCIETE ANONYME POUR L'ETUDE ET L'EXPLOITATION DES PROCEDES GEORGES CLAUDE
    Inventors: Hiroyuki Yashima, Takahiro Kozuka, Seiichi Terasaki, Jean-Marc Girard
  • Patent number: 10262872
    Abstract: There is provided a method of manufacturing a semiconductor device. The method includes: forming a first amorphous silicon film on a substrate in a process chamber; and etching a portion of the first amorphous silicon film using a hydrogen chloride gas under a temperature at which an amorphous state of the first amorphous silicon film is maintained, in the process chamber.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 16, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takahiro Miyakura, Atsushi Moriya, Naoharu Nakaiso, Kensuke Haga
  • Patent number: 10163383
    Abstract: Disclosed is a display device that may include a GIP circuit, provided on a display area of a substrate, for supplying gate signals to gate lines, wherein the GIP circuit includes a thin film transistor provided in the boundaries between adjacent pixels.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: December 25, 2018
    Assignee: LG Display Co., Ltd.
    Inventor: JungHyun Lee
  • Patent number: 9450139
    Abstract: A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Erika Kato
  • Patent number: 9324914
    Abstract: A semiconductor light-emitting device capable of keeping high luminance intensity even if electric power increases, and suitable for lighting instruments such as lights and lamps. The semiconductor device includes a metal electrode layer provided with openings, and is so large in size that the electrode layer has, for example, an area of 1 mm2 or more. The openings have a mean diameter of 10 nm to 2 ?m, and penetrate through the metal electrode layer. The metal electrode layer can be produced by use of self-assembling of block copolymer or by nano-imprinting techniques.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: April 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Fujimoto, Ryota Kitagawa, Koji Asakawa
  • Patent number: 9275855
    Abstract: A semiconductor thin-film manufacturing method includes: forming, above a substrate, an amorphous silicon film (precursor film) having a photoluminescence (PL) intensity greater than or equal to 0.65 when photon energy is 1.1 eV in a PL spectrum normalized to have a maximum PL intensity of 1; and annealing the amorphous silicon film to form a crystalline silicon film.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: March 1, 2016
    Assignee: JOLED INC.
    Inventors: Takahiro Kawashima, Hikaru Nishitani, Sei Ootaka
  • Patent number: 9257271
    Abstract: A method of manufacturing a semiconductor device includes: accommodating a substrate having an oxide film formed thereon into a processing chamber; supplying a process gas to the substrate; performing a preprocessing step in which the process gas is excited in a state that a pressure within the processing chamber is kept at a first pressure and an electric potential of the substrate is kept at a first electric potential; and performing a main processing step by which the process gas is excited in a state that the pressure within the processing chamber is kept at a second pressure and the electric potential of the substrate is kept at a second electric potential, wherein the first pressure is lower than the second pressure and the first electric potential is lower than the second electric potential.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 9, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Tatsushi Ueda
  • Patent number: 9023693
    Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Kung-Liang Lin, Chien-Chih Chen, Fu-Ching Tung, Chih-Yung Chen, Shih-Chin Lin, Kuan-Yu Lin, Chia-Hao Chang, Shieh-Sien Wu
  • Publication number: 20150093885
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device. The method includes introducing an inert gas and a material gas into a predetermined space, applying a voltage to generate plasma in the space after introducing the inert gas and the material gas so as to form a semiconductor layer on a substrate, introducing an oxidation-reduction gas in the predetermined space after the voltage is applied, and stopping the introduction of the material gas, the inert gas, and the oxidation-reduction gas after the voltage is applied.
    Type: Application
    Filed: March 3, 2014
    Publication date: April 2, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinya Okuda, Ichiro Mizushima, Kie Watanabe
  • Patent number: 8962454
    Abstract: Embodiments of the invention describe a method for forming dielectric films for semiconductor devices. The method includes providing a substrate in a process chamber containing a microwave plasma source, introducing into the process chamber a non-metal-containing process gas including a deposition gas having a carbon-nitrogen intermolecular bond, forming a plasma from the process gas, and exposing the substrate to the plasma to deposit carbon-nitrogen-containing film on the substrate. In some embodiments, the carbon-nitrogen-containing film can include a CN film, a CNO film, a Si-doped CN film, or a Si-doped CNO film.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: February 24, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Hiroyuki Takaba
  • Patent number: 8952499
    Abstract: An integrated circuit is provided with a substrate, an electrode, two diffusion areas, and a resistance heater. The substrate includes a first surface and second surface that are substantially parallel to each other. The electrode is laminated onto the first surface. The two diffusion areas are disposed within the substrate in the vicinity of the electrode to form one transistor with the electrode. The resistance heater is located on an area of the second surface across the substrate from the electrode. The resistance heater produces heat by allowing electric current to flow.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: February 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takashi Morimoto, Takashi Hashimoto
  • Patent number: 8946061
    Abstract: In one embodiment, a method of producing a porous semiconductor film on a workpiece includes generating semiconductor precursor ions that comprise one or more of: germanium precursor ions and silicon precursor ions in a plasma of a plasma chamber, in which the semiconductor precursor ions are operative to form a porous film on the workpiece. The method further includes directing the semiconductor precursor ions to the workpiece over a range of angles.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Varian Semiconductor Equiptment Associates, Inc.
    Inventors: Blake Darby, Ludovic Godet, Xianfeng Lu
  • Patent number: 8937000
    Abstract: A chemical vapor deposition reactor and method. Reactive gases, such as gases including a Group III metal source and a Group V metal source, are introduced into the chamber (10) of a rotating-disc reactor and directed downwardly onto a wafer carrier (32) and substrates (40) which are maintained at an elevated substrate temperature, typically above about 400° C. and normally about 700-1100° C. to deposit a compound such as a III-V semiconductor. The gases are introduced into the reactor at an inlet temperature desirably above about 75° C. and most preferably about 100°-350° C. The walls of the reactor may be at a temperature close to the inlet temperature. Use of an elevated inlet temperature allows the use of a lower rate of rotation of the wafer carrier, a higher operating pressure, lower flow rate, or some combination of these.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: January 20, 2015
    Assignee: Veeco Instruments Inc.
    Inventors: Alex Gurary, Mikhail Belousov, Bojan Mitrovic
  • Patent number: 8916453
    Abstract: A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gopalakrishnan Trichy Rengarajan, Armin Tilke
  • Patent number: 8906790
    Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Albert Lee, Tony P. Chiang, Jason Wright
  • Publication number: 20140357064
    Abstract: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Keith Fox, Dong Niu, Joseph L. Womack
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Patent number: 8895414
    Abstract: A method of forming an amorphous silicon film includes: forming a seed layer on a surface of a base by heating the base and supplying an amino silane-based gas to the heated base, forming the amorphous silicon film with thickness for layer growth on the seed layer by heating the base and supplying a silane-based gas containing no amino group to the seed layer on the surface of the heated base, and decreasing a film thickness of the amorphous silicon film by etching the amorphous silicon film formed with thickness for layer growth.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: November 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Akinobu Kakimoto, Satoshi Takagi, Kazumasa Igarashi
  • Patent number: 8895415
    Abstract: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: November 25, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Keith Fox, Dong Niu, Joseph L. Womack
  • Patent number: 8859404
    Abstract: A seed crystal including mixed phase grains having high crystallinity at a low density is formed under a first condition over an insulating film, and then a first microcrystalline semiconductor film is formed over the seed crystal under a second condition that allows the mixed phase grains to grow and a space between the mixed phase grains to be filled. Then, a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a third condition that allows formation of a microcrystalline semiconductor film having high crystallinity without increasing the space between the mixed phase grains included in the first microcrystalline semiconductor film.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryu Komatsu, Yasuhiro Jinbo, Hidekazu Miyairi
  • Publication number: 20140264319
    Abstract: An organic material with a porous interpenetrating network and an amount of inorganic material at least partially distributed within the porosity of the organic material is disclosed. A method of producing the organic-inorganic thin films and devices therefrom comprises seeding with nanoparticles and depositing an amorphous material on the nanoparticles.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: THE BOEING COMPANY
    Inventor: The Boeing Company
  • Patent number: 8822313
    Abstract: Embodiments provided herein describe methods and systems for processing substrates. A plasma including radical species and charged species is generated. The charged species of the plasma are collected. A substrate is exposed to the radical species of the plasma. A layer is formed on the substrate after exposing the substrate to the radical species.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 2, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Chi-I Lang, Sandip Niyogi
  • Patent number: 8802547
    Abstract: A method of forming an amorphous silicon film includes: forming a seed layer on a surface of a base by heating the base and supplying an amino silane-based gas to the heated base, forming the amorphous silicon film with thickness for layer growth on the seed layer by heating the base and supplying a silane-based gas containing no amino group to the seed layer on the surface of the heated base, and decreasing a film thickness of the amorphous silicon film by etching the amorphous silicon film formed with thickness for layer growth.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: August 12, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Akinobu Kakimoto, Satoshi Takagi, Kazumasa Igarashi
  • Publication number: 20140206180
    Abstract: A thin film formation method to form an amorphous silicon film containing an impurity on a surface of an object to be processed in a process chamber that allows vacuum exhaust includes supplying a silane-based gas composed of silicon and hydrogen into the process chamber in a state that the silane-based gas is adsorbed onto the surface of the object without supplying an impurity-containing gas, supplying the impurity-containing gas into the process chamber to form the amorphous silicon film containing the impurity without supplying the silane-based gas, and performing the supplying of the silane-based gas and the supplying of the impurity-containing gas alternately and repeatedly such that the impurity reacts with the silane-based gas.
    Type: Application
    Filed: February 28, 2014
    Publication date: July 24, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kazuhide HASEBE, Akinobu KAKIMOTO
  • Patent number: 8728951
    Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
  • Publication number: 20140113439
    Abstract: A method is for depositing in a chamber an amorphous silicon layer on a surface of a semiconducting or insulating substrate. In the method, the surface is pretreated with a NH3 plasma prior to deposition of the amorphous silicon layer.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 24, 2014
    Applicant: SPTS TECHNOLOGIES LIMITED
    Inventors: JASH PATEL, YUFEI LIU
  • Patent number: 8704445
    Abstract: A method for improving the uniformity of high-frequency discharge plasma by means of frequency modulation is disclosed. In a plasma discharge chamber, there is a pair of parallel electrodes. A high-frequency power supply is adopted to feed the electrodes. The frequency range of the electromagnetic field is 13.56 MHz˜160 MHz. Discharge gas is input to form plasma. The frequency of the fed-in high-frequency electromagnetic field is under automatic tuning control, and keeps changing cyclically without stop in the course of plasma discharge. The range of the frequency change may fall into either a portion of or the entire range of 13.56 MHz˜160 MHz and makes the locations with higher plasma density on the plane in parallel with the electrodes and in the plasma discharge space changed cyclically. In a time slot longer than one frequency change cycle, the average plasma density between the parallel electrodes is uniform.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 22, 2014
    Assignee: Beijing University of Technology
    Inventors: Bo Wang, Lichun Xu, Ming Zhang, Ruzhi Wang, Xuemei Song, Yudong Hou, Mankang Zhu, Jingbing Liu, Hao Wang, Hui Yan
  • Patent number: 8703586
    Abstract: In order to form a high quality film without causing in-plane nonuniformity in film quality, an apparatus for forming deposited film according to an aspect of the present invention includes: a chamber; a first electrode located in the chamber; a second electrode that is located in the chamber with a predetermined spacing from the first electrode and includes a plurality of supply parts configured to supply material gases; an introduction path connected to the supply parts, through which the material gases are introduced; a heater located in the introduction path; and a cooling mechanism configured to cool the second electrode.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: April 22, 2014
    Assignee: KYOCERA Corporation
    Inventors: Norikazu Ito, Shinichiro Inaba, Hiroshi Matsui, Koichiro Niira
  • Patent number: 8658522
    Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya Sato, Patricia M. Liu, Fanos Christodoulou
  • Patent number: 8652944
    Abstract: Fabricating semiconductor nanowires (5) on a substrate (1) having a metallic oxide layer (2), includes: a) exposing the metallic oxide layer to a hydrogen plasma (11) of power P for a duration t suitable for reducing the layer and for forming metallic nanodrops (3) of radius (Rm) on the surface of the metallic oxide layer; b) low temperature plasma-assisted deposition of a thin layer (4) of a semiconductor material on the metallic oxide layer including the metallic nanodrops, the thin layer having a thickness (Ha) suitable for covering the metallic nanodrops; and c) thermal annealing at a temperature T sufficient to activate lateral growth of nanowires by catalysis of the material deposited as a thin layer from the metallic nanodrops. Nanowires are obtained by this method and nanometric transistors including a semiconductor nanowire.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: February 18, 2014
    Assignees: Ecole Polytechnique, Centre National de la Recherche Scientifique
    Inventors: Pere Roca I Cabarrocas, Linwei Yu
  • Patent number: 8633094
    Abstract: A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: January 21, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Jamal Ramdani, Linlin Liu, John Paul Edwards
  • Patent number: 8631762
    Abstract: A plasma CVD apparatus includes: a film forming chamber; a holding member that holds a substrate to be processed that is set in the film forming chamber; a shower head that is set in the film forming chamber to face the holding member, and supplies raw material gas and generates a plasma of the raw material gas; a radical generation chamber that is set at an opposite side of the shower head relative to the holding member and generates radicals of process gas; and an openable and closable shutter that is provided between the shower head and the radical generation chamber.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: January 21, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mikio Yamamuka, Tae Orita, Hiroya Yamarin
  • Patent number: 8623471
    Abstract: A plasma treatment system for treating a workpiece with a downstream-type plasma. The processing chamber of the plasma treatment system includes a chamber lid having a plasma cavity disposed generally between a powered electrode and a grounded plate, a processing space separated from the plasma cavity by the grounded plate, and a substrate support in the processing space for holding the workpiece. A direct plasma is generated in the plasma cavity. The grounded plate is adapted with openings that remove electrons and ions from the plasma admitted from the plasma cavity into the processing space to provide a downstream-type plasma of free radicals. The openings may also eliminate line-of-sight paths for light between the plasma cavity and processing space. In another aspect, the volume of the processing chamber may be adjusted by removing or inserting at least one removable sidewall section from the chamber lid.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: January 7, 2014
    Assignee: Nordson Corporation
    Inventors: James S. Tyler, James D. Getty, Robert S. Condrashoff, Thomas V. Bolden, II
  • Patent number: 8609519
    Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: December 17, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Albert Lee, Tony P. Chiang, Jason Wright
  • Patent number: 8597969
    Abstract: In an optical semiconductor device including a semiconductor laminated body including at least a light emitting layer, a first metal body including at least one first metal layer formed on the semiconductor laminated body, a support substrate, a second metal body including at least one second metal layer formed on the support substrate, and at least one adhesive layer formed in a surface side of at least one of the first and second metal bodies, the semiconductor laminated body is coupled to the support substrate by applying a pressure-welding bonding process upon the adhesive layer to form a eutectic alloy layer between the first and second metal bodies. At least one of the first and second metal layers has a triple structure formed by two tight portions and a coarse portion sandwiched by the tight portions.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: December 3, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Noriko Nihei, Shinichi Tanaka, Yusuke Yokobayashi
  • Patent number: 8551871
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Shinji Mori, Masahiko Murano, Tsutomu Sato, Takashi Nakao, Hiroshi Itokawa
  • Patent number: 8501631
    Abstract: A method for controlling a plasma processing system using wafer bias information derived from RF voltage information is proposed. The RF voltage is processed via an analog or digital methodology to obtain peak voltage information at least for each of the fundamental frequencies and the broadband frequency. The peak voltage information is then employed to derive the wafer bias information to serve as a feedback or control signal to hardware/software of the plasma processing system.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: August 6, 2013
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Henry S. Povolny
  • Patent number: 8486222
    Abstract: A substrate processing apparatus includes a processing chamber configured to process a substrate, a substrate support member provided within the processing chamber to support the substrate, a microwave generator provided outside the processing chamber, a waveguide launch port configured to supply a microwave generated by the microwave generator into the processing chamber, wherein the central position of the waveguide launch port is deviated from the central position of the substrate supported on the substrate support member and the waveguide launch port faces a portion of a front surface of the substrate supported on the substrate support member, and a control unit configured to change a relative position of the substrate support member in a horizontal direction with respect to the waveguide launch port.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 16, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Tokunobu Akao, Unryu Ogawa, Masahisa Okuno, Shinji Yashima, Atsushi Umekawa, Kaichiro Minami
  • Patent number: 8455268
    Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: June 4, 2013
    Assignee: Spansion LLC
    Inventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Rinji Sugino, Chi Chang, Huaqiang Wu
  • Patent number: 8450139
    Abstract: A method for manufacturing a photoelectric conversion device including a forming a semiconductor film by a plasma CVD method. The semiconductor film is an amorphous film of SiGe-based compound or a microcrystalline film of SiGe-based compound. The plasma CVD controls bandgap in thickness direction of the semiconductor film by varying the ON or OFF time of electric power applied to generate a plasma and intermittently supplying the power. The ON time and OFF time of the power fall in a range where the duty ratio ON time/(ON time+OFF time)×100(%) is 10% or more and 50% or less.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: May 28, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuaki Ishikawa, Shinya Honda, Makoto Higashikawa
  • Patent number: 8443756
    Abstract: Showerhead electrodes for a semiconductor material processing apparatus are disclosed. An embodiment of the showerhead electrodes includes top and bottom electrodes bonded to each other. The top electrode includes one or more plenums. The bottom electrode includes a plasma-exposed bottom surface and a plurality of gas holes in fluid communication with the plenum. Showerhead electrode assemblies including a showerhead electrode flexibly suspended from a top plate are also disclosed. The showerhead electrode assemblies can be in fluid communication with temperature-control elements spatially separated from the showerhead electrode to control the showerhead electrode temperature. Methods of processing substrates in plasma processing chambers including the showerhead electrode assemblies are also disclosed.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: May 21, 2013
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, Rajinder Dhindsa
  • Patent number: 8445310
    Abstract: The present invention provides a stacked-layered thin film solar cell and manufacturing method thereof The manufacturing method includes the steps of: providing a substrate, a first electrode layer and a first light-absorbing layer; providing a mask with a plurality of patterns above the first light-absorbing layer; forming an interlayer made of an opaque, highly reflective material by providing the mask on the first light-absorbing layer, wherein the interlayer has a plurality of light transmissive regions corresponding to the patterns, and the light transmissive regions are provided to divide the interlayer into a plurality of units; and then depositing a second light-absorbing layer on the units and a second electrode layer on the second light-absorbing layer.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 21, 2013
    Assignee: Nexpower Technology Corp.
    Inventors: Chien-Chung Bi, Chun-Hsiung Lu
  • Patent number: 8426295
    Abstract: To provide a manufacturing method of a microcrystalline silicon film having both high crystallinity and high film density. In the manufacturing method of a microcrystalline silicon film according to the present invention, a first microcrystalline silicon film that includes mixed phase grains is formed over an insulating film under a first condition, and a second microcrystalline silicon film is formed thereover under a second condition. The first condition and the second condition are a condition in which a deposition gas containing silicon and a gas containing hydrogen are used as a first source gas and a second source gas. The first source gas is supplied under the first condition in such a manner that supply of a first gas and supply of a second gas are alternately performed.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: April 23, 2013
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Ryu Komatsu, Yasuhiro Jinbo, Hidekazu Miyairi, Yoshitaka Yamamoto
  • Patent number: 8394709
    Abstract: A process for producing a high-performance photovoltaic device by depositing a high-quality crystalline silicon layer, and a deposition apparatus for depositing the high-quality crystalline silicon layer. A process for producing a photovoltaic device that comprises forming a crystalline silicon-based photovoltaic layer comprising an i-layer on a substrate using a plasma-enhanced CVD method, wherein formation of the i-layer comprises an initial layer deposition stage and a bulk i-layer deposition stage, and the initial layer deposition stage comprises depositing the initial layer using a silane-based gas flow rate during the initial layer deposition stage that is lower than the silane-based gas flow rate during the bulk i-layer deposition stage, with the deposition time for the initial layer deposition stage set to not less than 0.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: March 12, 2013
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Hiroomi Miyahara, Kengo Yamaguchi
  • Publication number: 20130052808
    Abstract: A method is provided for forming a semiconductor device. The method includes providing a substrate on a substrate holder in a process chamber, where the substrate contains a raised feature having a top surface and a sidewall surface, and flowing a process gas into the process chamber, where the process gas contains a hydrocarbon gas, an oxygen-containing gas, and optionally argon or helium. The method further includes maintaining a process gas pressure of at least 1 Torr in the process chamber, forming a plasma from the process gas using a microwave plasma source, and exposing the substrate to the plasma to deposit a conformal amorphous carbon film over the surfaces of the raised feature.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Takaba
  • Patent number: 8343857
    Abstract: To provide a manufacturing method of a microcrystalline semiconductor film, the manufacturing method comprises the steps of forming a first semiconductor film over a substrate by generating plasma by performing continuous discharge under an atmosphere containing a deposition gas; forming a second semiconductor film over the first semiconductor film by generating plasma by performing pulsed discharge under the atmosphere containing the deposition gas; forming a third semiconductor film over the second semiconductor film by generating plasma by performing continuous discharge under the atmosphere containing the deposition gas; and forming a fourth semiconductor film over the third semiconductor film by generating plasma by performing pulsed discharge under the atmosphere containing the deposition gas.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoshi Toriumi
  • Patent number: 8313805
    Abstract: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which includes an inner electrode mechanically attached to a backing plate by a clamp ring and an outer electrode attached to the backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release cam pins extending upward from the upper face of the outer electrode. To compensate for differential thermal expansion, the clamp ring can include expansion joins at spaced locations which allow the clamp ring to absorb thermal stresses.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 20, 2012
    Assignee: Lam Research Corporation
    Inventors: Babak Kadkhodayan, Rajinder Dhindsa, Anthony de la Llera, Michael C. Kellogg
  • Patent number: 8312840
    Abstract: Disclosed is a substrate processing apparatus and method. The substrate processing apparatus includes a chamber (10) providing an internal space, in which a process is carried out onto a substrate; a gas supply unit (40) supplying a source gas to the internal space; a coil (16) generating an electric field in the internal space to generate plasma from the source gas; and an adjustment ring (50) disposed on a flow path of the plasma toward a support member to adjust the flow of the plasma. The chamber (10) includes a process chamber (12), in which the support member is provided and the process is carried out by the plasma; and a generation chamber (14), in which the plasma is generated by the coil (16), provided on the upper surface of the process chamber (12), and the adjustment ring (50) is installed at the lower end of the generation chamber (14).
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: November 20, 2012
    Assignee: Eugene Technology Co., Ltd.
    Inventor: Il-Kwang Yang
  • Patent number: 8297226
    Abstract: A movable deposition box (02) for silicon-based thin film solar cell comprises an electrode array composed of at least a group of cathode plates (203) and a piece of anode plate (208) which are set in movable chamber, wherein a feeding socket (203-1) is positioned on a circular or semicircular concave surface in the center area on the backside of the cathode plates (203), a circular or semicircular end face (201-1) of a feeding component (201) which has a flat middle part contacts the signal feeding socket (203-1) and feeds in RF/VHF power signal, the anode plate (208) is grounded, and a shield cover (204) of the cathode plate has through-hole (204-1) and is insulated from the cathode plate (203).
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: October 30, 2012
    Assignee: Shenzhen Trony Science & Technology Development Co., Ltd.
    Inventor: Yi Li
  • Patent number: 8291858
    Abstract: A movable jig for a silicon-based thin film solar cell comprises parallel electrode plates (203,208), a supporting frame and a signal feed-in assembly (201). The supporting frame is a movable frame and its side frame (216) is grounded. A shield device is set on the jig or among jig arrays themselves for preventing from being disturbed. The signal feed-in assembly is a conductor and its middle portion and head portion form a ladder cylinder, and one end surface (201-1) of the signal feed-in assembly is triangular and can surface contact and connect with a sunken triangular feed-in port (203-1) in the center area of the back surface of the cathode plate (203) of the electrode plates, so the radio frequency/the very high frequency power supply signal can be fed in.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: October 23, 2012
    Assignee: Shenzhen Trony Science & Technology Development Co., Ltd.
    Inventors: Shengming Hu, Yi Li, Zhubing He, Zhijiang Li, Jianhua Zhou, Chunzhu Wang