Deposition Utilizing Plasma (e.g., Glow Discharge, Etc.) Patents (Class 438/485)
  • Patent number: 7842586
    Abstract: As an electrode area of a plasma CVD apparatus is enlarged, influence of the surface standing wave remarkably appears, and there is a problem in that in-plane uniformity of quality and a thickness of a thin film formed over a glass substrate is degraded. Two or more high-frequency electric powers with different frequencies are supplied to an electrode for producing glow discharge plasma in a reaction chamber. With glow discharge plasma produced by supplying the high-frequency electric powers with different frequencies, a semiconductor thin film or an insulating thin film is formed. High-frequency electric powers with different frequencies (different wavelengths), which are superimposed on each other, are applied to an electrode in a plasma CVD apparatus, so that increase in plasma density and uniformity for preventing effect of surface standing wave of plasma are attained.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: November 30, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7833885
    Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: November 16, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Tae Kyung Won, Soo Young Choi, Dong Kil Yim, Jriyan Jerry Chen, Beom Soo Park
  • Patent number: 7829444
    Abstract: Provided is a novel method for manufacturing a field effect transistor. Prior to forming an amorphous oxide layer on a substrate, ultraviolet rays are irradiated onto the substrate surface in an ozone atmosphere, plasma is irradiated onto the substrate surface, or the substrate surface is cleaned by a chemical solution containing hydrogen peroxide.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: November 9, 2010
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Hisato Yabuta, Masafumi Sano, Tatsuya Iwasaki, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7799661
    Abstract: A device (101) for controlling the treatment of a substrate (102) with a plasma (103) is provided which comprises (a) a plasma chamber (104) adapted to generate a plasma (103); (b) a sensor (113) equipped with first (115) and second (117) electrodes that are exposed to the plasma generated within the chamber, said sensor being adapted to (i) apply a first low frequency voltage V1 to the first electrode, (ii) apply a plurality of high frequency voltages V2 . . . Vn to the first electrode, where n?2, and (iii) measure the respective currents I1 . . . In flowing through the second electrode during application of each of the voltages V1 . . . Vn, respectively; and (c) a data processing device (121) adapted to determine the densities of a plurality of ion species based on currents I1 . . . In and on a mathematical model or on calibration data relating to the plasma chamber.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: September 21, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Shahid Rauf
  • Patent number: 7799632
    Abstract: One embodiment of the present invention relates to a method of forming an isolation structure. During this method, an isolation trench is formed within a semiconductor body. After this trench is formed, it is filled by performing multiple high-frequency plasma depositions to deposit multiple dielectric layers over the semiconductor body. A first of the multiple layers is deposited at a high-frequency power of between approximately 100 watts and approximately 900 watts.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: September 21, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Jin Zhao, Manuel Quevedo-Lopez, Louis H. Breaux
  • Patent number: 7790478
    Abstract: In remote plasma cleaning, it is difficult to locally excite a plasma because the condition is not suitable for plasma excitation different from that at the time of film formation and a method using light has a problem of fogginess of a detection window that cannot be avoided in a CVD process and is not suitable for a mass production process.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: September 7, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyuki Fujii, Minoru Hanazaki, Gen Kawaharada, Masakazu Taki, Mutsumi Tsuda
  • Publication number: 20100151664
    Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.
    Type: Application
    Filed: February 25, 2010
    Publication date: June 17, 2010
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
  • Patent number: 7727864
    Abstract: Metallic-compound films are formed by plasma-enhanced atomic layer deposition (PEALD). According to preferred methods, film or thin film composition is controlled by selecting plasma parameters to tune the oxidation state of a metal (or plurality of metals) in the film. In some embodiments, plasma parameters are selected to achieve metal-rich metallic-compound films. The metallic-compound films can be components of gate stacks, such as gate electrodes. Plasma parameters can be selected to achieve a gate stack with a predetermined work function.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: June 1, 2010
    Assignee: ASM America, Inc.
    Inventor: Kai-Erik Elers
  • Patent number: 7723218
    Abstract: In a plasma CVD apparatus, unnecessary discharge such as arc discharge is prevented, the amount of particles due to peeling of films attached to a reaction chamber is reduced, and the percentage of a time contributing to production in hours of operation of the apparatus is increased while enlargement of the apparatus and easy workability are maintained. The plasma CVD apparatus is configured such that in a conductive reaction chamber 104 with a power source 113, a vacuum exhausting means 118, and a reaction gas introduction pipe 114, plasma 115 is generated in a space surrounded by an electrode 111, a substrate holder 112, and an insulator 120.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: May 25, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Mitsunori Sakama, Hisashi Abe, Hiroshi Uehara, Mika Ishiwata
  • Publication number: 20100105195
    Abstract: An apparatus is described for depositing a film on a substrate from a plasma. The apparatus comprises an enclosure, a plurality of plasma generator elements disposed within the enclosure, and means, also within the enclosure, for supporting the substrate. Each plasma generator element comprises a microwave antenna having an end from which microwaves are emitted, a magnet disposed in the region of the said antenna end and defining therewith an electron cyclotron resonance region in which a plasma can be generated, and a gas entry element having an outlet for a film precursor gas or a plasma gas. The outlet is arranged to direct gas towards a film deposition area situated beyond the magnet, as considered from the microwave antenna, the outlet being located in, or above, the hot electron confinement envelope.
    Type: Application
    Filed: October 26, 2007
    Publication date: April 29, 2010
    Applicants: DOW CORNING CORPORATION, ECOLE POLYTECHNIQUE
    Inventors: Pere Roca I Cabarrocas, Pavel Bulkin, Dmitri Daineka, Patrick Leempoel, Pierre Descamps, Thibault Kervyn De Meerendre
  • Patent number: 7691658
    Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1?xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1?xN nucleation layer, and cooling the substrate under a nitrogen overpressure.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: April 6, 2010
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: John F. Kaeding, Dong-Seon Lee, Michael Iza, Troy J. Baker, Hitoshi Sato, Benjamin A. Haskell, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 7687293
    Abstract: A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al,In,Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: March 30, 2010
    Assignee: The Regents of the University of California
    Inventors: Hiroshi Sato, John F. Kaeding, Michael Iza, Troy J. Baker, Benjamin A. Haskell, Steven P. DenBaars, Shuji Nakamura
  • Publication number: 20100075449
    Abstract: Methods and systems for forming an amorphous silicon layer are disclosed for one or more embodiments. For example, a substrate may be provided, and an amorphous silicon layer, in which a ratio of Si—H to Si—H2 has a value equal to or less than 4 to 1, may be formed on the substrate using chemical vapor deposition equipment.
    Type: Application
    Filed: March 5, 2009
    Publication date: March 25, 2010
    Inventors: Tae-Hyung HWANG, Hyung-Ii Jeon, Seok-Joon Hong
  • Publication number: 20100075458
    Abstract: A method is described of forming a film of an amorphous material on a substrate (14) by deposition from a plasma. The substrate (14) is placed in an enclosure, a film precursor gas is introduced into the enclosure through pipes (20), and unreacted and dissociated gas is extracted from the enclosure through pipes (22) so as to provide a low pressure therein. Microwave energy—is introduced into the gas within the enclosure as a sequence of pulses at a given frequency and power level to produce a plasma therein by distributed electron cyclotron resonance (DECR) and cause material to be deposited from the plasma on the substrate. The frequency and/or power level of the pulses is altered during the course of deposition of material, so as to cause the bandgap to vary over the thickness of the deposited material.
    Type: Application
    Filed: October 26, 2007
    Publication date: March 25, 2010
    Applicants: Dow Corning Corporation, Ecole Polytechnique
    Inventors: Pere Roca I Cabarrocas, Pavel Bulkin, Dmitri Daineka, Patrick Leempoel, Pierre Descamps, Thibault Kervyn De Meerendre
  • Publication number: 20100068870
    Abstract: A method and apparatus for the unusually high rate deposition of thin film materials on a stationary or continuous substrate. The method includes delivery of a pre-selected precursor intermediate to a deposition chamber and formation of a thin film material from the intermediate. The intermediate is formed outside of the deposition chamber and includes a metastable species such as a free radical. The intermediate is pre-selected to include a metastable species conducive to the formation of a thin film material having a low defect concentration. By forming a low defect concentration material, deposition rate is decoupled from material quality and heretofore unprecedented deposition rates are achieved. In one embodiment, the pre-selected precursor intermediate is SiH3.
    Type: Application
    Filed: September 12, 2008
    Publication date: March 18, 2010
    Inventor: Stanford R Ovshinsky
  • Publication number: 20100006812
    Abstract: Memory devices including a carbon-based resistivity-switchable material, and methods of forming such memory devices are provided, the methods including introducing a processing gas into a processing chamber, wherein the processing gas includes a hydrocarbon compound and a carrier gas, and generating a plasma of the processing gas to deposit a layer of the carbon-based switchable material on a substrate within the processing chamber. Numerous additional aspects are provided.
    Type: Application
    Filed: July 8, 2009
    Publication date: January 14, 2010
    Applicant: SanDisk 3D LLC
    Inventors: Huiwen Xu, Xiying Chen, Roy E. Scheuerlein, Er-Xuan Ping, Tanmay Kumar, Alper Ilkbahar
  • Patent number: 7638413
    Abstract: A method of fabricating a semiconductor uses chemical vapor deposition, or plasma-enhanced chemical vapor deposition, to deposit an amorphous silicon film on an exposed surface of a substrate, such as ASIC wafer. The amorphous silicon film is doped with nitrogen to reduce the conductivity of the film and/or to augment the breakdown voltage of the film. Nitrogen gas, N2, is activated or ionized in a reactor before it is deposited on the substrate.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: December 29, 2009
    Assignee: Pan Jit Americas, Inc.
    Inventors: Michael Kountz, George Engle, Steven Evers
  • Patent number: 7622369
    Abstract: A method of forming device isolation regions on a trench-formed silicon substrate and removing residual carbon therefrom includes providing a flowable, insulative material constituted by silicon, carbon, nitrogen, hydrogen, oxygen or any combination of two or more thereof; forming a thin insulative layer, by using the flowable, insulative material, in a trench located on a semiconductor substrate wherein the flowable, insulative material forms a conformal coating in a silicon and nitrogen rich condition whereas in a carbon rich condition, the flowable, insulative material vertically grows from the bottom of the trenches; and removing the residual carbon deposits from the flowable, insulative material by multi-step curing, such as O2 thermal annealing, ozone UV curing followed by N2 thermal annealing.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: November 24, 2009
    Assignee: ASM Japan K.K.
    Inventors: Woo Jin Lee, Atsuki Fukazawa, Nobuo Matsuki
  • Patent number: 7601619
    Abstract: A method and an apparatus for plasma processing which can accurately monitor an ion current applied to the surface of a sample. Predetermined gas is exhausted via an exhaust port by a turbo-molecular pump while introducing the gas within the vacuum chamber from a gas supply device, and the pressure within the vacuum chamber is kept at a predetermined value by a pressure regulating valve. A high-frequency power supply for a plasma source supplies a high-frequency power to a coil provided near a dielectric window to generate inductively coupled plasma within the vacuum chamber. A high-frequency power supply for the sample electrode for supplying the high-frequency power to the sample electrode is provided. A matching circuit for the sample electrode and a high-frequency sensor are provided between the sample electrode high-frequency power supply and the sample electrode. An ion current applied to the surface of a sample can be accurately monitored buy using the high-frequency sensor and an arithmetic device.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: October 13, 2009
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno, Cheng-Guo Jin, Ichiro Nakayama
  • Publication number: 20090233425
    Abstract: By an evacuation unit including first and second turbo molecular pumps connected in series, the ultimate pressure in a reaction chamber is reduced to ultra-high vacuum. By a knife-edge-type metal-seal flange, the amount of leakage in the reaction chamber is reduced. A microcrystalline semiconductor film and an amorphous semiconductor film are stacked in the same reaction chamber where the pressure is reduced to ultra-high vacuum. By forming the amorphous semiconductor film covering the surface of the microcrystalline semiconductor film, oxidation of the microcrystalline semiconductor film is prevented.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 17, 2009
    Inventors: Makoto FURUNO, Tetsuo SUGIYAMA, Taichi NOZAWA, Mitsuhiro ICHIJO, Ryota TAJIMA, Shunpei YAMAZAKI
  • Patent number: 7588990
    Abstract: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber and furnishing a hydrocarbon process gas into the chamber, preferably propylene (C3H6) or toluene (C7H8) or acetylene (C2H2) or a mixture of acetylene and methane (C2H4). The process further includes inductively coupling RF plasma source power into the chamber while and applying RF plasma bias power to the wafer. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired stress (compressive or tensile). We have discovered that at a wafer temperature less than or equal to 475 degrees C.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: September 15, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Vijay Parihar, Christopher Dennis Bencher, Rajesh Kanuri, Marlon E. Menezes
  • Patent number: 7575947
    Abstract: A method for growing a semi-polar nitride semiconductor thin film via metalorganic chemical vapor deposition (MOCVD) on a substrate, wherein a nitride nucleation or buffer layer is grown on the substrate prior to the growth of the semi-polar nitride semiconductor thin film.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: August 18, 2009
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Michael Iza, Troy J. Baker, Benjamin A. Haskell, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 7557027
    Abstract: A method of depositing a structural SiGe layer is presented. The structural SiGe layer may be located on top of a sacrificial layer above a substrate. The substrate may contain a semiconductor device such as a CMOS electronic circuit. The presented method uses a silicon source and a germanium source in a reaction zone to grow the structural SiGe layer. Hydrogen is introduced into the reaction zone and it may be used to dilute the silicon source and the germanium source. The resultant reaction occurs at temperatures below 450 degrees C., thereby preventing degradation of electronic device and/or other devices/materials located in the substrate.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: July 7, 2009
    Assignee: Interuniversitair Microelektronica Centrum
    Inventors: Ann Witvrouw, Maria Gromova, Marc Schaekers, Serge Vanhaelemeersch, Brenda Eyckens
  • Patent number: 7557019
    Abstract: A plasma is produced in a treatment space (58) by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes (54,56) separated by a dielectric material (64), and a precursor material is introduced into the treatment space to coat a substrate film or web (14) by vapor deposition or atomized spraying at atmospheric pressure. The deposited precursor exposed to an electromagnetic field (AC, DC, or plasma) and then it is cured by electron-beam, infrared-light, visible-light, or ultraviolet-light radiation, as most appropriate for the particular material being deposited. Additional plasma post-treatment may be used to enhance the properties of the resulting coated products.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: July 7, 2009
    Assignee: Sigma Laboratories of Arizona, LLC
    Inventors: Michael G. Mikhael, Angelo Yializis, Richard E. Ellwanger
  • Patent number: 7521341
    Abstract: A method for forming a polysilicon film in a plasma-assisted chemical vapor deposition (CVD) system including a chamber in which a first electrode and a second electrode spaced apart from the first electrode are provided comprises providing a substrate on the second electrode, the substrate including a surface exposed to the first electrode, applying a first power to the first electrode for generating a plasma in the chamber, applying a second power to the second electrode during a nucleation stage of the polysilicon film for ion bombarding the surface of the substrate, and flowing an erosive gas into the chamber.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: April 21, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Liang-Tang Wang, Chi-Lin Chen, I-Hsuan Peng, Jung-Fang Chang, Chin-Jen Huang
  • Patent number: 7507644
    Abstract: A method of manufacturing a flash memory device, wherein according to one embodiment, when a high dielectric material is formed by a remote plasma atomic layer deposition method, first and second dielectric layers are formed by one process at the same time using silicate as the first dielectric layer and the high dielectric layer formed on the silicate as the second dielectric layer. Accordingly, cost can be saved since the process is shortened, a film quality better than that of the existing dielectric layer structure can be obtained, and a film with improved step coverage can be formed. Furthermore, capacitance and insulating breakdown voltage can be increased by using silicate having a high dielectric constant and a high dielectric layer.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: March 24, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Hyoung Koo
  • Patent number: 7501326
    Abstract: A method for forming an isolation layer of a semiconductor device using a shallow trench isolation method is provided. The method includes: vertically etching a region of an insulating layer and a part of a semiconductor substrate corresponding thereto to form a trench; depositing an oxide layer on an entire surface of the semiconductor substrate to fill the trench; plasma-sputtering at least a surface part of the oxide layer; and removing the oxide layer using chemical mechanical polishing (CMP) so that the oxide layer remains only in the trench. The method may remove sharp parts of the oxide layer and reduce or prevent the occurrence of scratches during the CMP process.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: March 10, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jong Taek Hwang
  • Publication number: 20090047760
    Abstract: Electric characteristics of a thin film transistor including a channel formation region including a microcrystalline semiconductor are improved. The thin film transistor includes a gate electrode, a gate insulating film formed over the gate electrode, a microcrystalline semiconductor layer formed over the gate insulating film, a semiconductor layer which is formed over the microcrystalline semiconductor layer and includes an amorphous semiconductor, and a source region and a drain region which are formed over the semiconductor layer. A channel is formed in the microcrystalline semiconductor layer when the thin film transistor is placed in an on state, and the microcrystalline semiconductor layer includes an impurity element for functioning as an acceptor. The microcrystalline semiconductor layer is formed by a plasma-enhanced chemical vapor deposition method.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 19, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Publication number: 20090047759
    Abstract: After a gate insulating film is formed over a gate electrode, in order to improve the quality of a microcrystalline semiconductor film which is formed in an early stage of deposition, a film near an interface with the gate insulating film is formed under a first deposition condition in which a deposition rate is low but the quality of a film to be formed is high, and then, a film is further deposited under a second deposition condition in which a deposition rate is high. Then, a buffer layer is formed to be in contact with the microcrystalline semiconductor film. Further, plasma treatment with a rare gas such as argon or hydrogen plasma treatment is performed before formation of the film under the first deposition condition for removing adsorbed water on a substrate.
    Type: Application
    Filed: August 1, 2008
    Publication date: February 19, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
  • Patent number: 7462568
    Abstract: Disclosed herein is a method for forming an interlayer dielectric film in a semiconductor device. The method comprises the steps of preparing a semiconductor substrate having a dielectric film and conductive film patterns sequentially deposited thereon, and depositing a high plasma oxide film as the interlayer dielectric film on the conductive film patterns and the dielectric films by supplying H2 as an adding gas together with a source gas. A dangling bond in an interface of the semiconductor substrate is reduced by adding hydrogen into the dielectric film, thereby enhancing the uniformity of the deposition. Moreover, hydrogen in the dielectric film decreases current leakage occurring in the gate by preventing electrons in the plasma from flowing into a gate through the bit-line, thereby enhancing the refresh characteristics of the semiconductor device.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: December 9, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jie Won Chung
  • Publication number: 20080299747
    Abstract: A method includes introducing a silicon-containing source gas and a dilution gas to a reactor to deposit an amorphous silicon film on a substrate by plasma CVD; and adjusting a compressive film stress to 300 MPa or less and a uniformity of film thickness within the substrate surface to ±5% or less of the amorphous silicon film depositing on the substrate as a function of a flow rate of the source gas, a flow rate of the dilution gas, and a pressure of the reactor which are used as control parameters.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 4, 2008
    Applicant: ASM JAPAN K.K.
    Inventors: Hirofumi ARAI, Takashige WATANABE
  • Patent number: 7442627
    Abstract: A transparent conductive layer forming method is disclosed which comprises the steps of introducing a reactive gas to a discharge space, exciting the reactive gas in a plasma state by discharge at atmospheric pressure or at approximately atmospheric pressure, and exposing a substrate to the reactive gas in a plasma state to form a transparent conductive layer on the substrate, wherein the reactive gas comprises a reducing gas.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: October 28, 2008
    Assignee: Konica Corporation
    Inventors: Toshio Tsuji, Hiroto Itoh, Takakazu Kiyomura
  • Patent number: 7442628
    Abstract: A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a conductive film, which absorbs laser light, from attaching to the cleavage plane. During the plasma cleaning, a first process gas containing argon gas and nitrogen gas is introduced into a vacuumed ECR sputtering apparatus. After the cleavage plane is exposed to the first process gas in the plasma state for a certain time period without application of a voltage, a second process gas containing argon gas and oxygen gas is introduced, and the cleavage plane is exposed to the second process gas in the plasma state while a voltage is applied to the silicon target.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: October 28, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Yamane, Tetsuo Ueda, Isao Kidoguchi, Toshiya Kawata
  • Patent number: 7439191
    Abstract: A method of silicon layer deposition using a cyclical deposition process. The cyclical deposition process comprises alternately adsorbing a silicon-containing precursor and a reducing gas on a substrate structure. Thin film transistors, such as for example a bottom-gate transistor or a top-gate transistor, including one or more silicon layers may, be formed using such cyclical deposition techniques.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: October 21, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Kam Law, Quanyuan Shang, William Reid Harshbarger, Dan Maydan
  • Publication number: 20080230781
    Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.
    Type: Application
    Filed: May 19, 2008
    Publication date: September 25, 2008
    Inventors: Yoichiro Numasawa, Yukinobu Murao
  • Patent number: 7419887
    Abstract: An apparatus and method is disclosed for forming a nano structure on a substrate with nano particles. The nano particles are deposited through a nano size pore onto the substrate. A laser beam is directed through a concentrator to focus a nano size laser beam onto the deposited nano particles on the substrate. The apparatus and method is suitable for fabricating patterned conductors, semiconductors and insulators on semiconductor wafers of a nano scale line width by direct nanoscale deposition of materials.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: September 2, 2008
    Inventors: Nathaniel R. Quick, Aravinda Kar
  • Patent number: 7393723
    Abstract: A method of manufacturing a semiconductor device that forms laminate layers includes the steps of reducing contamination containing the single bond of carbon on at least one part of a surface on which the laminate films are formed by activated hydrogen before the laminate films are formed, and forming the laminate films on the surface on which the laminate films are formed.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: July 1, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsunori Sakama, Takeshi Fukada
  • Patent number: 7384828
    Abstract: A semiconductor film having a crystalline structure is formed by using a metal element that assists the crystallization of the semiconductor film, and the metal element remaining in the film is effectively removed to decrease the dispersion among the elements. The semiconductor film or, typically, an amorphous silicon film having an amorphous structure is obtained based on the plasma CVD method as a step of forming a gettering site, by using a monosilane, a rare gas element and hydrogen as starting gases, the film containing the rare gas element at a high concentration or, concretely, at a concentration of 1×1020/cm3 to 1×1021/cm3 and containing fluorine at a concentration of 1×1015/cm3 to 1×1017/cm3.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: June 10, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Noriyoshi Suzuki, Hideto Ohnuma, Masato Yonezawa
  • Patent number: 7368367
    Abstract: A preparing method of a semiconductor, particularly a preparing method of a polycrystal semiconductor film which has a good electrical property is disclosed. In order to obtain a non-crystalline silicon film containing a lot of combination of hydrogen and silicon, a forming process of a non-crystalline silicon film by a low temperature gas phase chemical reaction, a process of a heat annealing to produce a lot of dangling bonds of silicon, so as to draw out hydrogen from said non-crystalline silicon film, and a process of applying a laser irradiation to said non-crystal silicon film having a lot of dangling bond of silicon are conducted.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: May 6, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoto Kusumoto
  • Patent number: 7368317
    Abstract: The invention relates to a method of producing an n-type diamond. The inventive method comprises an n-doping stage during which a donor species is vacuum diffused in a diamond that was initially doped with an acceptor, in order to form donor groups containing the donor species, at a temperature that is less than or equal to the dissociation temperature of the complexes formed between the acceptor and the donor species.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: May 6, 2008
    Assignees: Centre National de la Recherche Scientifique-CNRS, Universite de Versailles St-Quentin En Yvelines
    Inventors: Jacques Paul Marie Chevallier, Zephirin Symplice Teukam, Dominique Ballutaud
  • Publication number: 20070287272
    Abstract: Epitaxial layers are selectively formed in semiconductor windows by a cyclical process of repeated blanket deposition and selective etching. The blanket deposition phases leave non-epitaxial material over insulating regions, such as field oxide, and the selective etch phases preferentially remove non-epitaxial material while deposited epitaxial material builds up cycle-by-cycle. Quality of the epitaxial material improves relative to selective processes where no deposition occurs on insulators. Use of a germanium catalyst during the etch phases of the process aid etch rates and facilitate economical maintenance of isothermal and/or isobaric conditions throughout the cycles. Throughput and quality are improved by use of trisilane, formation of amorphous material over the insulating regions and minimizing the thickness ratio of amorphous:epitaxial material in each deposition phase.
    Type: Application
    Filed: September 28, 2006
    Publication date: December 13, 2007
    Applicant: ASM AMERICA, INC.
    Inventors: Matthias Bauer, Keith Doran Weeks
  • Publication number: 20070281449
    Abstract: The substrate transportation apparatus 10 comprises a plurality of transportation rollers 22A-22D disposed at a predetermined spacing for transporting the substrate 40 in response to rotation of the transportation rollers 22. Each of the transportation rollers 22 is generally hollow cylindrical member formed with a plurality of slit nozzles 24 in the circumference. Alternating rows of the transportation rollers 22 are designed to blow and suck air to and from the bottom surface of the substrate 40 under transportation while preventing dust or any other foreign materials from collecting on the bottom surface of the substrate 40.
    Type: Application
    Filed: May 10, 2007
    Publication date: December 6, 2007
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventor: Kazuya Nagatomo
  • Patent number: 7279398
    Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: October 9, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Trung T. Doan, Ronald A. Weimer, Kevin L. Beaman, Lyle D. Breiner, Lingyi A. Zheng, Er-Xuan Ping, Demetrius Sarigiannis, David J. Kubista
  • Patent number: 7253086
    Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Lindsey Hall
  • Patent number: 7214600
    Abstract: A method for depositing a carbon-containing material layer onto a substrate includes delivering a mixture of precursors for the carbon-containing material layer into a process chamber, doping the carbon-containing material layer with silicon, and depositing the carbon-containing material layer at low temperature. In one aspect, improved light transmittance of the carbon-containing material layer at all wavelengths of a visible light spectrum is obtained. In addition, a method for depositing an encapsulating layer is provided for various display applications which require low temperature deposition process due to thermal instability of underlying materials used. The encapsulating layer may include one or more barrier layer material layers and one or more amorphous carbon material layers. The amorphous carbon material can be used to reduce thermal stress and prevent the deposited thin film from peeling off the substrate.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: May 8, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Tae Kyung Won, Sanjay Yadav
  • Patent number: 7199027
    Abstract: There is provided a technique for effectively removing a metallic element for promoting crystallization in a semiconductor film with a crystalline structure after the semiconductor film is obtained using the metallic element, to reduce a variation between elements. In a step of forming a gettering site, a plasma CVD method is used and a film formation is conducted using raw gas including monosilane, noble gas, and nitrogen to obtain a semiconductor film which includes the noble gas element at a high concentration, specifically, a concentration of 1×1020/cm3 to 1×1021/cm3 and has an amorphous structure, typically, an amorphous silicon film.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: April 3, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Taketomi Asami, Noriyoshi Suzuki, Shunpei Yamazaki
  • Patent number: 7192851
    Abstract: A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a conductive film, which absorbs laser light, from attaching to the cleavage plane. During the plasma cleaning, a first process gas containing argon gas and nitrogen gas is introduced into a vacuumed ECR sputtering apparatus. After the cleavage plane is exposed to the first process gas in the plasma state for a certain time period without application of a voltage, a second process gas containing argon gas and oxygen gas is introduced, and the cleavage plane is exposed to the second process gas in the plasma state while a voltage is applied to the silicon target.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: March 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Yamane, Tetsuo Ueda, Isao Kidoguchi, Toshiya Kawata
  • Patent number: 7172933
    Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Huang, Bow-Wen Chan, Baw-Ching Perng, Lawrence Sheu, Hun-Jan Tao, Chih-Hsin Ko, Chun-Chieh Lin
  • Patent number: 7056806
    Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: June 6, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Trung T. Doan, Ronald A. Weimer, Kevin L. Beaman, Lyle D. Breiner, Lingyi A. Zheng, Er-Xuan Ping, Demetrius Sarigiannis, David J. Kubista
  • Patent number: 7045445
    Abstract: Disclosed is a method for fabricating a semiconductor device by using a PECYCLE-CVD process. The method includes the steps of feeding source gas into a process chamber for predetermined time within one cycle, allowing reaction gas to flow in the process chamber at least until a plasma reaction is finished in the process chamber and feeding purge gas into the process chamber for a predetermined time within one cycle, thereby purging residual products remaining in the process chamber after source gas is reacted, forming plasma in the process chamber for a predetermined time within one cycle so as to allow reaction gas to react with plasma, thereby depositing a thin film on a wafer, and feeding purge gas into the process chamber for a predetermined time within one cycle, thereby purging residual products remaining in the process chamber after reaction gas is reacted. Superior step-coverage and uniformity of the thin film are achieved while depositing the thin film at a higher speed.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 16, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young Gi Kim, Sang Ho Woo, Seung Won Choi