Deposition Utilizing Plasma (e.g., Glow Discharge, Etc.) Patents (Class 438/485)
  • Patent number: 6531654
    Abstract: In a semiconductor thin-film formation process comprising feeding a semiconductor thin-film material gas into a discharge space, and applying a high-frequency power thereto to cause plasma to take place and decompose the material gas to form an amorphous semiconductor thin film on a desired substrate, the high-frequency power is applied changing its power density continuously or stepwise from a high power density to a low power density and thereafter again changing the power density continuously or stepwise from a low power density to a high power density, to form a semiconductor thin film made different in film quality in the direction of layer thickness while retaining the same conductivity type. This process enable formation of high-quality semiconductor thin films by plasma CVD.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: March 11, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shuichiro Sugiyama, Masahiro Kanai, Takahiro Yajima
  • Publication number: 20030022468
    Abstract: The present invention relates to a manufacturing method of a semiconductor device in which a barrier insulating film and a main insulating film having low relative dielectric constant are sequentially formed while a wiring mainly consisting of copper film is coated.
    Type: Application
    Filed: June 10, 2002
    Publication date: January 30, 2003
    Inventors: Yoshimi Shioya, Yuhko Nishimoto, Tomomi Suzuki, Hiroshi Ikakura, Kazuo Maeda
  • Patent number: 6503816
    Abstract: A thin film forming method and apparatus forms a thin film having an excellent thickness uniformity over a substrate, particularly a large-area substrate. The thin film forming method and apparatus includes a film forming chamber in which an inductive coupling electrode having a feeding portion and a grounding portion at its two ends is arranged, a high-frequency power source for feeding a high-frequency power to the feeding portion, and a waveform generator for amplitude-modulating the high-frequency power outputted from the high-frequency power source. The amplitude-modulated high-frequency power is fed to the inductive coupling electrode to generate a plasma so that a thin film may be formed on a substrate arranged to face the inductive coupling electrode.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: January 7, 2003
    Assignees: National Institute of Advanced Industrial Science and Technology, Anelva Corporation
    Inventors: Norikazu Ito, Yoshimi Watabe, Akihisa Matsuda, Michio Kondo
  • Publication number: 20030003696
    Abstract: Generally, a substrate processing apparatus is provided. In one aspect of the invention, a substrate processing apparatus is provided. In one embodiment, the substrate processing apparatus includes one or more chamber bodies coupled to a gas distribution system. The chamber bodies define at least a first processing region and a second processing region within the chamber bodies. The gas distribution system includes a first, a second and a third gas supply circuit. The first gas supply circuit is teed between the first and second processing regions and is adapted to supply a first processing gas thereto. The second gas supply circuit is coupled to the first processing region and adapted to supply a second process gas thereto. The third gas supply circuit is coupled to the second processing region and is adapted to supply a third process gas thereto. Alternatively, the processing regions may be disposed in a single chamber body.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Avgerinos Gelatos, Joel M. Huston, Lawrence Chung-Lai Lei, Vicky Uyen Nguyen, Yin Lin, Fong Chang
  • Publication number: 20020182828
    Abstract: A semiconductor film having a crystalline structure is formed by using a metal element that assists the crystallization of the semiconductor film, and the metal element remaining in the film is effectively removed to decrease the dispersion among the elements. The semiconductor film or, typically, an amorphous silicon film having an amorphous structure is obtained based on the plasma CVD method as a step of forming a gettering site, by using a monosilane, a rare gas element and hydrogen as starting gases, the film containing the rare gas element at a high concentration or, concretely, at a concentration of 1×1020/cm3 to 1×1021/cm3 and containing fluorine at a concentration of 1×1015/cm3 to 1×1017/cm3.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 5, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Noriyoshi Suzuki, Hideto Ohnuma, Masato Yonezawa
  • Patent number: 6488995
    Abstract: Disclosed herein is a method of forming a microcrystalline silicon film by using a raw gas containing at least a silicon compound by a high-frequency plasma CVD method, wherein the formation of the film is conducted in such a manner that the residence time, &tgr; (ms) of the raw gas in a film deposition chamber, which is defined as &tgr; (ms)=78.9×V×P/M, in which V is a volume (cm3) of the deposition chamber, P is a deposition pressure (Torr), and M is a total flow rate (sccm) of the raw gas, satisfies &tgr;<40. The method permits the formation of a good-quality microcrystalline silicon film at low cost.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: December 3, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomonori Nishimoto, Masafumi Sano
  • Patent number: 6486045
    Abstract: In order to make possible formation of a deposited film of a relatively large area at a treatment rate which could not accomplished by the plasma process of the prior art, and in order to make possible stable production of the deposited film without variation in film quality, in an apparatus and a method for forming a deposited film, a part of a reaction vessel is formed of a dielectric member, at least one high-frequency electrode is arranged so as to face at least one substrate with interposition of the dielectric member, an earth shield is arranged so as to cover the reaction vessel and the high-frequency electrode, plasma is generated between the high-frequency electrode and the substrate, and a deposited film is formed under the conditions in which the following equation: 0.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: November 26, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Otsuka, Tatsuyuki Aoike, Toshiyasu Shirasuna, Kazuyoshi Akiyama, Hitoshi Murayama, Daisuke Tazawa, Kazuto Hosoi
  • Publication number: 20020173124
    Abstract: A method of forming a multi-layered thin film uses photolysis chemical vapor deposition (PCVD). In the method, a substrate for a process of forming the multi-layered thin film is prepared. At least two source gases are supplied to the substrate. Reaction lights having particular wavelengths are prepared, which are absorbed by each of the source gases, are prepared. The reaction lights having particular wavelengths are alternatingly emitted on the substrate to a form a predetermined multi-layered thin film. A photolysis chemical vapor deposition (PCVD) reactor is disclosed, having a chamber with a substrate support, a gas supply system for supplying a plurality of source gases to the substrate in the chamber, and a light supply system mounted at one side of the chamber. The light supply system selectively emits one of the plurality of reaction lights having different wavelengths on the substrate.
    Type: Application
    Filed: May 16, 2002
    Publication date: November 21, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hyun Joo
  • Patent number: 6482754
    Abstract: A method of forming a carbon doped oxide layer on a substrate is described. That method comprises introducing into a chemical vapor deposition apparatus a precursor gas that is selected from those having the formula (CH3)xSi(OCH3)4−x. Simultaneously, a background gas, oxygen and nitrogen are introduced into the chemical vapor deposition apparatus. That apparatus is then operated under conditions that cause a carbon doped oxide layer to form on the substrate.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: November 19, 2002
    Assignee: Intel Corporation
    Inventors: Ebrahim Andideh, Kevin L. Peterson
  • Publication number: 20020168794
    Abstract: For efficiently forming a semiconductor element with excellent adhesion and environment resistance, a semiconductor element forming method is configured to have a step of forming a plurality of pin junctions of a silicon-based material on a substrate by a high-frequency plasma CVD process under a pressure of not more than atmospheric pressure, and the method further has a step of forming a p-layer, an i-layer, and a portion of an n-layer of a first pin junction of the pin junctions or forming an n-layer, an i-layer, and a portion of a p-layer of a first pin junction of the pin junctions, and thereafter exposing the p-layer or the n-layer exposed in the surface, to an oxygen-containing atmosphere; a step of forming on the p-layer or the n-layer as exposed to the oxygen-containing atmosphere a layer of the same conductivity type as that of the p-layer or the n-layer; and a step of forming an n-layer or a p-layer of a second pin junction adjacent to the first pin junction to form a pn interface.
    Type: Application
    Filed: January 30, 2002
    Publication date: November 14, 2002
    Inventors: Takaharu Kondo, Masafumi Sano, Akira Sakai, Koichi Matsuda, Yuzo Koda, Tadashi Hori
  • Publication number: 20020162736
    Abstract: Low resistant vias are formed by sequentially treating an opening in an interlayer dielectric and the exposed surface of a lower metal feature with an NH3 plasma followed by a N2/H2 plasma, thereby removing any oxide on the metal surface and removing residual polymers or polymeric deposits generated during etching to form the opening. Embodiments include forming a dual damascene opening in a low-k interlayer dielectric exposing the upper surface of a lower Cu or Cu alloy feature, sequentially treating the opening and the upper surface of the lower metal feature with an NH3 plasma and then with a N2/H2 plasma, Ar sputter etching, depositing a barrier layer lining the opening, depositing a seedlayer and filling the opening with Cu or a Cu alloy.
    Type: Application
    Filed: May 2, 2001
    Publication date: November 7, 2002
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Robert A. Huertas, Dawn Hopper
  • Patent number: 6472296
    Abstract: A process for producing a semiconductor layer by introducing a raw gas into a discharge chamber and supplying high-frequency power to the chamber to decompose the raw gas by discharge, thereby forming a semiconductor layer on a substrate within the discharge chamber, the process comprising the steps of supplying high-frequency power of at least very high frequency (VHF) as the high-frequency power; supplying bias power of direct current power and/or high-frequency power of radio-frequency (RF) together with the high-frequency power of VHF to the discharge chamber; and controlling a direct current component of an electric current flowing into an electrode, to which the bias power is supplied, so as to fall within a range of from 0.1 A/m2 to 10 A/m2 in terms of a current density based on the area of an inner wall of the discharge chamber. A good-quality semiconductor layer can be deposited over a large area at a high speed.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: October 29, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasushi Fujioka, Shotaro Okabe, Masahiro Kanai, Akira Sakai, Tadashi Sawayama, Yuzo Koda, Takahiro Yajima
  • Patent number: 6472297
    Abstract: There is suggested a method for forming a good-quality polysilicon layer having a large area through a low temperature process even if laser annealing is not conducted. An object of the present invention is therefore to provide a poly-Si TFT array substrate exhibiting little display unevenness and having a high exactitude even if it has a large screen. This object can be attained by a method for producing a TFT array substrate for a liquid crystal display device, comprising a process of forming, on a substrate, a poly-Si TFT in which a polysilicon semiconductor layer is used in a channel area, comprising a polysilicon layer forming step of depositing silicon particles excited by adding energy beforehand onto the substrate so that the polysilicon layer is formed at the stage when the silicon particles are deposited on the substrate.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: October 29, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazufumi Ogawa, Kazuyasu Adachi
  • Patent number: 6468885
    Abstract: A method of fabricating device quality, thin-film a-Si:H for use as semiconductor material in photovoltaic and other devices, comprising in any order; positioning a substrate in a vacuum chamber adjacent a plurality of heatable filaments with a spacing distance L between the substrate and the filaments; heating the filaments to a temperature that is high enough to obtain complete decomposition of silicohydride molecules that impinge said filaments into Si and H atomic species; providing a flow of silicohydride gas, or a mixture of silicohydride gas containing Si and H, in said vacuum chamber while maintaining a pressure P of said gas in said chamber, which, in combination with said spacing distance L, provides a P×L product in a range of 10-300 mT-cm to ensure that most of the Si atomic species react with silicohydride molecules in the gas before reaching the substrate, to thereby grow a a-Si:H film at a rate of at least 50 Å/sec.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: October 22, 2002
    Assignee: Midwest Research Institute
    Inventors: Archie Harvin Mahan, Edith C. Molenbroek, Alan C. Gallagher, Brent P. Nelson, Eugene Iwaniczko, Yueqin Xu
  • Patent number: 6448158
    Abstract: A method of patterning an indium tin oxide (ITO) layer is performed on a glass substrate. First, using sputtering, an amorphous ITO layer is deposited on the glass substrate. Then, using excimer laser annealing (ELA), the amorphous ITO layer within a predetermined pattern is turned into a crystalline ITO layer. Finally, using an etch solution, the amorphous ITO layer outside the predetermine pattern is removed.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: September 10, 2002
    Assignee: Hannstar Display Corp.
    Inventors: Chih-Yu Peng, In-Cha Hsieh
  • Patent number: 6440756
    Abstract: A method and apparatus for reducing plasma-induced charging damage in a semiconducting device are provided. The method includes exposing an article having a dielectric material susceptible to plasma-induced charging, to vacuum-ultraviolet (VUV) radiation of an energy greater than the bandgap energy of the dielectric material during or after plasma processing of the device. The plasma-induced charge is conducted from, or recombined at, the charging site.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: August 27, 2002
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: J. Leon Shohet, Cristian Cismaru, Francesco Cerrina
  • Patent number: 6429097
    Abstract: A method of physical vapor deposition includes selecting a target material; mixing at least two gases to form a sputtering gas mixture, wherein a first sputtering gas is helium and a second sputtering gas is taken from the gases consisting of neon, argon krypton, xenon and radon; forming a plasma in the sputtering gas mixture atmosphere to sputter atoms from the target material to the substrate thereby forming a layer of target material on the substrate and annealing the substrate and the deposited layer thereon. An improved physical vapor deposition vacuum chamber includes a target held in a target holder, a substrate held in a substrate holder, a plasma arc generator, and heating rods. A sputtering gas feed system is provided for introducing a mixture of sputtering gases into the chamber; as is a vacuum mechanism comprising at least one turbomolecular pump for evacuating the chamber to a pressure of less than 16 mTorr during deposition.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: August 6, 2002
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Apostolos Voutsas, Yukihiko Nakata
  • Publication number: 20020102847
    Abstract: TBHy is demonstrated as an efficient and a less carbon-containing N precursor for the growth of high-quality InGaAsN by MOCVD at lower growth temperatures. The photovoltaic characteristics of 1.20 eV InGaAsN solar cells, such as open-circuit voltage, short-circuit current, fill factor and efficiency are improved significantly by using TBHy compared to using DMHy. This demonstration can also be applied to other InGaAsN-based optoelectronic and electronic devices. Therefore, this invention is extremely important to expedite the demonstration of next-generation prototype products such as 1.3 &mgr;m-InGaAsN-epitaxial VCSELs for high-speed optical communications, low-power Npn InGaP/InGaAsN/GaAs HBTs and InGaP/AlGaAs/InGaAsN HEMTs for wireless applications, and high-efficiency multiple-junction InGaP/GaAs/InGaAsN/Ge solar cells for space power systems.
    Type: Application
    Filed: September 17, 2001
    Publication date: August 1, 2002
    Inventors: Paul R. Sharps, Hong Qi Hou, Nein-Yi Li, Ravi Kanjolia
  • Patent number: 6417079
    Abstract: A discharge electrode improves the uniformity of discharge such as plasma. The electrical discharge electrode, which receives high-frequency power and produces a discharge, comprises an electrode body adapted to receive high-frequency power, and a member for preventing the reflection of high-frequency power from the electrode body. The electrical discharge may comprise plasma generated by an electrical discharge.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: July 9, 2002
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Hideo Yamakoshi, Koji Satake, Minoru Danno
  • Patent number: 6410454
    Abstract: In a semiconductor wafer-processing, hydrogen gas is introduced into the same chamber as used for film formation and heated to generate hydrogen radicals. Alternatively, a plasma is applied to generate hydrogen radicals, or the semiconductor wafer is heated immediately before film formation. Thereby, contaminants on the surface of the wafer are removed. Thereafter, a conductive film or an insulating film is formed on the wafer in the same chamber.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: June 25, 2002
    Assignee: Mitsubishi Denki Kabushiki
    Inventors: Seiji Muranaka, Cozy Ban, Akihiko Osaki
  • Patent number: 6410408
    Abstract: It is an object of the present invention, when forming a high-density plasma CVD film, to suppress the production of particles, which are the cause of unsatisfactory formation of a micropattern, without causing a drop in productivity, and thus improve the yield of a semiconductor device. For this purpose, a CVD film is formed on a predetermined plurality of semiconductor substrates by repeating, in order, a process #101a in which a plasma CVD film is formed on a semiconductor substrate, and a process #101b in which low-pressure cleaning of the inside of a reaction chamber is performed by way of exhaustion to a first exhaust line on which a turbo pump employed in #101a is placed. In this manner, reactant, which has adhered to the first exhaust line, can be removed during the low-pressure cleaning.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: June 25, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hisashi Yano
  • Patent number: 6403497
    Abstract: A polycrystalline or polysilicon film having large grain size, such as 1 &mgr;m to 2 &mgr;m in diameter or greater, is obtained over the methods of the prior art by initially forming a silicon film, which may be comprised of amorphous silicon or micro-crystalline silicon or contains micro-crystal regions in the amorphous phase, at a low temperature via a chemical vapor deposition (CVD) method, such as by plasma chemical vapor deposition (PCVD) with silane gas diluted with, for example, hydrogen, argon or helium at a temperature, for example, in the range of room temperature to 600° C. This is followed by solid phase recrystallization of the film to form a polycrystalline film which is conducted at a relatively low temperature in the range of about 550° C. to 650° C. in an inert atmosphere, e.g., N or Ar, for a period of about several hours to 40 or more hours wherein the temperature is gradually increased, e.g., at a temperature rise rate below 20° C./min, preferably about 5° C.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: June 11, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Hideaki Oka, Satoshi Takenaka, Masafumi Kunii
  • Patent number: 6383898
    Abstract: A photoelectric conversion device including a plurality of pin junction layers, wherein at least a p-layer adjacent to an n-layer is formed of a stack of an amorphous silicon layer as a first p-layer and an amorphous silicon layer as a second p-layer, the first p-layer having a thickness of 5 nm or less and containing a p-type impurity and an n-type impurity, and the second p-layer having a p-type impurity concentration gradually decreasing as it is closer to an i-layer.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: May 7, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsushi Kishimoto
  • Publication number: 20020048909
    Abstract: Disclosed herein is a process for vapor phase growth of gallium nitride compound semiconductor which yields uniform crystal layers with good reproducibility. The process comprises forming a first nitride semiconductor layer on a substrate, forming thereon a protective film for crystal growth prevention in such a way that it has partly open window regions through which the first nitride semiconductor layer is exposed, forming a second nitride semiconductor layer by selective growth from the first nitride semiconductor layer at a crystal growth starting temperature, and continuing crystal growth at a temperature higher than the crystal growth starting temperature. The vapor phase growth at a low temperature yields a uniform crystal layer, and the ensuing vapor phase growth at a raised temperature yields a uniform crystal layer with good reproducibility in conformity with the first crystal layer.
    Type: Application
    Filed: July 31, 2001
    Publication date: April 25, 2002
    Inventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
  • Publication number: 20020042192
    Abstract: A shower head 10 is disposed inside the process chamber 2 of a plasma CVD apparatus 1. The shower head 10 has a plurality of gas introduction holes 11, and a process gas is supplied via these gas introduction holes 11 to a wafer W which is disposed on a pedestal 5. A rough surface portion B that has been subjected to a bead blasting treatment is formed over the entire surface of the shower head 10 that faces the pedestal 5. As a result, the area of the surface of the shower head 10 that faces the pedestal 5 is increased, so that a uniform high-density plasma is generated inside the process chamber 2.
    Type: Application
    Filed: October 9, 2001
    Publication date: April 11, 2002
    Applicant: Applied Materials. Inc.
    Inventors: Keiichi Tanaka, Yasunori Yokoyama, Takashi Suzuki, Terukazu Aitani
  • Publication number: 20020039832
    Abstract: In a discharge space, a substrate 201 and a cathode 206 are disposed a distance d (cm) apart from each other, and gas containing one or more silicon compounds and hydrogen are introduced into the discharge space, and a product Pd of a film forming pressure P (Pa) and d, and a hydrogen flow rate M (SLM) are set so as to meet a relation:
    Type: Application
    Filed: July 9, 2001
    Publication date: April 4, 2002
    Inventors: Takahiro Yajima, Masahiro Kanai, Shuichiro Sugiyama
  • Publication number: 20020037635
    Abstract: Method and apparatus for depositing an amorphous silicon film on a substrate using a high density plasma chemical vapor deposition (HDP-CVD) technique is provided. The method generally comprises positioning a substrate in a processing chamber, introducing an inert gas into the processing chamber, introducing a silicon source gas into the processing chamber generating a high density plasma, and depositing the amorphous silicon film. The amorphous silicon film is deposited at a substrate temperature 500° C. or less. The amorphous silicon film may then be annealed to improve film properties.
    Type: Application
    Filed: June 26, 2001
    Publication date: March 28, 2002
    Inventors: Zhuang Li, Kent Rossman, Tzuyuan Yiin
  • Patent number: 6352910
    Abstract: Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: March 5, 2002
    Assignee: Applied Komatsu Technology, Inc.
    Inventors: William R. Harshbarger, Takako Takehara, Jeff C. Olsen, Regina Qiu, Yvonne LeGrice, Guofu J. Feng, Robert M. Robertson, Kam Law
  • Publication number: 20020022349
    Abstract: In a semiconductor thin-film formation process comprising feeding a semiconductor thin-film material gas into a discharge space, and applying a high-frequency power thereto to cause plasma to take place and decompose the material gas to form an amorphous semiconductor thin film on a desired substrate, the high-frequency power is applied changing its power density continuously or stepwise from a high power density to a low power density and thereafter again changing the power density continuously or stepwise from a low power density to a high power density, to form a semiconductor thin film made different in film quality in the direction of layer thickness while retaining the same conductivity type This process enables formation of high-quality semiconductor thin films by plasma CVD.
    Type: Application
    Filed: May 22, 2001
    Publication date: February 21, 2002
    Inventors: Shuichiro Sugiyama, Masahiro Kanai, Takahiro Yajima
  • Publication number: 20020001924
    Abstract: The invention provides a process for producing a semiconductor layer by introducing a raw gas into a discharge chamber and supplying high-frequency power to the chamber to decompose the raw gas by discharge, thereby forming a semiconductor layer on a substrate within the discharge chamber, the process comprising the steps of supplying high-frequency power of at least very high frequency (VHF) as the high-frequency power; supplying bias power of direct current power and/or high-frequency power of radio-frequency (RF) together with the high-frequency power of VHF to the discharge chamber; and controlling a direct current component of an electric current flowing into an electrode, to which the bias power is supplied, so as to fall within a range of from 0.1 A/m2 to 10 A/m2 in terms of a current density based on the area of an inner wall of the discharge chamber. A good-quality semiconductor layer can be deposited over a large area at a high speed.
    Type: Application
    Filed: July 26, 2001
    Publication date: January 3, 2002
    Inventors: Yasushi Fujioka, Shotaro Okabe, Masahiro Kanai, Akira Sakai, Tadashi Sawayama, Yuzo Koda, Takahiro Yajima
  • Patent number: 6329270
    Abstract: A method is provided of fabricating a thin film transistor semiconductor film of polycrystalline silicon on a transparent substrate suitable for the manufacture of a liquid crystal display. The deposition of silicon film at very low rates provides conditions for the optimum formation of microcrystallites. As the amorphous silicon is annealed, crystal grains, begun from the seed crystals, are formed in the resulting polycrystalline silicon. The seed crystals help regulate the annealment process, and reduce process dependence on precision deposition and heating methods. This microcrystalline film results in a polycrystalline film having larger crystal grains, and crystal grains of a relatively uniform size. The invention relies on a quantifiable relationship between the pre-melt crystalline fraction and crystallite density, post-melt crystalline fraction and crystallite density, and the ELA density during annealing.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: December 11, 2001
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Tolis Voutsas
  • Publication number: 20010041375
    Abstract: A method and apparatus for reducing plasma-induced charging damage in a semiconducting device are provided. The method includes exposing an article having a dielectric material susceptible to plasma-induced charging, to vacuum-ultraviolet (VUV) radiation of an energy greater than the bandgap energy of the dielectric material during or after plasma processing of the device. The plasma-induced charge is conducted from, or recombined at, the charging site.
    Type: Application
    Filed: December 13, 2000
    Publication date: November 15, 2001
    Inventors: J. Leon Shohet, Cristian Cismaru, Francesco Cerrina
  • Publication number: 20010041463
    Abstract: A method to deposit insulating, semiconducting, and conducting films at pressures close to the atmospheric pressure and at temperatures less than 500° C. is provided. In this method, noble gas is mixed with reactant gas, and electric energy is applied to produce plasma at pressure substantially close to atmospheric pressure. The process can be applied to deposit films such as silicon dioxide, silicon nitride, silicon, and metal films.
    Type: Application
    Filed: February 8, 2001
    Publication date: November 15, 2001
    Inventor: Ramesh H. Kakkad
  • Patent number: 6309906
    Abstract: The device (10) comprises a deposition chamber (12) containing two electrodes (13, 14), one of which comprises a support (16) for a substrate (17) and is earthed, the other being connected to an electric radio frequency generator (15). The device includes a mechanism (23) for extracting gas from the chamber (12) and a mechanism (18) for supplying gas. The device also comprises a mechanism for purification (31) of the gases introduced into the chamber, these a mechanism being arranged so as to reduce the number of oxygen atoms contained in the deposition gas, such gas being made up of silane, hydrogen and/or argon. The procedure consists of creating a vacuum in the deposition chamber (12), purifying the gases using purification a mechanism (31), introducing these purified gases into the chamber (12), then creating a plasma between the electrodes (13, 14). A film of intrinsic microcrystalline silicon in then deposited on the substrate.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: October 30, 2001
    Assignee: Universite de Neuchatel-Institut de Microtechnique
    Inventors: Johann Meier, Ulrich Kroll
  • Publication number: 20010031543
    Abstract: A process of producing a thin film is disclosed which comprises the steps of:
    Type: Application
    Filed: March 13, 2001
    Publication date: October 18, 2001
    Inventors: Kenji Ando, Minoru Otani, Yasuyuki Suzuki, Toshiaki Shingu, Ryuji Biro, Hidehiro Kanazawa
  • Publication number: 20010023971
    Abstract: A film, typically a silicon-based film, is formed on a substrate by means of a plasma CVD process using a high frequency wave in a condition where a resistance element made of a different material than that of the substrate is provided on the electric path between the substrate and the earth. The resultant film shows a high quality and an improved adhesion strength while it can be formed at a practically high rate.
    Type: Application
    Filed: February 27, 2001
    Publication date: September 27, 2001
    Inventors: Takaharu Kondo, Masafumi Sano, Koichi Matsuda, Makoto Higashikawa
  • Patent number: 6287943
    Abstract: The invention provides a process for producing a semiconductor layer by introducing a raw gas into a discharge chamber and supplying high-frequency power to the chamber to decompose the raw gas by discharge, thereby forming a semiconductor layer on a substrate within the discharge chamber, the process comprising the steps of supplying high-frequency power of at least very high frequency (VHF) as the high-frequency power; supplying bias power of direct current power and/or high-frequency power of radio-frequency (RF) together with the high-frequency power of VHF to the discharge chamber; and controlling a direct current component of an electric current flowing into an electrode, to which the bias power is supplied, so as to fall within a range of from 0.1 A/m2 to 10 A/m2 in terms of a current density based on the area of an inner wall of the discharge chamber. A good-quality semiconductor layer can be deposited over a large area at a high speed.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: September 11, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasushi Fujioka, Shotaro Okabe, Masahiro Kanai, Akira Sakai, Tadashi Sawayama, Yuzo Koda, Takahiro Yajima
  • Patent number: 6281147
    Abstract: In a process of forming a silicon oxide film 116 that constitutes an interlayer insulating film with TEOS as a raw material through the plasma CVD method, the RF output is oscillated at 50 W, and the RF output is gradually increased from 50 W to 250 W (an output value at the time of forming a film) after discharging (after the generation of O2-plasma). A TEOS gas is supplied to start the film formation simultaneously when the RF output becomes 250 W, or while the timing is shifted. As a result, because the RF power supply is oscillated at a low output when starting discharging, a voltage between the RF electrodes can be prevented from changing transitionally and largely.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: August 28, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsunori Sakama, Masaaki Hiroki
  • Patent number: 6277696
    Abstract: The present invention provides a vertical cavity surface emitting laser having high gain and high reflectivity in the desired wavelength range and good thermal and electrical conductivity. The laser structure is comprised of a first mirror region, a second mirror region, and an active region positioned between the first and second mirror regions. Unlike, prior VCSELs, the active region is fused to both the first mirror region and the second mirror region. This allows the laser designer to optimize laser performance for the desired wavelength range by allowing the choice of different materials for the first mirror region, the second mirror region, and the active region.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: August 21, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Kent W. Carey, Long Yang, John E. Bowers, Dubravko I. Babic, James J. Dudley
  • Patent number: 6274900
    Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewall bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: August 14, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Kemal Tamer San, Wei William Lee, Cetin Kaya
  • Patent number: 6274461
    Abstract: Plasma deposition of substantially amorphous semiconductor materials is carried out under a set of deposition parameters which are selected so that the process operates near the amorphous/microcrystalline threshold. This threshold varies as a function of the thickness of the depositing semiconductor layer; and, deposition parameters, such as diluent gas concentrations, must be adjusted as a function of layer thickness. Also, this threshold varies as a function of the composition of the depositing layer, and in those instances where the layer composition is profiled throughout its thickness, deposition parameters must be adjusted accordingly so as to maintain the amorphous/microcrystalline threshold.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: August 14, 2001
    Assignee: United Solar Systems Corporation
    Inventors: Subhendu Guha, Chi C. Yang
  • Patent number: 6265288
    Abstract: A method of fabricating a silicon-based thin-film photoelectric conversion device, where a plasma CVD process is used to deposit a polycrystalline photoelectric conversion layer. During the deposition of the photoelectric conversion layer, the temperature of the underlying layer is less than 550° C., the pressure in the plasma chamber is more than 5 Torr, and the ratio of the flow rates of a hydrogen gas and a silane-type gas is more than 50. In addition, one of the following operations is carried out during the deposition to change the relevant parameters between the start and end of the deposition. First, the distance between the plasma discharge electrodes is increased gradually or in steps. Second, the pressure of the reaction chamber is increased gradually or in steps. Third, the flow rate of the silane-type gas is increased gradually. Fourth, the plasma discharge power density is reduced gradually or in steps.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: July 24, 2001
    Assignee: Kaneka Corporation
    Inventors: Yoshifumi Okamoto, Masashi Yoshimi
  • Patent number: 6235615
    Abstract: Generation of low work function, stable compound thin films by laser ablation. Compound thin films with low work function can be synthesized by simultaneously laser ablating silicon, for example, and thermal evaporating an alkali metal into an oxygen environment. For example, the compound thin film may be composed of Si/Cs/O. The work functions of the thin films can be varied by changing the silicon/alkali metal/oxygen ratio. Low work functions of the compound thin films deposited on silicon substrates were confirmed by ultraviolet photoelectron spectroscopy (UPS). The compound thin films are stable up to 500° C. as measured by x-ray photoelectron spectroscopy (XPS). Tests have established that for certain chemical compositions and annealing temperatures of the compound thin films, negative electron affinity (NEA) was detected. The low work function, stable compound thin films can be utilized in solar cells, field emission flat panel displays, electron guns, and cold cathode electron guns.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: May 22, 2001
    Assignee: The Regents of the University of California
    Inventors: Long N. Dinh, William McLean, II, Mehdi Balooch, Edward J. Fehring, Jr., Marcus A. Schildbach
  • Patent number: 6235563
    Abstract: An improved polycrystalline or polysilicon film having large grain size, such as 1 &mgr;m to 2 &mgr;m in diameter or greater, is obtained over the methods of the prior art by initially forming a silicon film, which may be comprised of amorphous silicon or micro-crystalline silicon or contains micro-crystal regions in the amorphous phase, at a low temperature via a chemical vapor deposition (CVD) method, such as by plasma chemical vapor deposition (PCVD) with silane gas diluted with, for example, hydrogen, argon or helium at a temperature, for example, in the range of room temperature to 600° C. This is followed by solid phase recrystallization of the film to form a polycrystalline film which is conducted at a relatively low temperature in the range of about 550° C. to 650° C. in an inert atmosphere, e.g., N or Ar, for a period of about several hours to 40 or more hours wherein the temperature is gradually increased, e.g., at a temperature rise rate below 20° C./min, preferably about 5° C.
    Type: Grant
    Filed: November 7, 1991
    Date of Patent: May 22, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Hideaki Oka, Satoshi Takenaka, Masafumi Kunii
  • Patent number: 6204197
    Abstract: An improved semiconductor device manufacturing system and method is shown. In the system, undesirable sputtering effect can be averted by virtue of a combination of an ECR system and at CVD system. Prior to the deposition according to the above combination, a sub-layer can be pre-formed on a substrate in a reaction chamber and transported to another chamber in which deposition is made according to the combination without making contact with air, so that a junction thus formed has good characteristics.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: March 20, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6191011
    Abstract: Systems and methods are described for semiconductor wafer pretreatment. A method of increasing the selectivity of silicon deposition with regard to an underlying oxide layer during deposition of a silicon containing material by broadening a selective temperature of formation window for said silicon containing material by decreasing a lower temperature endpoint includes: providing a semiconductor wafer with the underlying oxide layer in a processing chamber; then pumping water from then processing chamber; and then depositing the silicon containing material on the semiconductor wafer. A step of seeding the semiconductor wafer can be conducted by exposing the semiconducotor wafer to a germanium containing gas. A chlorine containing precursor and/or hydrogen can be introduced into the processing chamber to increase the selectivity of the silicon containing material to the underlying oxide. The selective HSG temperature of formation window is widened.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: February 20, 2001
    Assignee: AG Associates (Israel) Ltd.
    Inventors: Yitzhak Eric Gilboa, Benjamin Brosilow, Sagy Levy, Hedvi Spielberg, Itai Bransky
  • Patent number: 6169013
    Abstract: A method is provided for optimizing the crystal drain size in polycrystalline silicon films deposited on transparent substrates suitable for the manufacture of liquid crystal displays. A film of microcrystalline silicon is deposited on a transparent substrate in a manner which yields microcrystallites embedded in the film during deposit. By means of excimer laser anneal, or another suitable annealing method, the microcrystalline silicon film is partially melted to leave a portion of the microcrystallites unmelted upon completion of the anneal. The film is then allowed to crystallize by crystal growth from the microcrystallites that remain unmelted in the film. The result is high quality polycrystalline silicon having large grain sizes suitable for active devices, such as TFTs.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: January 2, 2001
    Assignees: Sharp Laboratories of America, Inc., Sharp Kabushiki Kaisha
    Inventor: Tolis Voutsas
  • Patent number: 6162707
    Abstract: Generation of low work function, stable compound thin films by laser ablation. Compound thin films with low work function can be synthesized by simultaneously laser ablating silicon, for example, and thermal evaporating an alkali metal into an oxygen environment. For example, the compound thin film may be composed of Si/Cs/O. The work functions of the thin films can be varied by changing the silicon/alkali metal/oxygen ratio. Low work functions of the compound thin films deposited on silicon substrates were confirmed by ultraviolet photoelectron spectroscopy (UPS). The compound thin films are stable up to 500.degree. C. as measured by x-ray photoelectron spectroscopy (XPS). Tests have established that for certain chemical compositions and annealing temperatures of the compound thin films, negative electron affinity (NEA) was detected. The low work function, stable compound thin films can be utilized in solar cells, field emission flat panel displays, electron guns, and cold cathode electron guns.
    Type: Grant
    Filed: May 18, 1998
    Date of Patent: December 19, 2000
    Assignee: The Regents of the University of California
    Inventors: Long N. Dinh, William McLean, II, Mehdi Balooch, Edward J. Fehring, Jr., Marcus A. Schildbach
  • Patent number: 6162717
    Abstract: A method of forming the gate structure of a MOS device forms a gate structure over a semiconductor substrate and then treats the sidewalls of the gate structure with nitrous oxide plasma so that the silicon and tungsten atoms within the gate structure can react with activated nitrogen in the plasma to form chemical bonds. Hence, a protective layer is formed on the gate sidewalls, thereby increasing thermal stability of the tungsten suicide layer and the polysilicon layer within the gate structure. Thereafter, an oxide material is formed over the protective layer using a rapid thermal oxidation. Next, spacers are formed over the sidewall oxide layer. Finally, subsequent operations necessary for forming a complete MOS device are performed.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: December 19, 2000
    Assignees: ProMOS Technologies, Inc, Mosel Vitelic, Inc., Siemens AG
    Inventor: Ta-Hsun Yeh
  • Patent number: 6159763
    Abstract: There is provided a method of forming a photovoltaic element, in which a p-type semiconductor layer is formed in a device for forming a semiconductor thin film having a cathod electrode structure, in which in a plasma discharge space, the surface area of a cathod electrode in a plasma discharge space is larger than the sum of surface areas of a belt-like member and an anode electrode, a potential of said cathod electrode at the time of excitation of glow discharge is positive relative to the belt-like member and the anode electrode, and a separator electrode partially constituting the cathod electrode is configured to have a form of a fin or a block, and an n-type semiconductor layer is formed in a device for forming a semiconductor thin film having a cathod electrode structure of a capacitive-coupling, parallel-plate type.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: December 12, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Sakai, Yasushi Fujioka, Shotaro Okabe, Masahiro Kanai, Yuzo Kohda, Tadashi Hori, Takahiro Yajima