Deposition Utilizing Plasma (e.g., Glow Discharge, Etc.) Patents (Class 438/485)
  • Patent number: 8293626
    Abstract: It is an object to provide a homogeneous semiconductor film in which variation in the size of crystal grains is reduced. Alternatively, it is an object to provide a homogeneous semiconductor film and to achieve cost reduction. By introducing a glass substrate over which an amorphous semiconductor film is formed into a treatment atmosphere set at more than or equal to a temperature that is needed for crystallization, rapid heating due to heat conduction from the treatment atmosphere is performed so that the amorphous semiconductor film is crystallized. More specifically, for example, after the temperature of the treatment atmosphere is increased in advance to a temperature that is needed for crystallization, the substrate over which the semiconductor film is formed is put into the treatment atmosphere.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: October 23, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Naoki Okuno
  • Patent number: 8278195
    Abstract: In a plasma CVD apparatus, unnecessary discharge such as arc discharge is prevented, the amount of particles due to peeling of films attached to a reaction chamber is reduced, and the percentage of a time contributing to production in hours of operation of the apparatus is increased while enlargement of the apparatus and easy workability are maintained. The plasma CVD apparatus is configured such that in a conductive reaction chamber 104 with a power source 113, a vacuum exhausting means 118, and a reaction gas introduction pipe 114, plasma 115 is generated in a space surrounded by an electrode 111, a substrate holder 112, and an insulator 120.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Mitsunori Sakama, Hisashi Abe, Hiroshi Uehara, Mika Ishiwata
  • Patent number: 8273641
    Abstract: Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus avoids unintended deposition on windows or other microwave transmission elements that couple microwave energy to deposition species. The apparatus includes a microwave applicator with one or more conduits passing therethrough that carry deposition species. The applicator transfers microwave energy to the deposition species to activate or energize them to a reactive state. The conduits physically isolate deposition species that would react or otherwise combine to form a thin film material at the point of microwave power transfer and deliver the microwave-excited species to a deposition chamber. One or more supplemental material streams may be delivered directly to the deposition chamber without passing through the microwave applicator and may combine with deposition species exiting the one or more conduits to form a thin film material.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: September 25, 2012
    Assignee: Ovshinsky Innovation LLC
    Inventor: Stanford R. Ovshinsky
  • Patent number: 8252668
    Abstract: Provided is a photoelectric conversion device fabrication method that realizes both high productivity and high conversion efficiency by rapidly forming an n-layer having good coverage. The fabrication method for a photoelectric conversion device includes a step of forming a silicon photoelectric conversion layer on a substrate by a plasma CVD method. In the fabrication method for the photoelectric conversion device, the step of forming the photoelectric conversion layer includes a step of forming an i-layer formed of crystalline silicon and a step of forming, on the i-layer, an n-layer under a condition with a hydrogen dilution ratio of 0 to 10, inclusive.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: August 28, 2012
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Kengo Yamaguchi, Satoshi Sakai, Yoshiaki Takeuchi
  • Patent number: 8247315
    Abstract: By an evacuation unit including first and second turbo molecular pumps connected in series, the ultimate pressure in a reaction chamber is reduced to ultra-high vacuum. By a knife-edge-type metal-seal flange, the amount of leakage in the reaction chamber is reduced. A microcrystalline semiconductor film and an amorphous semiconductor film are stacked in the same reaction chamber where the pressure is reduced to ultra-high vacuum. By forming the amorphous semiconductor film covering the surface of the microcrystalline semiconductor film, oxidation of the microcrystalline semiconductor film is prevented.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Furuno, Tetsuo Sugiyama, Taichi Nozawa, Mitsuhiro Ichijo, Ryota Tajima, Shunpei Yamazaki
  • Publication number: 20120193632
    Abstract: Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.
    Type: Application
    Filed: January 24, 2012
    Publication date: August 2, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Satoshi TORIUMI
  • Patent number: 8231800
    Abstract: There is provided a plasma processing apparatus including a plasma generating unit for generating a plasma in a processing chamber in which a set processing is performed on a substrate serving as an object to be processed. The plasma processing apparatus further includes a particle moving unit for electrostatically driving particles in a region above the substrate to be removed out of the region above the substrate in the processing chamber while the processing on the substrate is performed by using the plasma. In addition, there is provided a plasma processing method of a plasma processing apparatus including the steps of generating plasma in a processing chamber in which a set processing is performed on a substrate serving as an object to be processed; and performing the processing on the substrate by the plasma.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: July 31, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Tsuyoshi Moriya, Hiroyuki Nakayama
  • Patent number: 8222125
    Abstract: Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus avoids deposition on windows or other microwave transmission elements that couple microwave energy to deposition species. The apparatus includes a microwave applicator with conduits passing therethrough that carry deposition species. The applicator transfers microwave energy to the deposition species to transform them to a reactive state conducive to formation of a thin film material. The conduits physically isolate deposition species that would react to form a thin film material at the point of microwave power transfer. The deposition species are separately energized and swept away from the point of power transfer to prevent thin film deposition. The invention allows for the ultrafast formation of silicon-containing amorphous semiconductors that exhibit high mobility, low porosity, little or no Staebler-Wronski degradation, and low defect concentration.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: July 17, 2012
    Assignee: Ovshinsky Innovation, LLC
    Inventors: Stanford R. Ovshinsky, David Strand, Patrick Klersy, Boil Pashmakov
  • Patent number: 8207049
    Abstract: A solar cell fabrication process is described that includes etching a cap layer into a front surface of a semiconductor structure, depositing an anti-reflective coating onto the front surface of the semiconductor structure, forming a front electrical contact on the front surface of the semiconductor structure, forming a first back metal contact on a back surface of the semiconductor structure, utilizing a plasma enhanced chemical vapor deposition (PECVD) process to apply a dielectric layer to the first back metal contact, the PECVD process performed at within a temperature environment and for a duration that allows for the annealing of metal associated with the front electrical contact and the first back metal contact, and attaching at least one secondary electrical contact to the dielectric layer.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: June 26, 2012
    Assignee: The Boeing Company
    Inventors: Xiaobo Zhang, Julie Hoskin
  • Patent number: 8198179
    Abstract: A method for producing a group III nitride semiconductor light-emitting device including: an intermediate layer formation step in which an intermediate layer containing group III nitride is formed on a substrate by sputtering, and a laminate semiconductor formation step in which an n-type semiconductor layer having a base layer, a light-emitting layer, and a p-type semiconductor layer are laminated on the intermediate layer in this order, wherein the method includes a pretreatment step in which the intermediate layer is treated using plasma between the intermediate layer formation step and the laminate semiconductor formation step, and a formation step for the base layer which is included in the laminate semiconductor formation step is a step for laminating the base layer by sputtering.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: June 12, 2012
    Assignee: Showa Denko K.K.
    Inventors: Yasumasa Sasaki, Hisayuki Miki
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Publication number: 20120100675
    Abstract: To provide a manufacturing method of a microcrystalline silicon film having both high crystallinity and high film density. In the manufacturing method of a microcrystalline silicon film according to the present invention, a first microcrystalline silicon film that includes mixed phase grains is formed over an insulating film under a first condition, and a second microcrystalline silicon film is formed thereover under a second condition. The first condition and the second condition are a condition in which a deposition gas containing silicon and a gas containing hydrogen are used as a first source gas and a second source gas. The first source gas is supplied under the first condition in such a manner that supply of a first gas and supply of a second gas are alternately performed.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 26, 2012
    Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Ryu KOMATSU, Yasuhiro JINBO, Hidekazu MIYAIRI, Yoshitaka YAMAMOTO
  • Patent number: 8148245
    Abstract: There is provided a method for producing an a-IGZO oxide thin film by sputtering, which can control the carrier density of the film to a given value with high reproducibility. The method is an amorphous In—Ga—Zn—O based oxide thin film production method including: providing a sintered oxide material consisting essentially of indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as constituent elements, wherein the ratio [In]/([In]+[Ga]) of the number of indium atoms to the total number of indium and gallium atoms is from 20% to 80%, the ratio [Zn]/([In]+[Ga]+[Zn]) of the number of zinc atoms to the total number of indium, gallium and zinc atoms is from 10% to 50%, and the sintered oxide material has a specific resistance of 1.0×10?1 ?cm or less; and producing a film on a substrate by direct current sputtering at a sputtering power density of 2.5 to 5.5 W/cm2 using the sintered oxide material as a sputtering target.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: April 3, 2012
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Masakatsu Ikisawa, Masataka Yahagi
  • Patent number: 8093142
    Abstract: There is provided a plasma processing device capable of forming a film in a favorable manner irrespective of deflection generated in an anode electrode and a cathode electrode in the case where an area of the electrodes is increased. A plasma processing device 100 includes a chamber 15, a gas introducing portion 28, an exhaust unit 29, and a high-frequency power supply unit 30. In the chamber 15, there are provided an anode electrode (first electrode) 4 having a flat-plate shape, a cathode electrode (second electrode) 12 having a flat-plate shape, and first supporting members 6 and second supporting members 5 for slidably supporting the two electrodes 4 and 12 in parallel with each other. The cathode electrode 12 is provided so as to face the anode electrode 4. The anode electrode 4 and the cathode electrode 12 are not fixed with screws or the like but are merely placed on the first supporting members 6 and the second supporting members 5.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: January 10, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yusuke Fukuoka, Katsushi Kishimoto
  • Publication number: 20120003787
    Abstract: A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 5, 2012
    Inventors: Tetsuhiro Tanaka, Erika Kato
  • Patent number: 8069817
    Abstract: Showerhead electrodes for a semiconductor material processing apparatus are disclosed. An embodiment of the showerhead electrodes includes top and bottom electrodes bonded to each other. The top electrode includes one or more plenums. The bottom electrode includes a plasma-exposed bottom surface and a plurality of gas holes in fluid communication with the plenum. Showerhead electrode assemblies including a showerhead electrode flexibly suspended from a top plate are also disclosed. The showerhead electrode assemblies can be in fluid communication with temperature-control elements spatially separated from the showerhead electrode to control the showerhead electrode temperature. Methods of processing substrates in plasma processing chambers including the showerhead electrode assemblies are also disclosed.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: December 6, 2011
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, Rajinder Dhindsa
  • Patent number: 8053338
    Abstract: In a plasma CVD apparatus, unnecessary discharge such as arc discharge is prevented, the amount of particles due to peeling of films attached to a reaction chamber is reduced, and the percentage of a time contributing to production in hours of operation of the apparatus is increased while enlargement of the apparatus and easy workability are maintained. The plasma CVD apparatus is configured such that in a conductive reaction chamber 104 with a power source 113, a vacuum exhausting means 118, and a reaction gas introduction pipe 114, plasma 115 is generated in a space surrounded by an electrode 111, a substrate holder 112, and an insulator 120.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: November 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Mitsunori Sakama, Hisashi Abe, Hiroshi Uehara, Mika Ishiwata
  • Patent number: 8048782
    Abstract: Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus avoids deposition on windows or other microwave transmission elements that couple microwave energy to deposition species. The apparatus includes a microwave applicator with conduits passing therethrough that carry deposition species. The applicator transfers microwave energy to the deposition species to transform them to a reactive state conducive to formation of a thin film material. The conduits physically isolate deposition species that would react to form a thin film material at the point of microwave power transfer. The deposition species are separately energized and swept away from the point of power transfer to prevent thin film deposition. The invention allows for the ultrafast formation of silicon-containing amorphous semiconductors that exhibit high mobility, low porosity, little or no Staebler-Wronski degradation, and low defect concentration.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: November 1, 2011
    Assignee: Ovshinsky Innovation LLC
    Inventors: Stanford R. Ovshinsky, David Strand, Patrick Klersy, Boil Pashmakov
  • Patent number: 8043945
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Shinji Mori, Masahiko Murano, Tsutomu Sato, Takashi Nakao, Hiroshi Itokawa
  • Patent number: 8043484
    Abstract: Conductive or barrier material is deposited on a semiconductor substrate having recessed features by a method that has at least two operations. The first operation involves depositing a layer of the material on at least a portion of the field regions of the wafer. The second operation involves resputtering at least the layer residing on the field region of the wafer under high pressure. If the pressure is sufficiently high, momentum transfer reflection of the resputtered material will take place, such that at least some of the resputtered material is placed in the recessed features of the wafer. This approach can, among other advantages, offer improved step coverage and better utilization of the material.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: October 25, 2011
    Assignee: Novellus Systems, Inc.
    Inventor: Robert Rozbicki
  • Patent number: 8030206
    Abstract: A solar cell fabrication process is described that includes etching a cap layer into a front surface of a semiconductor structure, depositing an anti-reflective coating onto the front surface of the semiconductor structure, forming a front electrical contact on the front surface of the semiconductor structure, forming a first back metal contact on a back surface of the semiconductor structure, utilizing a plasma enhanced chemical vapor deposition (PECVD) process to apply a dielectric layer to the first back metal contact, the PECVD process performed at within a temperature environment and for a duration that allows for the annealing of metal associated with the front electrical contact and the first back metal contact, and attaching at least one secondary electrical contact to the dielectric layer.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: October 4, 2011
    Assignee: The Boeing Company
    Inventors: Xiaobo Zhang, Julie Hoskin
  • Patent number: 8026157
    Abstract: Embodiments of the present invention generally relate to methods of forming a microcrystalline silicon layer on a substrate in a deposition chamber. In, one embodiment, the method includes flowing a processing gas into a diffuser region between a backing plate and a showerhead of the deposition chamber, flowing the processing gas through a plurality of holes in the showerhead and into a process volume between the showerhead and a substrate support in the deposition chamber, igniting a plasma in the process volume, back-flowing gas ions formed in the plasma through the plurality of holes in the showerhead and into the diffuser region, mixing the gas ions and the processing gas in the diffuser region, re-flowing the gas ions and processing gas through the plurality of holes in the showerhead and into the process volume, and depositing a microcrystalline silicon layer on the substrate.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: September 27, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Xiesen Yang, Yong-Kee Chae, Shuran Sheng, Liwei Li
  • Patent number: 8012784
    Abstract: Provided is a method for producing a group III nitride semiconductor light emitting device capable of producing a group III nitride semiconductor light emitting device with excellent light emitting properties with excellent productivity; a group III nitride semiconductor light emitting device; and a lamp. Provided is a method in which a buffer layer 12 composed of a group III nitride compound is laminated on a substrate 11 and then an n-type semiconductor layer 14 provided with an underlying layer 14a, a light emitting layer 15, and an p-type semiconductor layer 16 are sequentially laminated on the buffer layer 12, and is a method in which the buffer layer 12 is formed so as to have a composition of AlXGa1-XN (0?X<1) by activating, with plasma, and thereby reacting at least a metallic Ga source and a gas containing a group V element, and the underlying layer 14 is formed on the buffer layer 12.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: September 6, 2011
    Assignee: Showa Denko K.K.
    Inventors: Hisayuki Miki, Yasunori Yokoyama, Takehiko Okabe, Kenzo Hanawa
  • Patent number: 7998884
    Abstract: A light emitting device using a silicon (Si) nanocrystalline Si insulating film is presented with an associated fabrication method. The method provides a doped semiconductor or metal bottom electrode. Using a high density plasma-enhanced chemical vapor deposition (HDPECVD) process, a Si insulator film is deposited overlying the semiconductor electrode, having a thickness in a range of 30 to 200 nanometers (nm). For example, the film may be SiOx, where X is less than 2, Si3Nx, where X is less than 4, or SiCx, where X is less than 1. The Si insulating film is annealed, and as a result, Si nanocrystals are formed in the film. Then, a transparent metal electrode is formed overlying the Si insulator film. An annealed Si nanocrystalline SiOx film has a turn-on voltage of less than 20 volts, as defined with respect to a surface emission power of greater than 0.03 watt per square meter.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: August 16, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jiandong Huang, Pooran Chandra Joshi, Apostolos T. Voutsas, Hao Zhang
  • Patent number: 7998843
    Abstract: Methods and systems for forming an amorphous silicon layer are disclosed for one or more embodiments. For example, a substrate may be provided, and an amorphous silicon layer, in which a ratio of Si—H to Si—H2 has a value equal to or less than 4 to 1, may be formed on the substrate using chemical vapor deposition equipment.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hyung Hwang, Hyung-Il Jeon, Seok-Joon Hong
  • Patent number: 7998842
    Abstract: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Hyungjun Kim, Stephen M. Rossnagel
  • Patent number: 7993994
    Abstract: A method of crystallizing amorphous silicon comprises forming an amorphous silicon layer on a substrate; forming an insulating layer on the amorphous silicon layer; forming a heat distributing metal layer on the insulating layer; and forming a thermite layer on the heat distributing metal layer. Ignition heat is then applied to ignite the thermite layer and generate sufficient localized exothermic heat from the ignited thermite layer so as to crystallize the amorphous silicon layer. The substrate beneath the amorphous silicon layer can be a heat sensitive substrate which is not substantially deformed by the localized crystallizing heat applied to the top portion of the amorphous silicon layer by way of the heat distributing metal layer and the insulating layer.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: August 9, 2011
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Younsei University
    Inventors: Tae-Hyung Hwang, Hyun-Jae Kim, Do-Kyung Kim, Woong-Hee Jeong, Choong-Hee Lee, Tae-Hun Jung
  • Publication number: 20110189841
    Abstract: One aspect of the present invention relates to a method for fabricating a polycrystalline silicon film. In one embodiment, the method includes the steps of providing a substrate having a thermally-grown silicon dioxide layer, forming an amorphous silicon film on the thermally-grown silicon dioxide layer of the substrate, forming an aluminum layer on the amorphous silicon film to form a structure having the substrate, the amorphous silicon film and the aluminum layer, and annealing the structure at an annealing temperature for a period of time in an N2 environment with a ramp-up time to crystallize the amorphous silicon film to form a polycrystalline silicon film.
    Type: Application
    Filed: April 11, 2011
    Publication date: August 4, 2011
    Applicant: BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
    Inventors: Min Zou, Li Cai, William David Brown
  • Patent number: 7989330
    Abstract: After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is improved due to the rise in a wafer temperature or the low pressure of a processing pressure, thereby preventing a side etching and unevenness of a sidewall of the polysilicon film. Further, by using the protective film made of a carbon polymer, metallic substances scattered at the time of etching the metallic material are not directly attached to the polysilicon film, but can be simply removed along with the protective film made of a carbon polymer in an asking step.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: August 2, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takeshi Shima, Kenichi Kuwabara, Tomoyoshi Ichimaru, Kenji Imamoto
  • Patent number: 7981776
    Abstract: The inventive method for depositing silicon onto a substrate firstly involves the introduction of a reactive silicon-containing gas and hydrogen into the plasma chamber and then the initiation of the plasma. After initiating the plasma, only reactive silicon-containing gas or a gas mixture containing hydrogen is supplied to the plasma chamber in an alternatively continuous manner, and the gas mixture located inside the chamber is, at least in part, simultaneously withdrawn from the chamber. From the start, homogeneous microcrystalline silicon is deposited onto the substrate in the presence of hydrogen.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: July 19, 2011
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Tobias Roschek, Bernd Rech
  • Patent number: 7981777
    Abstract: The present invention provides PECVD methods for forming stable and hermetic ashable hard masks (AHMs). The methods involve depositing AHMs using dilute hydrocarbon precursor gas flows and/or high LFRF/HFRF ratios. In certain embodiments, the AHMs are transparent and have high etch selectivities. Single and dual layer hermetic AHM stacks are also provided. According to various embodiments, the dual layer stack includes an underlying AHM layer having tunable optical properties and a hermetic cap layer.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: July 19, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Pramod Subramonium, Yongsik Yu, Zhiyuan Fang, Jon Henri
  • Patent number: 7968436
    Abstract: Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: June 28, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Yongsik Yu, Karen Billington, Xingyuan Tang, Haiying Fu, Michael Carris, William Crew
  • Patent number: 7960252
    Abstract: An apparatus for high-rate chemical vapor (CVD) deposition of semiconductor films comprises a reaction chamber for receiving therein a substrate and a film forming gas, a gas inlet for introducing the film forming gas into the reaction chamber, an incidence window in the reaction chamber for transmission of a laser sheet into the reaction chamber, a laser disposed outside the reaction chamber for generating the laser sheet and an antenna disposed outside the reaction chamber for generating a plasma therein. The film forming gas in the chamber is excited and decomposed by the laser sheet, which passes in parallel with the substrate along a plane spaced apart therefrom, and concurrent ionization effected by the antenna, thereby forming a dense semiconductor film on the substrate at high rate.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: June 14, 2011
    Inventor: Yung-Tin Chen
  • Patent number: 7955883
    Abstract: Interdigitated electrode arrays are very promising devices for multi-parameter (bio)sensing, for example the label-free detection of nucleic acid hybridization for diagnostic applications. The current disclosure provides an innovative method for the affordable manufacturing of polymer-based arrays of interdigitated electrodes with ?m-dimensions. The method is based on a combination of an appropriate three-dimensional structure and a single and directional deposition of conductive material. The three-dimensional structure can be realized in a polymer material using a molding step, for which the molds are manufactured by electroplating as a reverse copy of a silicon master structure. In order to ensure sufficient electrical isolation and individual, but convenient, accessibility of the sensors in the array, the interdigitated electrode regions need to be complemented with specific features on the three-dimensional structure. Combined with the use of e.g.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 7, 2011
    Assignees: IMEC, Innogenetics
    Inventors: Wim Laureyn, Jan Suls, Paul Jacobs
  • Patent number: 7955890
    Abstract: Embodiments of the present invention relate to methods for depositing an amorphous film that may be suitable for using in a NIP photodiode in display applications. In one embodiment, the method includes providing a substrate into a deposition chamber, supplying a gas mixture having a hydrogen gas to silane gas ratio by volume greater than 4 into the deposition chamber, maintaining a pressure of the gas mixture at greater than about 1 Torr in the deposition chamber, and forming an amorphous silicon film on the substrate in the presence of the gas mixture, wherein the amorphous silicon film is configured to be an intrinsic-type layer in a photodiode sensor.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: June 7, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Soo Young Choi, Jriyan Jerry Chen, Tae Kyung Won, Dong-Kil Yim
  • Patent number: 7947579
    Abstract: Barrier layers and methods for forming barrier layers on a porous layer are provided. The methods can include chemically adsorbing a plurality of first molecules on a surface of the porous layer in a chamber and forming a first layer of the first molecules on the surface of the porous layer. A plasma can then be used to react a plurality of second molecules with the first layer of first molecules to form a first layer of a barrier layer. The barrier layers can seal the pores of the porous material, function as a diffusion barrier, be conformal, and/or have a negligible impact on the overall ILD k value of the porous material.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: May 24, 2011
    Assignee: STC.UNM
    Inventors: Ying-Bing Jiang, Joseph L. Cecchi, C. Jeffrey Brinker
  • Patent number: 7939434
    Abstract: A method of directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first polysilicon sub-layer on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second polysilicon sub-layer on the first sub-layer. The first and second sub-layers constitute the polysilicon film, and the first bias voltage differs from the second bias voltage.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: May 10, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Yuan Tseng, I Hsuan Peng, Yung-Hui Yeh, Jung-Jie Huang, Cheng-Ju Tsai
  • Patent number: 7927982
    Abstract: A silicon-based thin film mass-producing apparatus, including transparent electrodes placed to face in parallel to corresponding counter electrodes with a space therebetween, and silicon-based thin films are deposited on the transparent electrodes by feeding a raw material gas for depositing the silicon-based thin films into the chamber and by applying a DC pulse voltage to the counter electrodes to generate plasma. Unlike methods in which a radio frequency voltage is intermittently applied to perform discharge, a high plasma density distribution does not occur, and in-plane film thickness distribution does not occur. Furthermore, since the DC pulse voltage rises sharply, the ON period can be shortened. As a result, generation of a sheath ceases in the transient state before reaching the steady state, and the thickness of the sheath is small, which allows the space between the counter and transparent electrodes to decrease.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: April 19, 2011
    Assignee: NGK Insulators, Ltd.
    Inventors: Minoru Imaeda, Yuichiro Imanishi, Takao Saito
  • Patent number: 7927907
    Abstract: The invention relates to a method for producing solar cells comprising at least one p-i-n layer sequence containing micro-crystalline layers with the aid of a PECVD method. Said method is characterised in that all layers of the p-i-n layer sequence are deposited in a single-chamber process. The electrodes are interspaced at a distance of between 5 and 15 mm and the gas is distributed by means of a shower-head gas inlet, which guarantees a homogeneous distribution of the gas over the substrate. SiH4 gas streams with values of between 0.01 and 3 sccm/cm2 are added with a process pressure of between 8 and 50 hPa. The heater temperature is set at between 50 and 280° C. and the HF output is between 0.2 and 2 watt/cm2. The H2 gas streams have values of between 0.3 and 30 sccm/cm2, in particular between 0.3 and 10 sccm/cm2.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: April 19, 2011
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Tobias Repmann, Bernd Rech
  • Patent number: 7927981
    Abstract: A silicon-based thin film depositing apparatus, including a plurality of transparent electrodes disposed to face corresponding counter electrodes with a space therebetween. Subsequently, while injecting a raw material gas from raw material gas injection orifices toward the supporting electrodes and also injecting a barrier gas from barrier gas injection orifices in the same direction as the direction in which the raw material gas is injected, the gases are discharged from a gas outlet, and thereby, the pressure in a chamber is controlled to a pressure of more than 1 kPa. Then, a DC pulse voltage is applied to each counter electrode to deposit a silicon-based thin film. A DC pulse voltage is applied to perform discharge. Therefore, even in a state where the distance between the electrodes is increased, plasma can be generated efficiently, and the in-plane distribution of film thickness can be improved.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: April 19, 2011
    Assignee: NGK Insulators, Ltd.
    Inventors: Minoru Imaeda, Yuichiro Imanishi, Takao Saito
  • Patent number: 7923356
    Abstract: Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method, a condition is provided with a frequency of 15 to 25 kHz and a deposition power of 0.5 to 3 kW. This can sufficiently contain Ar at 10×1020/cm3 or more in an amorphous silicon film, thus making possible to form an amorphous silicon film having distortion.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: April 12, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Kengo Akimoto
  • Patent number: 7902050
    Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: March 8, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya Sato, Patricia M. Liu, Fanos Christodoulou
  • Patent number: 7902049
    Abstract: A process for the plasma deposition of a layer of a microcrystalline semiconductor material is carried out by energizing a process gas which includes a precursor of the semiconductor material and a diluent with electromagnetic energy so as to create a plasma therefrom. The plasma deposits a layer of the microcrystalline semiconductor material onto the substrate. The concentration of the diluent in the process gas is varied as a function of the thickness of the layer of microcrystalline semiconductor material which has been deposited. Also disclosed is the use of the process for the preparation of an N-I-P type photovoltaic device.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: March 8, 2011
    Assignee: United Solar Ovonic LLC
    Inventors: Subhendu Guha, Chi C. Yang, Baojie Yan
  • Patent number: 7888245
    Abstract: A plasma doping method includes providing a doping source over a substrate. The doping source includes dopants that are to be injected into the substrate. At least two different bias voltages are applied to inject the dopants from the doping source to the substrate.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: February 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Sung Roh, Jae-Geun Oh, Hyun-Chul Sohn, Sun-Hwan Hwang, Jin-Ku Lee
  • Patent number: 7879697
    Abstract: Methods of growing Group-III nitride thin-film structures having reduced dislocation density are provided. Methods in accordance with the present invention comprise growing a Group-III nitride thin-film material while applying an ion flux and preferably while the substrate is stationary or non-rotating substrate. The ion flux is preferably applied as an ion beam at a glancing angle of incidence. Growth under these conditions creates a nanoscale surface corrugation having a characteristic features size, such as can be measured as a wavelength or surface roughness. After the surface corrugation is created, and preferably in the same growth reactor, the substrate is rotated in an ion flux which cause the surface corrugation to be reduced. The result of forming a surface corrugation and then subsequently reducing or removing the surface corrugation is the formation of a nanosculpted region and polished transition region that effectively filter dislocations.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: February 1, 2011
    Assignee: Regents of the University of Minnesota
    Inventors: Philip I. Cohen, Bentao Cui
  • Patent number: 7871676
    Abstract: The present invention relates to an enhanced sequential atomic layer deposition (ALD) technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. This is accomplished by 1) providing a non-thermal or non-pyrolytic means of triggering the deposition reaction; 2) providing a means of depositing a purer film of higher density at lower temperatures; and, 3) providing a faster and more efficient means of modulating the deposition sequence and hence the overall process rate resulting in an improved deposition method.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: January 18, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Tony P. Chiang, Karl F. Leeser
  • Patent number: 7871928
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: January 18, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Patent number: 7867801
    Abstract: An apparatus for producing a group-III nitride semiconductor layer which forms a group-III nitride semiconductor layer on a substrate by a sputtering method, the apparatus including: a first plasma-generating region where a target containing a group-III element is disposed and the target is sputtered to generate material particles formed of a material contained in the target; and a second plasma generating region where the substrate is disposed and nitrogen-containing plasma is generated. The first plasma-generating region and the second plasma-generating region are provided inside a chamber, and the first plasma-generating region and the second plasma-generating region are separated by a shielding wall which has an opening part from which the material particles are supplied onto the substrate. Also disclosed are a method of producing a group-III nitride semiconductor layer, a method of producing a group-III nitride semiconductor light-emitting device, and a lamp thereof.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: January 11, 2011
    Assignee: Showa Denko K.K.
    Inventors: Yasunori Yokoyama, Takehiko Okabe, Hisayuki Miki
  • Patent number: 7863113
    Abstract: A transistor for active matrix display and a method for producing the transistor (1). The transistor (1) includes a microcrystalline silicon film (5) and an insulator (3). The crystalline fraction of the microcrystalline silicon film (5) is above 80%. According to the invention, the transistor (1) includes a plasma treated interface (4) located between the insulator (3) and the microcrystalline silicon film (5) so that the transistor (1) has a linear mobility equal or superior to 1.5 cm2V?1s?1, shows threshold voltage stability and wherein the microcrystalline silicon film (5) includes grains (6) whose size ranges between 10 nm and 400 nm. The invention concerns as well a display unit having a line-column matrix of pixels that are actively addressed, each pixel comprising at least a transistor as described above.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: January 4, 2011
    Assignees: Centre National de la Recherche Scientifique, Ecole Polytechnique
    Inventors: Pere Roca I Cabarrocas, Régis Vanderhaghen, Bernard Drevillon
  • Patent number: 7851307
    Abstract: Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: December 14, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej Sandhu, Bhaskar Srinivasan, John Smythe