Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Abstract: A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not possible, the tool may inform its user, including making suggestions of additional resources that could allow the test system to perform the test or suggestions for other variations in input parameters that would allow a mapping. The tool employs an assignment process in which groups of associated pins are identified, along with associated resource requirements for each group. Groups of test system resources that collectively fulfill a higher level requirement are identified and the assignment is made by mapping resource sets to resource groups, using ordering and matching heuristics to reduce processing time.

Abstract: A semiconductor structure comprises a dielectric layer, a conduction piece, a first metal piece, a first protecting layer, and a second protecting layer. The conduction piece is surrounded by electrical materials of the dielectric layer. The first metal piece is over the dielectric layer and is in contact with the conduction piece. The first protecting layer covers dielectric materials of the dielectric layer that are not covered by the first metal piece. The second protecting layer is over the first protecting layer.

Abstract: A platen for polishing a surface of a wafer has a reaction plate, a polishing plate, and a bladder. The reaction plate has a top and bottom surface, and defines a longitudinal axis. The polishing plate is positioned coaxially with the reaction plate. The polishing plate has a second top surface and a second bottom surface. The second top surface is adjacent to the bottom surface of the reaction plate. The bladder is coaxially located along a radially outer portion of either the top or bottom surface of the reaction plate. The bladder is connected with the polishing plate and able to expand to deform the polishing plate with respect to the bottom surface of the reaction plate.

Abstract: A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.

Abstract: The invention relates to the technical field of an alignment method, and discloses a method for aligning substrate and mask, including: firstly forming at least one set of alignment marks on a mask plate; selecting a certain number of large-size substrates as sample substrates; forming a plurality of sets of alignment marks on each sample substrate using the mask plate and the at least one set of alignment marks formed thereon to divide the sample substrate into a plurality of sub-substrate areas; and then performing mask process on the respective sample substrates, accurate alignment for each sub-substrate area can be realized by means of the plurality of sets of alignment marks on the sample substrate, and one sub-substrate area can be accurately aligned by means of at least two sets of alignment marks formed on the sample substrate.

Abstract: A combination of deposition processes can be used to evaluate layer properties using a combinatorial workflow. The processes can include a base ALD process and another process, such as a PVD process. The high productivity combinatorial technique can provide an evaluation of the material properties for given ALD base layer and PVD additional elements. An ALD process can then be developed to provide the desired layers, replacing the ALD and PVD combination.

Abstract: Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400° C. and about 600° C. for at least about 1 hour.

Abstract: A segmented mask includes a set of cell structures, wherein each cell structure includes a set of features having an unresolvable segmentation pitch along a first direction, wherein the unresolvable segmentation pitch along the first direction is smaller than the illumination of the lithography printing tool, wherein the plurality of cell structures have a pitch along a second direction perpendicular to the first direction, wherein the unresolvable segmentation pitch is suitable for generating a printed pattern for shifting the best focus position of the lithography tool by a selected amount to achieve a selected level of focus sensitivity.

Abstract: One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate. The first plurality of variable-size solder bump structures are disposed on a bottom surface of the substrate. The first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package.

Abstract: An baking case body of tunnel type sterilization dryer comprises a case body (1), an air intake cavity (24) which is disposed in the case body (1), a conveyor mesh belt (7), and an air return channel (22). The conveyor mesh belt (7) is located between the air return channel (22) and the air intake cavity (24). The air intake cavity (24) is divided into two or more than two independent air intake chambers (21) by one or more than one air intake partition boards (11). A heater (9) is disposed in each air intake chamber (21), and a hot air generator (2), a diffuser fan cover (3), a high temperature and high efficient filter (4) and a temperature probe (5) are disposed sequentially in each air intake chamber (21) from top to bottom. Air return partition boards (15) are arranged in the air return channel (22), corresponding to the air intake partition boards (11). The air return channel (22) is divided into two or more than two air return cavities (23) by the air return partition boards (15).

Abstract: A deposition amount measuring apparatus includes a plate-shaped body having a rotating shaft, a plurality of deposition amount sensors along side surfaces of the body, the deposition amount sensors being configured to measure an amount of deposition material, and a housing surrounding the body, the housing including an inflow port that exposes one of the deposition amount sensors.

Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: A substrate processing apparatus includes: a reaction tube configured to accommodate a substrate holder holding a plurality of substrates and process a substrate held on the substrate holder; a heating unit installed outside the reaction tube and configured to heat an inside of the reaction tube; a protection tube installed to extend in a vertical direction in contact with an outer wall of the reaction tube; an insulating tube disposed inside the protection tube and having through-holes extending in a vertical direction; a thermocouple having a thermocouple junction provided at an upper end thereof, and thermocouple wires joined at the thermocouple junction and inserted into the through-holes of the insulating tube; a gas supply unit configured to supply a gas, for processing a substrate accommodated in the reaction tube, into the reaction tube; and an exhaust unit configured to exhaust a gas from the reaction tube.

Abstract: One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

Abstract: A solution for manufacturing semiconductors is provided. An embodiment provides a chemical vapor deposition reactor, which includes a chemical vapor deposition chamber. A substrate holder located in the chemical vapor deposition chamber can be rotated about its own axis at a first angular speed, and a gas injection component located in the chemical vapor deposition chamber can be rotated about an axis of the gas injection component at a second angular speed. The angular speeds are independently selectable and can be configured to cause each point on a surface of a substrate wafer to travel in an epicyclical trajectory within a gas flow injected by the gas injection component. An angle between the substrate holder axis and the gas injection component axis and/or a distance between the substrate holder axis and the gas injection component axis can be controlled variables.

Abstract: A method of balancing a microelectromechanical system comprises determining if a microelectromechanical system is balanced in a plurality of orthogonal dimensions, and if the microelectromechanical system is not balanced, selectively depositing a first volume of jettable material on a portion of the microelectromechanical system to balance the microelectromechanical system in the plurality of orthogonal dimensions. A jettable material for balancing a microelectromechanical system comprises a vehicle, and a dispersion of nano-particles within the vehicle, in which the total mass of jettable material deposited on the microelectromechanical system is equal to the weight percentage of nano-particles dispersed within the vehicle multiplied by the mass of jettable material deposited on the microelectromechanical system.

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.

Abstract: In a substrate processing apparatus 1 which performs a process on a substrate W, each of multiple processing modules 2 includes at least a first processing member 21 and a second processing member 22, and substrate transfer devices 15 and 17 transfer substrates W into the multiple processing modules 2. Further, a controller 3 configured to control the substrate processing apparatus 1 stores member operating possibility information on whether it is possible to use the first processing member 21 and the second processing member 22 provided in each of the multiple processing modules 2, and the controller 3 creates, based on the member operating possibility information and process recipe information on processes to be performed on the substrates W, a transfer schedule in which the substrate transfer devices 15 and 17 transfer the substrates W into the multiple processing modules 2 in parallel.

Abstract: A showerhead electrode assembly for use in a capacitively coupled plasma processing apparatus comprising a heat transfer plate. The heat transfer plate having independently controllable gas volumes which may be pressurized to locally control thermal conductance between a heater member and a cooling member such that uniform temperatures may be established on a plasma exposed surface of the showerhead electrode assembly.

Abstract: An apparatus for plasma processing a substrate is provided. The apparatus comprises a processing chamber, a substrate support disposed in the processing chamber, and a lid assembly coupled to the processing chamber. The lid assembly comprises a conductive gas distributor coupled to a power source. A tuning electrode may be disposed between the conductive gas distributor and the chamber body for adjusting a ground pathway of the plasma. A second tuning electrode may be coupled to the substrate support, and a bias electrode may also be coupled to the substrate support.

Abstract: A method is described for creating at least one recess in a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one mask to the semiconductor component, forming at least one lattice having at least one or more lattice openings in the mask over the recess to be formed, the lattice opening or lattice openings being formed as a function of the etching rate and/or the dimensioning of the recess to be formed; forming the recess below the lattice.

Abstract: A semiconductor processing device and a method of operating the same. The method may include measuring at least one property of a semiconductor wafer and determining a recipe for processing the semiconductor wafer based on the at least one property. The semiconductor wafer may be processed with a plurality of chemical mechanical polishing (CMP) modules based on the determined recipe, wherein the recipe comprises a value of at least one parameter for use by each of the plurality of CMP modules. The measurements may be made in situ or by an inline metrology device. The recipe and various parameters associated with the recipe may be determined by a controller of the semiconductor processing device.

Abstract: A method, apparatus and a system, for provided for performing a dynamic weighting technique for performing fault detection. The method comprises processing a workpiece and performing a fault detection analysis relating to the processing of the workpiece. The method further comprises determining a relationship of a parameter relating to the fault detection analysis to a detected fault and adjusting a weighting associated with the parameter based upon the relationship of the parameter to the detected fault.

Abstract: According to one embodiment, a microwave annealing apparatus is provided, including a housing shielding electromagnetic waves, a first electromagnetic wave source configured to apply a first electromagnetic wave into the housing, a second electromagnetic wave source configured to apply, into the housing, a second electromagnetic wave having a higher frequency than the first electromagnetic wave, a susceptor configured to hold a semiconductor substrate, made of a material transparent to the first electromagnetic wave and provided in the housing, a temperature measuring device configured to measure the temperature of the semiconductor substrate, and a control unit configured to control the power of each of the first and second electromagnetic wave sources in accordance with the temperature measured by the temperature measuring device.

Abstract: An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device, including measuring a physical amount related to an impurity concentration of a semiconductor wafer having a first thickness, deciding a second thickness of the semiconductor wafer based on a measurement value of the physical amount, the second thickness being thinner than the first thickness, and reducing the first thickness of the semiconductor wafer to approximately the same thickness as the second thickness.

Abstract: A wafer processing method divides a wafer along a plurality of crossing streets formed on the front side of the wafer to thereby partition a plurality of regions where a plurality of devices are respectively formed. The method includes a division groove forming step of cutting the back side of the wafer along each street by using a cutting blade to thereby form a division groove along each street with a predetermined thickness left between the bottom of the division groove and the front side of the wafer, a wafer supporting step of attaching the back side of the wafer to a dicing tape supported by an annular frame, and a wafer dividing step of applying an external force to the wafer attached to the dicing tape to thereby divide the wafer into the individual devices along the streets where the division grooves are respectively formed.

Abstract: In a control method, a first processing is performed on an object to be processed by controlling a temperature of a base to a first temperature and controlling a temperature of an electrostatic chuck that is disposed on a mounting surface of the base so as to mount thereon the object to be processed and has a heater installed therein to a second temperature. A second processing is performed on the object by controlling a temperature of the base to a third temperature and controlling a temperature of the electrostatic chuck to a fourth temperature by a heater. In the control method, a difference between the first temperature and the second temperature and a difference between the third temperature and the fourth temperature are within a tolerable temperature of the junction layer for bonding the base and the electrostatic chuck.

Abstract: An ion implantation system is provided having an ion implantation apparatus configured to provide a spot ion beam having a beam density to a workpiece, wherein the workpiece has a crystalline structure associated therewith. A scanning system iteratively scans one or more of the spot ion beam and workpiece with respect to one another along one or more axes. A controller is also provided and configured to establish a predetermined localized temperature of the workpiece as a predetermined location on the workpiece is exposed to the spot ion beam. A predetermined localized disorder of the crystalline structure of the workpiece is thereby achieved at the predetermined location, wherein the controller is configured to control one or more of the beam density of the spot ion beam and a duty cycle associated with the scanning system to establish the localized temperature of the workpiece at the predetermined location on the workpiece.

Abstract: A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.

Abstract: A method of forming a group III nitride semiconductor comprises: preparing a group III nitride semiconductor which contains a p-type dopant or an n-type dopant; and performing a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor. The treatment includes performing a first treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, which are supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and after the first treatment is performed, performing a second treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas, which are supplied to the treatment apparatus at a third flow rate and a fourth flow rate, respectively.

Abstract: A method of manufacturing a semiconductor device includes: (a) supplying a first process gas from a first process gas supply unit into a process chamber via a flow rate control device to form a film on a substrate; (b) transmitting a signal representing an exhaust pressure detected by a pressure detector to a controller after the first process gas is supplied into the process chamber; (c) controlling a pressure adjustor and the flow rate control device once the signal is received by the controller such that the exhaust pressure reaches a predetermined pressure; (d) supplying a purge gas from a purge gas supply unit into the process chamber to purge an inside atmosphere after forming the first film; and (e) supplying a second process gas from a second process gas supply unit into the process chamber via the flow rate control device to form a second film.

Abstract: A method can be used to produce a semiconductor component. A semiconductor layer sequence has an active region that is provided for generating radiation and also has an indicator layer. Material of the semiconductor layer sequence that is arranged on that side of the indicator layer that is remote from the active region is removed in regions. The material is removed using a dry-chemical removal of the semiconductor layer sequence. A property of a process gas is monitored during the removal to determine that the indicator layer has been reached based on a change in the property of the process gas.

Abstract: The present invention relates to an apparatus for manufacturing an inorganic thin-film solar cell, the apparatus including: a substrate stage which is mounted in a chamber and in which a solar cell substrate is disposed; and an inorganic powder supply unit including a nozzle configured to discharge an inorganic powder aerosol containing an inorganic powder onto the substrate stage in a supersonic flow so as to form a solar cell layer on the solar cell substrate, and an inorganic powder supply portion configured to supply the inorganic powder aerosol to the nozzle.

Abstract: A method and system for cleaving a film of material utilizing thermal flux. The method includes providing a substrate having a face and an underlying cleave region including a prepared initiation region. Additionally, the method includes subjecting the initiation region to a first thermal flux to form a cleave front separating the cleave region of the substrate to a film portion and a bulk portion. The method further includes subjecting an area of the bulk portion substantially in the vicinity of the cleave front to a second thermal flux to cause a temperature difference above and below the cleave region for inducing a propagation of the cleave front expanding the film portion to the area at the expense of the bulk portion. Furthermore, the method includes determining a scan path for the second thermal flux based on the cleave front. Moreover, the method includes scanning the second thermal flux to follow the scan path to further propagate the cleave front.

Abstract: A plasma processing tool for fabricating a semiconductor device on a semiconductor wafer includes an optical window disposed on a plasma chamber, remotely from a plasma region. The window is thermally connected to an electrical heater element capable of maintaining the window at a temperature of at least 30° C. A heater controller provides electrical power to the heater element. During operation of the plasma processing tool, the heater controller provides power to the heater element so as to maintain the window at a temperature of at least 30° C. during at least a portion of a plasma process step in which by-products are produced in the plasma chamber.

Abstract: An edge seal extruded onto at least a portion of one or more edges of a photovoltaic module is disclosed. A method for making a photovoltaic module comprising an extruded edge seal is also disclosed.

Abstract: A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad.

Abstract: [Object] To provide a method of bonding an organic molecular crystal layer, which is capable of bonding an organic molecular crystal layer to an electrode by controlling the alignment of the organic molecular crystal layer, and to provide a method of manufacturing an organic element using the bonding method. [Solving Means] Alignment of an organic molecular crystal layer 13 with respect to an electrode 12 is controlled by controlling an inclined angle of a side surface 12a of the electrode 12 with respect to a main surface of an insulating base 11, in the case where the electrode 12 and the organic molecular crystal layer 13 are formed on the insulating base 11, the organic molecular crystal layer 13 including an aromatic compound, the organic molecular crystal layer 13 being bonded to the electrode 12. The side surface of the electrode 12 may be formed to have a plurality of surfaces having different inclined angles.

Abstract: An organic layer deposition apparatus includes: a conveyer unit including a transfer unit for attaching a substrate, a first conveyer unit, and a second conveyer unit; and a deposition unit including a vacuum chamber and an organic layer deposition assembly for depositing an organic layer on the substrate. The organic layer deposition assembly includes: a deposition source for discharging a deposition material; a deposition source nozzle unit including a plurality of deposition source nozzles; a patterning slit sheet including a plurality of patterning slits that are arranged in a first direction; and a deposition source shutter that moves in the first direction, and selectively blocks the deposition material that is vaporized in the deposition source. The transfer unit moves between the first and second conveyer units. The transfer unit keeps the attached substrate spaced apart from the organic layer deposition assembly while being transferred by the first conveyer unit.

Abstract: By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.

Abstract: Methods for chemical mechanical polishing (CMP) of semiconductor substrates, and more particularly to temperature control during such chemical mechanical polishing are provided. In one aspect, the method comprises polishing the substrate with a polishing surface during a polishing process to remove a portion of the conductive material, repeatedly monitoring a temperature of the polishing surface during the polishing process, and exposing the polishing surface to a rate quench process in response to the monitored temperature so as to achieve a target value for the monitored temperature during the polishing process.

Abstract: A method for producing a substrate, the method including: forming a porous zone in an inner layer of the substrate; progressively thinning a thickness of the substrate towards the inner layer including the porous zone; completing the progressively thinning by polishing; and controlled stopping of the polishing by detecting the porous zone during the polishing, the detecting including measuring at least one measurable physical parameter admitting a significant variation during a transition between two layers.

Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

Abstract: An integrated circuit is formed by identifying process parameters of a plurality of process steps for the first partial lot containing the integrated circuit; confirming the number of wafers in the first partial lot is less than the wafer carrier capacity; examining lots upstream of the partial lot and identifying a second partial lot which can be combined with the first partial lot into a single wafer carrier and which can be processed with the first partial lot; combining the wafers of the partial lots into a single wafer carrier; processing the partial lots through the plurality of process steps; and performing a multi-lot verification process. The multi-lot verification process determines if all wafers in the partial lots have completed the process step; determines if any wafers in the partial lots are on hold; and determining if all wafers in the partial lots are in a same material carrier.

Abstract: In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure.