Abstract: Methods, apparatuses and devices related to the manufacturing of compensation devices are provided. In some cases, an n/p-codoped layer is deposited for calibration purposes to minimize a net doping concentration. In other cases, alternatingly n- and p-doped layers are then deposited. In other embodiments, an n/p-codoped layer is deposited in a trench where n- and p-dopants have different diffusion behavior. To obtain different doping profiles, a heat treatment may be performed.

Abstract: The defect-containing die identified from an inspection layer analysis subsequent to a manufacturing step for a wafer including a plurality of die and as well as the faulty die identified from a fault testing of the wafer are processed to identify a subset of the die that both contain a defect and are faulty. A probability analysis is performed to determine a confidence level of whether the die in the subset are faulty due to their defects.

Abstract: Provided is a semiconductor device that suppresses the occurrence of defects due to photocorrosion. A method for manufacturing the semiconductor device includes the steps of: forming an insulating layer with a concave portion over a substrate; forming a conductive film over the insulating film and the inside of the concave portion; polishing and removing the conductive film positioned over the insulating layer; and cleaning the insulating layer in a light-shielded state. Between the step of polishing and the step of cleaning, or after the step of cleaning, the substrate SUB is moved by detecting the presence or absence of the substrate SUB in the light-shielded state using an infrared sensor.

Abstract: The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).

Abstract: Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems are disclosed. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.

Abstract: Device structures, fabrication methods, and design structures for a biological and chemical sensor used to detect a property of a substance. The device structure includes a drain and a source of a field effect transistor formed at a frontside of a substrate. A sensing layer is formed at a backside of the substrate. The sensing layer is configured to receive the substance.

Abstract: The present invention discloses a transistor, the preparation method thereof, and a display panel. The transistor comprises: a gate electrode; a gate insulating layer covering the gate electrode; an oxide semiconductor layer formed on the gate insulating layer; a first protective layer formed on the oxide semiconductor layer; a source/drain electrode connected with the oxide semiconductor layer; and a second protective layer covering the source/drain electrode; wherein, the hydrogen atom content per unit volume of the first protective layer is less than that of the gate insulating layer, and the hydrogen atom content per unit volume of the gate insulating layer is less than that of the second protective layer. Through the above solutions, the present invention can suppress the combination of the oxygen atom of the semiconductor layer in the transistor and the external hydrogen atom, to improve the performance and stability of the device.

Abstract: A deposition apparatus includes: a transfer unit including a first transfer unit and a second transfer unit, wherein the first transfer unit transfers, in a first direction, a moving unit to which a substrate is detachably fixed, and the second transfer unit transfers, in an opposite direction of the first direction, the moving unit from which the substrate is separated, and a deposition unit including a deposition assembly wherein the deposition assembly deposits a material on the substrate spaced apart from the deposition assembly while the first transfer unit transfers the substrate which is fixed to the moving unit, wherein the first transfer unit includes a first support unit that supports both ends of the moving unit in the first direction, and a second support unit that supports a side of the moving unit opposite to a side close to the deposition assembly.

Abstract: Indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers. Each die is obtained in a respective position of the wafer. A manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession. The method may include providing a die index on each die which is indicative of the position of the respective die by forming an external index indicative of the position of the superficial portion of the material wafer corresponding to the subset of the plurality of dies including said die and may comprise a plurality of electronic components electrically coupled to each other by means of a respective common control line.

Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.

Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the subregion (208).

Abstract: A method for manufacturing a solar cell capable of significantly reducing the amount of wastewater generated during a wet-etching process and improving the efficiency of the solar cell. A method comprising: texturing to form an uneven structure on one semiconductor substrate surface by etching the semiconductor substrate surface with a texturing device; forming a temporary layer at an upper portion of the semiconductor substrate surface to surround a first byproduct layer formed at a predetermined region of the semiconductor substrate surface during the texturing; and doping the semiconductor substrate surface with a predetermined dopant using a doping device to form a first semiconductor layer and a second semiconductor layer disposed above the first semiconductor layer and having a different polarity than the first semiconductor layer. The first byproduct layer and the temporary layer are simultaneously removed.

Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.

Abstract: An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact.

Abstract: The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an electrically-insulating adhesive which couples the packages. A pressure generator and a variable frequency microwave source are coupled to a process chamber which encapsulates a package-on-package semiconductor structure. The package-on-package semiconductor structure is simultaneously heated by the variable frequency microwave source at variable frequency, variable temperature, and variable duration and exposed to an elevated pressure by the pressure generator. This combination for microwave heating and elevated pressure limits the amount of warpage introduced while preventing void formation within an electrically-insulating adhesive which couples the substrates of the package-on-package semiconductor structure.

Abstract: At the time of transporting a substrate into or from a space where a film formation process is performed, the space where the film formation process is performed, a space where a lower heater 16 is provided, and a space where an upper heater 19 is provided are made in an inert gas atmosphere.

Abstract: By determining at least one surface characteristic of a passivation layer stack used for forming a bump structure, the situation after the deposition and patterning of a terminal metal layer stack may be “simulated,” thereby providing the potential for using well-established bump manufacturing techniques while nevertheless significantly reducing process complexity by omitting the deposition and patterning of the terminal metal layer stack.

Abstract: A coating film (90) is formed by causing vapor deposition particles (91) discharged from a vapor deposition source opening (61) of a vapor deposition source (60) to pass through a space (82) between a plurality of limiting plates (81) of a limiting plate unit (80) and a mask opening (71) of a vapor deposition mask in this order and adhere to a substrate while the substrate is moved relative to the vapor deposition mask in a state in which the substrate (10) and the vapor deposition mask (70) are spaced apart at a fixed interval. It is determined whether or not it is necessary to correct the position of at least one of the plurality of limiting plates in the X axis direction, and in the case where it is necessary to correct the position, the position of at least one of the plurality of limiting plates in the X axis direction is corrected. Accordingly, a coating film whose edge blur is suppressed can be stably formed at a desired position on a large-sized substrate.

Abstract: A method is provided for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. A plurality of locations are defined about a periphery of the semiconductor wafer, and one or more properties, such as oxygen concentration and a density of bulk micro defects present, are measured at each of the plurality of locations. A statistical profile associated with the periphery of the semiconductor wafer is determined based on the one or more properties measured at the plurality of locations. The semiconductor wafer is subsequently thermally treated when the statistical profile falls within a predetermined range. The semiconductor wafer is rejected from subsequent processing when the statistical profile deviates from the predetermined range. As such, wafers prone to distortion, warpage, and breakage are rejected from subsequent thermal processing.

Abstract: A method of forming an epitaxial SiC film on SiC substrates in a warm wall CVD system, wherein the susceptor is actively heated and the ceiling and sidewall are not actively heated, but are allowed to be indirectly heated by the susceptor. The method includes a first process of reaction cell preparation and a second process of epitaxial film growth. The epitaxial growth is performed by flowing parallel to the surface of the wafers a gas mixture of hydrogen, silicon and carbon gases, at total gas velocity in a range 120 to 250 cm/sec.

Abstract: The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters.

Abstract: A method and apparatus for solvent annealing a layered substrate including a layer of a block copolymer are provided. The method includes (a) introducing an annealing gas into a processing chamber; (b) maintaining the annealing gas in the processing chamber for a first time period; (c) removing the annealing gas from the processing chamber; and (d) repeating steps (a)-(c) a plurality of times in order induce the block copolymer to undergo cyclic self-assembly. The apparatus includes a processing chamber comprising a process space; a substrate support in the process space; an annealing gas supply and a purge gas supply, both in fluid communication with the process space; a heating element positioned within the processing chamber; an exhaust port in the processing chamber; and a sequencing device programmed to control the annealing gas supply, the heating element, the isolation valve of the exhaust port, and the purge gas supply.

Abstract: Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.

Abstract: A microelectromechanical system, including a first element and a second element, the first element having a first conductive surface facing a second conductive surface of the second element; wherein at least one of the first element and the second element is operable to constrainedly move nearer and farther from the other element; and at least one insulating separating member which is operable to mechanically maintain a separation between the first surface and the second surface, wherein a minimal distance between a first projection of a first contact area of the insulating separating member and a second projection of a second contact area of the insulating separating member is larger than a minimal separation maintained by the insulating separating member between the first element and the second element.

Abstract: One or more integrated circuit structures and techniques for forming such integrated circuit structures are provided. The integrated circuit structures comprise a conductive structure that is formed within a trench in a dielectric layer on a substrate. The conductive structure is formed over a barrier layer formed within the trench, or the conductive structure is formed over a liner formed over the barrier layer. At least some of the dielectric layer, the barrier layer, the liner and the conductive structure are removed, for example, by chemical mechanical polishing, such that a step height exists between a top surface of the substrate and a top surface of the dielectric layer. Removing these layers in this manner removes areas where undesired interlayer peeling is likely to occur. A conductive cap is formed on the conductive structure.

Abstract: A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

Abstract: There is provided an etching method. A temperature at a plurality of predetermined positions on an upper surface of an Si substrate is measured during the etching processing. The etching processing includes supplying an etching solution to the upper surface of the Si substrate. An exothermic reaction occurs in the etching processing. The upper surface is heated or cooled depending on the measured value.

Abstract: A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit.

Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.

Abstract: A method for placing a component on a target platform includes providing component alignment marks, target platform reference marks, a first multiple-sensor probe including first sensors, and a second multiple-sensor probe including third sensors. The method further includes determining second sensors included in the first sensors, and sensing a first signal from a first one of the alignment marks by at least one of the second sensors. The method further includes determining fourth sensors included in the third sensors. The method further includes sensing a second signal from a second one of the alignment marks by at least one of the fourth sensors, and detecting a deviation of the component from the target platform associated with a first position of one of the second sensors that sense the first signal and a second position of one of the fourth sensors that sense the second signal.

Abstract: According to one embodiment, a step difference estimation unit, an assist pattern generation unit, and a spherical aberration conversion unit are installed. The step difference estimation unit estimates step difference of a processing layer. The assist pattern generation unit adds an assist pattern having different sensitivity to spherical aberration in an exposure process to a mask pattern based on the step difference of the processing layer. The spherical aberration conversion unit converts the step difference of the processing layer into the spherical aberration.

Abstract: A substrate holder positioning method, capable of positioning a substrate holder without using any positioning jig, includes: measuring a first position of a substrate held on a substrate holder included in a substrate carrying mechanism; carrying the substrate held on the substrate holder to a substrate rotating unit for holding and rotating the substrate; turning the substrate held by the substrate rotating unit through a predetermined angle by the substrate rotating unit; transferring the substrate turned by the substrate rotating unit from the substrate rotating unit to the substrate holder; measuring a second position of the substrate transferred from the substrate rotating unit to the substrate holder; determining the position of the center of rotation of the substrate rotating unit on the basis of the first and the second position; and positioning the substrate holder on the basis of the position of the center of rotation.

Abstract: A phase change random access memory includes a semiconductor substrate having a bottom electrode formed over the semiconductor substrate; and a phase change layer formed over the bottom electrode. The phase change layer a first phase change layer formed over the bottom electrode and including at least one of a first element, a second element, and a third element; and a second phase change layer formed over a surface of the first phase change layer and formed of the first element to prevent an area of the first phase change layer from increasing through diffusion.

Abstract: Embodiments of the present invention provide apparatus and method for reducing non uniformity during thermal processing. One embodiment provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to rotate the substrate, a sensor assembly configured to measure temperature of the substrate at a plurality of locations, and one or more pulse heating elements configured to provide pulsed energy towards the processing volume.

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

Abstract: Photolithographic methods of forming a roughened surface for an LED to improve LED light emission efficiency are disclosed. The methods include photolithographically imaging a phase-shift mask pattern onto a photoresist layer of a substrate to form therein a periodic array of photoresist features. The roughened substrate surface is created by processing the exposed photoresist layer to form a periodic array of substrate posts in the substrate surface. A p-n junction multilayer structure is then formed atop the roughened substrate surface to form the LED. The periodic array of substrate posts serve as scatter sites that improve the LED light emission efficiency as compared to the LED having no roughened substrate surface. The use of the phase-shift mask enables the use of affordable photolithographic imaging at a depth of focus suitable for non-flat LED substrates while also providing the needed resolution to form the substrate posts.

Abstract: Embodiments of the present disclosure generally provide apparatus and method for improving processing uniformity by reducing external magnetic noises. One embodiment of the present disclosure provides an apparatus for processing semiconductor substrates. The apparatus includes a chamber body defining a vacuum volume for processing one or more substrate therein, and a shield assembly for shielding magnetic flux from the chamber body disposed outside the chamber body, wherein the shield assembly comprises a bottom plate disposed between the chamber body and the ground to shield magnetic flux from the earth.

Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

Abstract: A flash heating part in a heat treatment apparatus includes 30 built-in flash lamps, and irradiates a semiconductor wafer held by a holder in a chamber with a flash of light. Thirty switching elements are provided in a one-to-one correspondence with the 30 flash lamps. Each of the switching elements defines the waveform of current flowing through a corresponding one of the flash lamps by intermittently supplying electrical charge thereto. Radiation thermometers measure an in-plane temperature distribution of the semiconductor wafer during flash irradiation. Based on the results of measurement with the radiation thermometers, a controller individually controls the operations of the 30 switching elements to individually define the light emission patterns of the 30 flash lamps.

Abstract: A substrate processing method which is capable of enhancing productivity in manufacturing product substrates. In process chambers of an etching apparatus, etching is carried out on a substrate as an object to be processed, and dummy processing is carried out on at least one non-product substrate before execution of the etching. A host computer determines whether or not the dummy processing is to be executed. The host computer determines whether or not the interior of each of the process chambers and is in a stable state, and omits the execution of the dummy processing when it is determined that it is in the stable state.

Abstract: Provided is a method for creating a mask blank that includes a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detection of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer.

Abstract: In one embodiment, a substrate processing apparatus includes a chamber having an interior volume with an upper portion and a lower portion, a cooling source disposed in the upper portion of the interior volume, a heating source opposing the cooling source, a magnetically movable substrate support that moves between the upper portion and the lower the portion, and a plurality of sensors coupled to the chamber to detect the position of the substrate support relative to the heating source and the cooling source

Abstract: A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome. Vacuum is maintained in the process chamber during processing. The upper dome is thermally controlled by flowing a thermal control fluid along the upper dome outside the processing region. Thermal lamps are positioned proximate the lower dome, and thermal sensors are disposed among the lamps. The lamps are powered in zones, and a controller adjusts power to the lamp zones based on data received from the thermal sensors.

Abstract: Disclosed is a process tunnel (102) through which substrates (140) may be transported in a floating condition between two gas bearings (124, 134). To monitor the transport of the substrates through the process tunnel, the upper and lower walls (120, 130) of the tunnel are fitted with at least one substrate detection sensor (S1, . . . , S6) at a respective substrate detection sensor location, said substrate detection sensor being configured to generate a reference signal reflecting a presence of a substrate between said first and second walls near and/or at said substrate detection sensor location. Also provided is a monitoring and control unit (160) that is operably connected to the at least one substrate detection sensor (S1, . . . , S6), and that is configured to record said reference signal as a function of time and to process said reference signal.

Abstract: A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.

Abstract: A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome. Vacuum is maintained in the process chamber during processing. The upper dome is thermally controlled by flowing a thermal control fluid along the upper dome outside the processing region. Thermal lamps are positioned proximate the lower dome, and thermal sensors are disposed among the lamps. The lamps are powered in zones, and a controller adjusts power to the lamp zones based on data received from the thermal sensors.

Abstract: Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.

Abstract: In vapour deposition applications, especially OLED mass production, where it is necessary to measure and/or control the deposition rate of evaporation sources within specific tolerances, a measurement system is adapted to use robust and accurate optical thickness measurement methods at high and low rate sources, so that the thickness of a layer deposited on a substrate can be measured and controlled. A first evaporation source (11) deposits a layer of material on a substrate (20). A mobile element (41) is provided, On which a film is deposited from a second evaporation source (12b) in a deposition location (D1). Subsequently the mobile element is conveyed to a measurement location (D2) where the thickness of the film is measured by a thickness detector (45). The measurement apparatus is arranged to control the deposition of the first evaporation source in dependence on the thickness of the film deposited on the mobile element.

Abstract: An organic light emitting display, a method for driving the same, and a method for manufacturing the same are discussed. The organic light emitting display according to an embodiment includes a panel including subpixels each having a compensation circuit including a reference voltage supply transistor, which receives a reference voltage and initializes a node of a gate electrode of a driving transistor using the reference voltage, a scan driver supplying a scan signal to scan lines of the panel, a data driver supplying a data signal to data lines of the panel, a timing controller controlling the scan driver and the data driver, and a reference voltage compensation unit which varies the reference voltage on each scan line and supplies the reference voltage to the subpixels.

Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.