Abstract: In a method for growing a p-type SiC semiconductor single crystal on a SiC single crystal substrate, using a first solution in which C is dissolved in a melt of Si, a second solution is prepared by adding Al and N to the first solution such that an amount of Al added is larger than that of N added, and the p-type SiC semiconductor single crystal is grown on the SiC single crystal substrate from the second solution. A p-type SiC semiconductor single crystal is provided which is grown by the method as described above, and which contains 1×1020 cm?3 of Al and 2×1018 to 7×1018 cm?3 of N as impurities.

Abstract: Disclosed is a producing method of a semiconductor device, including: loading a silicon substrate into a processing chamber, the silicon substrate having a silicon nitride film or a silicon oxide film on at least a portion of a surface thereof and a silicon surface being exposed from the surface; and alternately repeating a first introducing at least a silane-compound gas into the processing chamber and a second introducing at least etching gas a plurality of times to selectively grow an epitaxial film on the silicon surface, wherein the alternate repeating is started with the second introducing prior to the first introducing.

Abstract: A method for fabricating quantum wells by using indium gallium nitride (InGaN) semiconductor material includes fabricating a potential well on a layered group III-V nitride structure at a first predetermined temperature in a reactor chamber by injecting into the reactor chamber an In precursor gas and a Ga precursor gas. The method further includes, subsequent to the fabrication of the potential well, terminating the Ga precursor gas, maintaining a flow of the In precursor gas, and increasing the temperature in the reactor chamber to a second predetermined temperature while adjusting the In precursor gas flow rate from a first to a second flow rate. In addition, the method includes annealing and stabilizing the potential well at the second predetermined temperature while maintaining the second flow rate. The method also includes fabricating a potential barrier above the potential well at the second predetermined temperature while resuming the Ga precursor gas.

Abstract: On a substrate, a silicon carbide layer provided with a main surface is formed. A mask is formed to cover a portion of the main surface of the silicon carbide layer. The main surface of the silicon carbide layer on which the mask is formed is thermally etched using chlorine-based gas so as to provide the silicon carbide layer with a side surface inclined relative to the main surface. The step of thermally etching is performed in an atmosphere in which the chlorine-based gas has a partial pressure of 50% or smaller.

Abstract: High temperature semiconducting materials in a freestanding epitaxial chip enables the use of high temperature interconnect and bonding materials. Process materials can be used which cure, fire, braze, or melt at temperatures greater than 400 degrees C. These include, but are not limited to, brazing alloys, laser welding, high-temperature ceramics and glasses. High temperature interconnect and bonding materials can additionally exhibit an index of refraction intermediate to that of the freestanding epitaxial chip and its surrounding matrix. High index, low melting point glasses provide a hermetic seal of the semiconductor device and also index match the freestanding epitaxial chip thereby increasing extraction efficiency. In this manner, a variety of organic free semiconducting devices, such as solid-sate lighting sources, can be created which exhibit superior life, efficiency, and environmental stability.

Abstract: Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.

Abstract: To provide a method for manufacturing a nitride semiconductor substrate capable of reducing a cleavage during slicing of a nitride semiconductor single crystal, and capable of improving a yield rate of the nitride semiconductor substrate, comprising: growing a nitride semiconductor single crystal on a seed crystal substrate by vapor phase epitaxy; grinding an outer peripheral surface of the grown nitride semiconductor single crystal; and slicing the nitride semiconductor single crystal with its outer peripheral surface ground, wherein a grinding amount of the outer peripheral surface of the nitride semiconductor single crystal in the step of grinding is 1.5 mm or more.

Abstract: Provided are a crystalline film in which variations in the crystal axis angle after separation from a substrate for epitaxial growth have been eliminated, and various devices in which the properties thereof have been improved by including the crystalline film. And the crystalline film has a thickness of 300 ?m or more and 10 mm or less and reformed region pattern is formed in an internal portion of the crystalline film.

Abstract: Provided are a semiconductor layer manufacturing method and a semiconductor manufacturing apparatus capable of forming a high quality semiconductor layer even by a single chamber system, with a shortened process time required for reducing a concentration of impurities that exist in a reaction chamber before forming the semiconductor layer. A semiconductor device manufactured using such a method and apparatus is also provided.

Abstract: A substrate processing apparatus having a processing chamber for processing a substrate; a processing gas feeding line for feeding a processing gas into the processing chamber; an inert gas feeding line for feeding an inert gas into the processing chamber; an inert gas vent line provided in the inert gas feeding line, for exhausting the inert gas fed into the inert gas feeding line without feeding the inert gas into the processing chamber; a first valve provided in the inert gas feeding line, on a downstream side of a part where the inert gas vent line is provided in the inert gas feeding line; a second valve provided in the inert gas vent line; and an exhaust line that exhausts an inside of the processing chamber.

Abstract: Methods for selectively depositing high quality epitaxial material include introducing pulses of a silicon-source containing vapor while maintaining a continuous etchant flow. Epitaxial material is deposited on areas of a substrate, such as source and drain recesses. Between pulses, the etchant flow continues such that lower quality epitaxial material may be removed, as well as any non-epitaxial material that may have been deposited. The pulse of silicon-source containing vapor may be repeated until a desired thickness of epitaxial material is selectively achieved in semiconductor windows, such as recessed source/drain regions.

Abstract: A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, the apparatus a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. In one embodiment, the showerhead includes one or more cleaning gas conduits configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. In one embodiment, the showerhead includes a plurality of metrology ports configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. As a result, the processing chamber components can be cleaned more efficiently and effectively than by introducing cleaning gas into the chamber only through the processing gas channels.

Abstract: A method for manufacturing a microcrystalline semiconductor film having high crystallinity is provided. A method for manufacturing a semiconductor device which has favorable electric characteristics with high productivity is provided. After a first microcrystalline semiconductor film is formed over a substrate, treatment for flattening a surface of the first microcrystalline semiconductor film is performed. Then, treatment for removing an amorphous semiconductor region on a surface side of the flattened first microcrystalline semiconductor film is performed so that a second microcrystalline semiconductor film having high crystallinity and flatness is formed. After that, a third microcrystalline semiconductor film is formed over the second microcrystalline semiconductor film.

Abstract: A method for producing quantum dots embedded in a matrix on a substrate includes the steps of: depositing a precursor on the substrate, the precursor including at least one first metal or a metal compound; contacting the deposited precursor and uncovered areas of the substrate with a gas-phase reagent including at least one second metal and/or a chalcogen; and initiating a chemical reaction between the precursor and the reagent by raising a temperature thereof simultaneously with or subsequent to the contacting so that the matrix consists exclusively of elements of the reagent.

Abstract: Surface passivation techniques for chamber-split processing are described. A method includes forming a first Group III-V material layer above a substrate, the first Group III-V material layer having a top surface. A passivation layer is deposited on the top surface of the Group III-V material layer. The passivation layer is removed. Subsequently, a second Group III-V material layer is formed above the first Group III-V material layer.

Abstract: Method for forming a semi-conducting structure includes the formation of at least one part of a circuit or a component, in or on a superficial layer of a substrate, the substrate including a buried layer underneath the superficial layer, and an underlying layer serving as first support, a transfer of said substrate onto a handle substrate, and then an elimination of the first support, the formation of an electrically conducting or ground plane forming layer, on at least one part of said buried layer, the formation, on said electrically conducting or ground plane forming layer, of a bonding layer, a transfer of the structure obtained onto a second support and an elimination of said handle substrate.

Abstract: A substrate including a host and a seed layer bonded to the host is provided, then a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. In some embodiments, a bonding layer bonds the host to the seed layer. The seed layer may be thinner than a critical thickness for relaxation of strain in the semiconductor structure, such that strain in the semiconductor structure is relieved by dislocations formed in the seed layer, or by gliding between the seed layer and the bonding layer an interface between the two layers. In some embodiments, the host may be separated from the semiconductor structure and seed layer by etching away the bonding layer.

Abstract: A method for fabricating a semiconductor device includes forming an AlN layer on a substrate made of silicon by supplying an Al source without supplying a N source and then supplying both the Al source and the N source, and forming a GaN-based semiconductor layer on the AlN layer after the forming of the AlN layer. The forming of the AlN layer grows the AlN layer so as to satisfy the following: 76500/x0.81<y<53800/x0.83 where x is a thickness of the AlN layer and y is an FWHM of a rocking curve of a (002) plane of the AlN layer.

Abstract: There is provided a film formation apparatus which is capable of forming an EL layer using an EL material with high purity. The EL material is purified by sublimation immediately before film formation in the film formation apparatus, to thereby remove oxygen, water, and another impurity, which are included in the EL material. Also, when film formation is performed using the EL material (high purity EL material) obtained by purifying with sublimation as an evaporation source, a high purity EL layer can be formed.

Abstract: Epitaxial layers are selectively formed in semiconductor windows by a cyclical process of repeated blanket deposition and selective etching. The blanket deposition phases leave non-epitaxial material over insulating regions, such as field oxide, and the selective etch phases preferentially remove non-epitaxial material while deposited epitaxial material builds up cycle-by-cycle. Quality of the epitaxial material improves relative to selective processes where no deposition occurs on insulators. Use of a germanium catalyst during the etch phases of the process aid etch rates and facilitate economical maintenance of isothermal and/or isobaric conditions throughout the cycles. Throughput and quality are improved by use of trisilane, formation of amorphous material over the insulating regions and minimizing the thickness ratio of amorphous:epitaxial material in each deposition phase.

Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: growing a p-type gallium nitride-based compound semiconductor layer by performing a metalorganic chemical vapor deposition process in a heated atmosphere so that the crystal-growing plane of the semiconductor layer is an m plane (Step S13); and cooling the p-type gallium nitride-based compound semiconductor layer (Step S14) after the step of growing has been carried out. The step of growing includes supplying hydrogen gas to a reaction chamber in which the p-type gallium nitride-based compound semiconductor layer is grown. The step of cooling includes cooling the p-type gallium nitride-based compound semiconductor layer with the supply of the hydrogen gas to the reaction chamber cut off.

Abstract: Exemplary embodiments provide methods of forming semiconductor devices, by which defects formed upon nucleation and coalescence of semiconductor islands can be reduced or eliminated. In one embodiment, an annealing process can be performed prior to coalescence of the semiconductor islands into a continuous semiconductor layer. In another embodiment, high-quality Group III-V materials can be formed on the continuous semiconductor layer.

Abstract: A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface between the SiC substrate and the gate insulating film, some of elements of both of or one of Si and C in an outermost surface of the SiC substrate are replaced with at least one type of element selected from nitrogen, phosphorus, and arsenic.

Abstract: Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.

Abstract: This disclosure relates to the synthesis of Er doped GaN epilayers by in-situ doping by metal-organic chemical vapor deposition (MOCVD). In an embodiment, both above and below bandgap excitation results in a sharp PL emission peak at 1.54 ?m. Contrary with other growth methods, MOCVD grown Er-doped GaN epilayers exhibit virtually no visible emission lines, an present a small thermal quenching effect. The Er incorporation has very little effect on the electrical conductivity of the GaN epilayers and Er doped layers retain similar electrical properties as those of undoped GaN.

Abstract: A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.

Abstract: A method for producing a silicon wafer for epitaxial substrate which includes a first step of performing thermal oxidization on a silicon wafer containing boron atoms no less than 1E19 atoms/cm3, thereby forming a silicon oxide film on the surface of the silicon wafer, a second step of peeling off the silicon oxide film, and a third step of performing heat treatment on the silicon wafer in a hydrogen atmosphere.

Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.

Abstract: To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.

Abstract: A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.

Abstract: A method for forming a microcrystalline semiconductor film over a base formed of a different material, which has high crystallinity in the entire film and at an interface with the base, is proposed. Further, a method for manufacturing a thin film transistor including a microcrystalline semiconductor film with high crystallinity is proposed. Furthermore, a method for manufacturing a photoelectric conversion device including a microcrystalline semiconductor film with high crystallinity is proposed. By forming crystal nuclei with high density and high crystallinity over a base film and then growing crystals in a semiconductor from the crystal nuclei, a microcrystalline semiconductor film which has high crystallinity at an interface with the base film, which has high crystallinity in crystal grains, and which has high adhesion between the adjacent crystal grains is formed.

Abstract: The present invention generally provides apparatus and methods for forming LED structures. One embodiment of the present invention provides a method for fabricating a compound nitride structure comprising forming a first layer comprising a first group-III element and nitrogen on substrates in a first processing chamber by a hydride vapor phase epitaxial (HVPE) process or a metal organic chemical vapor deposition (MOCVD) process, forming a second layer comprising a second group-III element and nitrogen over the first layer in a second processing chamber by a MOCVD process, and forming a third layer comprising a third group-III element and nitrogen over the second layer by a MOCVD process.

Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.

Abstract: The present invention provides methods for fabricating a copper indium diselenide semiconductor film. The method includes providing a plurality of substrates having a copper and indium composite structure, and including a peripheral region, the peripheral region including a plurality of openings, the plurality of openings including at least a first opening and a second opening. The method includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the furnace including a holding apparatus. The method further includes introducing a gaseous species into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature to at least initiate formation of a copper indium diselenide film on each of the substrates.

Abstract: A method for forming a quantum well structure that can reduce the variation in the In composition in the thickness direction of a well layer and a method for manufacturing a semiconductor light emitting element are provided. In a step of forming a quantum well structure (active layer) by alternately growing barrier layers and well layers on a primary surface of a GaN substrate, the well layers are each formed by growing InGaN, the barrier layers are each grown at a first temperature, the well layers are each grown at a second temperature which is lower than that of the first temperature, and when the well layers are each formed, before a starting material gas for Ga (trimethylgallium) is supplied, a starting material gas for In is supplied.

Abstract: Methods form epitaxial materials by forming at least two gate stacks on a silicon substrate and forming sidewall spacers on sides of the gate stacks. Such methods pattern a recess in the silicon substrate between adjacent ones of the gate stacks. The methods also provide a liner in a bottom of the recess, and epitaxially grow epitaxial material from sidewalls of the recess to fill the recess with the epitaxial material.

Abstract: A gate insulating film (13) is formed on a substrate (1) so as to cover a gate electrode (11), and an amorphous silicon film (semiconductor thin film) (15) is further formed. A light absorption layer (19) is formed thereon through a buffer layer (17). Energy lines Lh are applied to the light absorption layer (19) from a continuous-wave laser such as a semiconductor laser. This oxidizes only a surface side of the light absorption layer Lh and produces a beautiful crystalline silicon film (15a) obtained by crystallizing the amorphous silicon film (15) using heat generated by thermal conversion of the energy lines Lh at the light absorption layer (19) and heat of the oxidation reaction. This provides a method for crystallizing a thin film with good controllability at low costs achieved with simpler process.

Abstract: A method includes an act of providing a crystalline substrate with a diamond-type lattice and an exposed substantially (111)-surface. The method also includes an act of forming a graphene layer or a graphene-like layer on the exposed substantially (111)-surface.

Abstract: A method for fabricating a semiconductor layer comprising: a) growing a semiconductor layer on a foreign substrate; b) forming at least one opening on the semiconductor layer, wherein the opening exposes the interface between the semiconductor layer and the foreign substrate; and c) removing at least part of the semiconductor solid state material along the interface between the semiconductor layer and the foreign substrate. The removing step c) is preferably achieved by selective interfacial chemical etching. The semiconductor layer may be utilized as a substrate for fabrication of a wide variety of electronic and opto-electronic devices and integrated circuitry products.

Abstract: The present invention provides silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the compounds. The compounds are defined by formula: SiHnI (GeHn2)y, wherein y is 2, 3, or 4 wherein n1 is 0 1, 2 or 3 to satisfy valency and wherein n2 is independently 0, 1, 2 or 3 for each Ge atom in the compound, to satisfy valency.

Abstract: A method for forming a quantum well structure that can reduce the variation in the In composition in the thickness direction of a well layer and a method for manufacturing a semiconductor light emitting element are provided. In a step of forming a quantum well structure (active layer) by alternately growing barrier layers and well layers on a primary surface of a GaN substrate, the well layers are each formed by growing InGaN, the barrier layers are each grown at a first temperature, the well layers are each grown at a second temperature which is lower than that of the first temperature, and when the well layers are each formed, before a starting material gas for Ga (trimethylgallium) is supplied, a starting material gas for In is supplied.

Abstract: A semiconductor substrate fabrication method according to the first aspect of this invention is characterized by including a preparation step of preparing an underlying substrate, a stacking step of stacking, on the underlying substrate, at least two multilayered films each including a peeling layer and a semiconductor layer, and a separation step of separating the semiconductor layer.

Abstract: In a structure for crystalline material growth, there is provided a lower growth confinement layer and an upper growth confinement layer that is disposed above and vertically separated from the lower growth confinement layer. A lateral growth channel is provided between the upper and lower growth confinement layers, and is characterized by a height that is defined by the vertical separation between the upper and lower growth confinement layers. A growth seed is disposed at a site in the lateral growth channel for initiating crystalline material growth in the channel. A growth channel outlet is included for providing formed crystalline material from the growth channel. With this growth confinement structure, crystalline material can be grown from the growth seed to the lateral growth channel outlet.

Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±40 ?m to ±100 ?m. Since with that bow device fabrication by photolithography is challenging, reducing the bow to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the bow. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the bow.

Abstract: A technique for forming nanostructures including a definition of a charge pattern on a substrate and introduction of charged molecular scale sized building blocks (MSSBBs) to a region proximate the charge pattern so that the MSSBBs adhere to the charge pattern to form the feature.

Abstract: A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A nanostructure in another embodiment includes a substrate having an area with a nanofeature; and a nanowire extending from the nanofeature, the nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A method for forming a nanostructure is also presented. A method for reading and writing data is also presented. A method for preparing nanoparticles is also presented.

Abstract: A plasma processing apparatus, comprising: a reaction chamber; a plurality of discharge portions each made up of a pair of a first electrode and a second electrode disposed inside the reaction chamber so as to oppose to each other and to cause a plasma discharge under an atmosphere of a reactant gas; and a dummy electrode, wherein a plurality of the first electrodes are connected to a power supply portion, a plurality of the second electrodes are grounded, and the dummy electrode is disposed so as to oppose to an outer surface side of an external first electrode in terms of a parallel direction out of the plurality of the first electrodes which are disposed in the parallel direction, and is grounded.

Abstract: Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.

Abstract: A process for coating a substrate at atmospheric pressure is disclosed, the process comprising the steps of vaporizing a mass of semiconductor material within a heated inert gas stream to create a fluid mixture having a temperature above the condensation temperature of the semiconductor material, directing the fluid mixture at the substrate, the substrate having a temperature below the condensation temperature of the semiconductor material thereby depositing a layer of the semiconductor material onto a surface of the substrate, extracting undeposited semiconductor material; and circulating the undeposited semiconductor material into the fluid mixture having a temperature above the condensation temperature.