Abstract: The invention relates to a device for depositing one or more layers, in particular crystalline layers, on one or more substrates, in particular crystalline substrates (6), which are situated on a susceptor (3) in a process chamber (2) of a reactor (1). A process chamber wall (4) that can be actively heated by a process chamber heating unit (11) lies opposite the susceptor (3) that can be actively heated by the susceptor heating unit (11). The device is provided with a gas inlet organ (7) for introducing process gases into the process chamber and the process chamber heating unit (11) has a coolant channel (13) and is situated at a distance from the exterior (18) of the process chamber wall (4) during the active heating of the latter (4). The aim of the invention is to also allow the device to be used with hybrid technology.

Abstract: In a process of fabricating a nitride nitride semi-conductor layer of AlaGabIn(1-a-b)N (0<a<1, 0<b<1, 1?a?b>0), the AlGaInN layer is grown at a growth rate less than 0.09 ?m/h according to the metal organic vapor phase epitaxy (MOPVE) method. The AlGaInN layer fabricated by the process in the present invention exhibits a high quality with low defect, and increases internal quantum yield.

Abstract: A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface.

Abstract: The invention discloses a method of producing on a substrate a semiconductor optical device having a laser diode and an EA optical modulator. An etched side face of a first semiconductor portion is formed. Then, for example, a first optical confinement layer and an active layer both for the EA optical modulator are grown by the metal organic vapor phase epitaxy method. The first optical confinement layer is grown by supplying hydrogen chloride in addition to a material gas. When the first optical confinement layer is grown, the formation of a thick semiconductor layer along the etched side face, which is an abnormally grown semiconductor layer, is decreased. Subsequently, the active layer for the EA optical modulator is grown. This method can suppress the active layer for the EA optical modulator from bending caused by the abnormally grown semiconductor layer.

Abstract: An epitaxial wafer is provided capable of eliminating particles in a device process, particles being generated from a scratch in a boundary area between a rear surface and a chamfered surface of a wafer. The scratch in the boundary area between the rear surface and the chamfered surface is removed in a scratch removal process. Thus, no particles exist caused by a scratch, at a time of immersion in an etching solution in the device process, and thus a device yield is increased.

Abstract: A thick gallium nitride (GaN) film is formed on a LiAlO2 substrate through two stages. First, GaN nanorods are formed on the LiAlO2 substrate through chemical vapor deposition (CVD). Then the thick GaN film is formed through hydride vapor phase epitaxy (HVPE) by using the GaN nanorods as nucleus sites. In this way, a quantum confined stark effect (QCSE) becomes small and a problem of spreading lithium element into gaps in GaN on using the LiAlO2 substrate is mended.

Abstract: A method for fabricating a semiconductor device includes growing an AlN layer by MOVPE in which a nitrogen-source flow ratio at a far side from a substrate is set lower than that at a near side, the nitrogen-source flow ratio being a ratio of a flow rate of a nitrogen source to a total flow rate of growth gas; and growing a GaN-based semiconductor layer on the AlN layer by MOVPE.

Abstract: A method of growing a semi-polar nitride single crystal thin film. The method includes forming a semi-polar nitride single crystal base layer on an m-plane hexagonal system single crystal substrate, forming a dielectric pattern layer on the semi-polar nitride single crystal base layer, and growing the semi-polar nitride single crystal thin film on the semi-polar nitride single crystal base layer having the dielectric pattern layer in a lateral direction. The growing of the semi-polar nitride single crystal thin film in a lateral direction includes primarily growing the semi-polar nitride single crystal thin film in the lateral direction such that part of a growth plane on the semi-polar nitride single crystal base layer has an a-plane, and secondarily growing the semi-polar nitride single crystal thin film in the lateral direction such that sidewalls of the primarily grown semi-polar nitride single crystal thin film are combined to have a (11 22) plane.

Abstract: A pn junction type Group III nitride semiconductor light-emitting device 10 (11) of the present invention has a light-emitting layer 2 of multiple quantum well structure in which well layers 22 and barrier layers 21 including Group III nitride semiconductors are alternately stacked periodically between an n-type clad layer 105 and a p-type clad layer 107 which are formed on a crystal substrate and which include Group III nitride semiconductors, in which one end layer 21m of the light-emitting layer 2 is closest to and opposed to the n-type clad layer, and the other end layer 21n of the light-emitting layer 2 is closest to and opposed to the p-type clad layer, both the one and the other end layers are barrier layers, and the other end layer 21n is thicker than the barrier layer of the one end layer.

Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 ?2 0) plane or (1 ?1 0 0) plane.

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract: A semiconductor device includes a device isolation structure formed on a semiconductor substrate to define an active region. A first Si-based epitaxial pattern is formed over the active region corresponding to a bit line contact region and a portion of a gate region at both sides adjacent to the bit line contact region. A second Si-based epitaxial layer is formed over the semiconductor substrate which is stepped up on the first Si-based epitaxial pattern. A stepped gate pattern is formed over the stepped second Si-based epitaxial layer.

Abstract: To provide a manufacturing method for an epitaxial wafer that alleviates distortions on a back surface thereof due to sticking between a wafer and a susceptor, thereby preventing decrease in flatness thereof due to a lift pin. A manufacturing method for an epitaxial wafer according to the present invention includes: an oxide film forming step in which an oxide film is formed on a back surface thereof; an etching step in which a hydrophobic portion exposing a back surface of the semiconductor wafer is provided by partially removing the oxide film; a wafer placing step in which the semiconductor wafer is placed; and an epitaxial growth step in which an epitaxial layer is grown on a main surface of the semiconductor wafer; and the diameter of the lift pin installation circle provided on a circle on a bottom face of a susceptor is smaller than that of the hydrophobic portion.

Abstract: The method for producing a group III nitride semiconductor crystal of the invention comprises a step of preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing step includes growing the group III nitride semiconductor so as to extend in the +C-axis direction of the seed crystal. A group III-V nitride semiconductor crystal having high quality and a large-area non-polar plane can be obtained by the method.

Abstract: In a light or radiation detector manufacturing method and a light or radiation detector of this invention, when forming a semiconductor, the semiconductor is formed in a predetermined thickness on a dummy substrate by vapor deposition, subsequently the dummy substrate is replaced with a graphite substrate which is a supporting substrate, and the semiconductor continues to be formed on the graphite substrate by vapor deposition. The time when forming the semiconductor in the predetermined thickness on the dummy substrate by vapor deposition is an initial state, and a defective film inevitably to be formed is formed on the dummy substrate. Subsequently, a semiconductor not in the initial state is formed on the graphite substrate put as replacement. This realizes a detector having the semiconductor of higher quality than in the prior art. The semiconductor manufactured in this way is formed continuously at least in a direction of thickness.

Abstract: A process for coating a substrate at atmospheric pressure is disclosed, the process comprising the steps of vaporizing a mass of semiconductor material within a heated inert gas stream to create a fluid mixture having a temperature above the condensation temperature of the semiconductor material, directing the fluid mixture at the substrate, the substrate having a temperature below the condensation temperature of the semiconductor material thereby depositing a layer of the semiconductor material onto a surface of the substrate, extracting undeposited semiconductor material; and circulating the undeposited semiconductor material into the fluid mixture having a temperature above the condensation temperature.

Abstract: A semiconductor device manufacturing method comprises the steps of loading a substrate into a processing chamber, mounting the substrate on a support tool in the processing chamber, processing the substrate mounted on the support tool by supplying process gas into the processing chamber, purging the interior of the processing chamber after the substrate processing step, and unloading the processed substrate from the processing chamber after the step of purging the interior of the processing chamber, wherein in the step of purging the interior of the processing chamber, exhaust is performed toward above the substrate and toward below the substrate in the processing chamber, and the exhaust rate toward above the substrate is set larger than the exhaust rate toward below the substrate.

Abstract: The invention relates to nitride semiconductor component having a Group III nitride layer structure which is deposited on a substrate having a Group IV substrate surface made of a Group IV substrate material with a cubical crystal structure. The Group IV substrate surface has an elementary cell with C2 symmetry, but not with a higher rotational symmetry than C2 symmetry, when any surface reconstruction is ignored. The Group III nitride layer structure has a seeding layer of ternary or quaternary Al1-x-yInxGayN, where 0?x, y<1 and x+y?1, immediately adjacent to the Group IV substrate surface. High-quality monocrystalline growth is achieved as a result. The advantage of the invention consists in the high level of crystal quality that can be achieved, in the growth of c-, a- and m-plane GaN and above all in the ease with which the silicon substrate can be wholly or partially removed, since this is easier to do in a wet chemical process than on (111)-oriented substrates.

Abstract: A growth substrate is removed from a semiconductor film, and a surface of the semiconductor film exposed by removing the growth substrate is flattened. The semiconductor film along device division lines are partially etched by dry etching to form grooves in a lattice that form streets, not reaching the metal support in the semiconductor film. The surface of the semiconductor film at the bottom of the grooves is flattened. The semiconductor film along the device division lines at the bottom of the grooves are further etched by wet etching to expose the metal support at the bottom of the grooves to finish the streets.

Abstract: Methods in accordance with this invention form microelectronic structures, such as non-volatile memories, that include carbon layers, such as carbon nanotube (“CNT”) films, in a way that protects the CNT film against damage and short-circuiting. Microelectronic structures, such as non-volatile memories, in accordance with this invention are formed in accordance with such techniques.

Abstract: The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing sidewalls of the opening are lined with a second material, with monocrystalline material being exposed at a base of the second material-lined opening. A silicon-comprising layer is epitaxially grown from the exposed monocrystalline material within the second material-lined opening. At least a portion of the second material lining is in situ removed. Other aspects and implementations are contemplated.

Abstract: Methods and apparatuses for selective epitaxial formation of films separately inject reactive species into a CVD chamber. The methods are particularly useful for selective deposition using volatile combinations of precursors and etchants. Formation processes include simultaneous supply of precursors and etchants for selective deposition, or sequential supply for cyclical blanket deposition and selective etching. In either case, precursors and etchants are provided along separate flow paths that intersect in the relatively open reaction space, rather than in more confined upstream locations.

Abstract: A semiconductor structure includes a substrate which may be formed from a ZnS single crystal of wurtzite (2H) structure with a predetermined crystal orientation, and which has a first surface and a second surface. The structure includes a layer of a group III-nitride crystalline material deposited as an epitaxial layer on the first surface of the substrate. In one embodiment, the group III-nitride deposit is epitaxially grown using a MOCVD (or MOVPE) technique or a HVPE technique or a combination thereof. There may be a mask and/or a buffer layer on the first surface and/or a protective layer on the second surface.

Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.

Abstract: To provide a p-type semiconductor material having a band matching with a hole injection layer and suitable for an anode electrode that can be formed on a glass substrate or a polymer substrate, and to provide a semiconductor device. In the p-type semiconductor material, 1×1018 to 5×1020 cm?3 of Ag is contained in a compound containing Zn and Se, and the semiconductor device includes a substrate and a p-type electrode layer arranged on this substrate and having the aforementioned p-type semiconductor material.

Abstract: An apparatus for processing a substrate, comprising a processing chamber and a substrate support and lift pin assembly disposed within the chamber. The substrate support and lift pin assembly are coupled to a lift mechanism that controls positioning of the substrate support and the lift pins and provides rotation for the substrate support. The lift mechanism includes at least one sensor capable of generating a signal when clearance between the substrate support and the lift pins allows rotation of the substrate support to begin. The substrate support capable of concurrent axial motion and rotation may be used in a processing chamber comprising multiple processing zones separated by edge rings. Substrates may be subjected to successive or cyclical processes by moving between the multiple processing zones.

Abstract: A structure and method of forming same, comprising a low threading density alloy graded layer, deposited according to a deposition temperature profile in correspondence with increasing alloy composition. In one embodiment, a first substantially relaxed alloy graded layer is deposited while varying a deposition temperature according to a first temperature profile. A second substantially relaxed alloy graded layer is deposited over the first graded layer while varying a deposition temperature according to a second temperature profile. Preferably, the minimum signed rate of change of the second temperature profile is less than the maximum signed rate of change of the first temperature profile.

Abstract: The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.

Abstract: A vertical semiconductor element comprises: an electro-conductive substrate; a GaN layer, as a nitride compound semiconductor layer, which is selectively grown as a convex shape on one surface of the electro-conductive substrate through a buffer layer; a source electrode as a first electrode formed on the GaN layer; and a drain electrode as a second electrode formed on another surface of the electro-conductive substrate.

Abstract: Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration of the materials. The nanowires may be between 10 and 30 nm in diameter, formed using a comparable size particle of catalyst material. The nanowires may then be used as part of the channel of a field effect transistor, and the field effect transistor is itself characterized.

Abstract: A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.

Abstract: A method of growing a p-type nitride semiconductor material by molecular beam epitaxy (MBE) uses bis(cyclopentadienyl)magnesium (Cp2Mg) as the source of magnesium dopant atoms. Ammonia gas is used as the nitrogen precursor for the MBE growth process. To grow p-type GaN, for example, by the method of the invention, gallium, ammonia and Cp2Mg are supplied to an MBE growth chamber; to grow p-type AlGaN, aluminum is additionally supplied to the growth chamber. The growth process of the invention produces a p-type carrier concentration, as measured by room temperature Hall effect measurements, of up to 2 1017 cm?3, without the need for any post-growth step of activating the dopant atoms.

Abstract: The present invention provides a method for manufacturing a nitride semiconductor self-supporting substrate and a nitride semiconductor self-supporting substrate manufactured by this manufacturing method, the method including at least: a step of preparing a nitride semiconductor self-supporting substrate serving as a seed substrate; a step of epitaxially growing the same type of nitride semiconductor as the seed substrate on the seed substrate; and a step of slicing an epitaxially grown substrate subjected to the epitaxial growth into two pieces in parallel to an epitaxial growth surface. As a result, there is provided a method for manufacturing a large-diameter nitride semiconductor self-supporting substrate having an excellent crystal quality and small warp with good productivity at a low cost, etc.

Abstract: A method of manufacturing a semiconductor substrate includes a growing step of growing a second single crystalline semiconductor on a first single crystalline semiconductor, a blocking layer forming step of forming a blocking layer on the second single crystalline semiconductor, and a relaxing step of generating crystal defects at a portion deeper than the blocking layer to relax a stress acting on the second single crystalline semiconductor. The blocking layer includes, e.g., a porous layer, and prevents the crystal defects at the portion deeper than the blocking layer from propagating to the surface of the second single crystalline semiconductor.

Abstract: Embodiments of the invention generally relate to a chemical vapor deposition system and related method of use. In one embodiment, the system includes a reactor lid assembly having a body, a track assembly having a body and a guide path located along the body, and a heating assembly operable to heat the substrate as the substrate moves along the guide path. The body of the lid assembly and the body of the track assembly are coupled together to form a gap that is configured to receive a substrate. In another embodiment, a method of forming layers on a substrate using the chemical vapor deposition system includes introducing the substrate into a guide path, depositing a first layer on the substrate and depositing a second layer on the substrate, while the substrate moves along the guide path; and preventing mixing of gases between the first deposition step and the second deposition step.

Abstract: A strained germanium field effect transistor (FET) and method of fabricating the same is related to the strained Ge field effect transistor with a thin and pure Ge layer as a carrier channel. The pure Ge layer with the thickness between 1 nm and 10 nm is formed between an unstrained substrate and a gate insulation layer, and directly contacts with the unstrained substrate. The gate is disposed on the gate insulation layer. The germanium layer is used as a carrier transport channel of the strained Ge FET to improve the drive current and the carrier mobility, and to increase the devices performance effectively. Furthermore, a Si protective layer with extremely thin thickness can be deposed between and directly contacts with the gate insulation layer and the pure Ge layer.

Abstract: Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.

Abstract: Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles are disclosed. Carbon nanotube growth catalyst is applied on to a surface of a substrate. The substrate is subjected to a chemical vapor deposition of a carbon-containing gas to grow a non-woven fabric of carbon nanotubes. Portions of the non-woven fabric are selectively removed according to a defined pattern to create the article. A non-woven fabric of carbon nanotubes may be made by applying carbon nanotube growth catalyst on to a surface of a wafer substrate to create a dispersed monolayer of catalyst. The substrate is subjected to a chemical vapor deposition of a carbon-containing gas to grow a non-woven fabric of carbon nanotubes in contact and covering the surface of the wafer and in which the fabric is substantially uniform density.

Abstract: A device layer is formed on at least the upper surface of a prime wafer by an epitaxial growth method. Then, a protective film is formed to cover at least the device layer. The lower surface of the prime wafer is ground to have a flat lower surface.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and etching the CNT seeding layer, and selectively fabricating CNT material on the CNT seeding layer. Numerous other aspects are provided.

Abstract: A method utilizes HVPE to grow high quality flat and thick compound semiconductors (15) onto foreign substrates (10) using nanostructure compliant layers. Nanostructures (12) of semiconductor materials car be grown on foreign substrates (10) by molecular beam epitaxy (MBE), chemical vapour deposition (CVD), metalorganic chemical vapour deposition (MOCVD) and hydride vapour phase epitaxy (HVPE). Further growth of continuous compound semiconductor thick films (15) or wafer is achieved by epitaxial lateral overgrowth using HVPE.

Abstract: An aspect of the invention provides a method of manufacturing a method of manufacturing a semiconductor element comprises the steps of: growing epitaxially a semiconductor layer on top of a semiconductor substrate; forming a patterned portion of the grown semiconductor layer by forming a pattern by a patterning process on top of the grown semiconductor layer; removing a portion of the semiconductor layer other than the patterned portion by a first etching method with a first etchant; and immersing a resultant from the first etching method in a second etchant that etches only the semiconductor substrate by a second etching method thereby removing the substrate from the semiconductor layer.

Abstract: A method for depositing an epitaxial Ge—Sn layer on a substrate in a CVD reaction chamber includes introducing into the chamber a gaseous precursor comprising SnD4 under conditions whereby the epitaxial Ge—Sn layer is formed on the substrate. the gaseous precursor comprises SnD4 and high purity H2 of about 15-20% by volume. The gaseous precursor is introduced at a temperature in a range of about 250° C. to about 350° C. Using the process device-quality Sn—Ge materials with tunable bandgaps can be grown directly on Si substrates.

Abstract: Chemical vapor deposition processes utilize chemical precursors that allow for the deposition of thin films to be conducted at or near the mass transport limited regime. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, a higher order silane is employed to deposit thin films containing silicon that are useful in the semiconductor industry in various applications such as transistor gate electrodes.

Abstract: The invention relates to a manufacturing method of a semi-conductor on insulator substrate from an SOI substrate comprising a surface layer of silicon on an electrically insulating layer, called buried insulating layer, wherein a layer of Si1-xGex is formed on the superficial layer of silicon.

Abstract: A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a first portion adjacent the epitaxial layer and a second portion spaced apart from the first portion, wherein the amorphous silicon layer is formed on the insulation pattern at substantially the same rate at the first portion and at a second portion. The amorphous silicon layer may be formed to a uniform thickness without a thinning defect.

Abstract: A manufacturing method of a self separation layer includes the steps of: forming a plurality of convex portions on a substrate; growing a main material layer on the convex portions; and separating the main material layer from the substrate.

Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts not burying the facets, maintaining the convex facet hills on ? and the network concavities on excluding dislocations in the facet hills down to the outlining concavities on forming a defect accumulating region H on decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.

Abstract: In the method of fabricating an optical semiconductor device, a semiconductor layer is formed on an InP region, and includes semiconductor films. A first etching mask is formed on the semiconductor layer. The semiconductor layer is etched through the first etching mask to form a semiconductor mesa and a first marking mesa, each mesa includes an active layer and an InP cladding layer, the InP cladding layer being provided on the active layer. The active layer is made of semiconductor material different from InP. An InP burying region is grown through the first etching mask on a side of the semiconductor mesa and a side of the first marking mesa to bury the semiconductor mesa and the first marking mesa. A second etching mask is formed on the InP burying region after removing the first etching mask, and has an opening located above the first marking mesa. InP in the InP burying region and the first marking mesa is etched through the second etching mask to form a second marking mesa.

Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.