Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.

Abstract: According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet.

Abstract: An object of the present invention is to provide a nitride semiconductor device which shifts a luminescence wavelength toward a longer wavelength side without decreasing luminescence efficiency, and the nitride semiconductor device according to an implementation of the present invention includes: a GaN layer having a (0001) plane and a plane other than the (0001) plane; and an InGaN layer which contacts the GaN layer and includes indium, and the InGaN layer has a higher indium composition ratio in a portion that contacts the plane other than the (0001) plane than in a portion that contacts the (0001) plane.

Abstract: Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar III-nitride films initially grow vertically through openings in the dielectric mask before laterally overgrowing the mask in directions perpendicular to the vertical growth direction. Threading dislocations are reduced in the overgrown regions by (1) the mask blocking the propagation of dislocations vertically into the growing film and (2) the bending of dislocations through the transition from vertical to lateral growth.

Abstract: Methods of selective formation leave high quality epitaxial material using a repeated deposition and selective etch process. During the deposition process, an inert carrier gas is provided with a silicon-containing source without hydrogen carrier gas. After depositing silicon-containing material, an inert carrier gas is provided with an etchant to selectively etch deposited material without hydrogen. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is achieved. Using the processes described within, it is possible to maintain temperature and pressure conditions, as well as inert carrier gas flow rates, to provide for increased throughput. The inert flow can be constant, or etch rates can be increased by reducing inert flow for the etch phases of the cycles.

Abstract: Gas containing Si, gas containing C and gas containing Cl are introduced into a reacting furnace. SiC epitaxial film is grown on the surface of a 4H—SiC substrate by CVD in a gas atmosphere including raw material gas, additive gas, doping gas and carrier gas. The amount of the gas containing Cl relative to the gas containing Si in the gas atmosphere is reduced gradually. At the start of growth, the number of Cl atoms in the gas containing Cl is three times as large as the number of Si atoms in the gas containing Si. The number of Cl atoms in the gas containing Cl relative to the number of Si atoms in the gas containing Si in the gas atmosphere is reduced at a rate of 0.5%/min to 1.0%/min. The method grows silicon carbide semiconductor film at a high rate.

Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gas is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.

Abstract: A method for manufacturing a Group III nitride semiconductor of the present invention includes a sputtering step of forming a single-crystalline Group III nitride semiconductor on a substrate by a reactive sputtering method in a chamber in which a substrate and a Ga element-containing target are disposed, wherein said sputtering step includes respective substeps of: a first sputtering step of performing a film formation of the Group III nitride semiconductor while setting the temperature of the substrate to a temperature T1; and a second sputtering step of continuing the film formation of the Group III nitride semiconductor while lowering the temperature of the substrate to a temperature T2 which is lower than the temperature T1.

Abstract: The present disclosure involves a method of packaging a light-emitting diode (LED). According to the method, a group of metal pads and a group of LEDs are provided. The group of LEDs is attached to the group of metal pads, for example through a bonding process. After the LEDs are attached to the metal pads, each LED is spaced apart from adjacent LEDs. Also according to the method, a phosphor film is coated around the group of LEDs collectively. The phosphor film is coated on top and side surfaces of each LED and between adjacent LEDs. A dicing process is then performed to slice through portions of the phosphor film located between adjacent LEDs. The dicing process divides the group of LEDs into a plurality of individual phosphor-coated LEDs.

Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.

Abstract: Exemplary embodiments of the present invention relate to a single-crystal substrate including a buffer layer including a nitride semiconductor, holes penetrating the buffer layer, and a single-crystal nitride semiconductor disposed on the buffer layer.

Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.

Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.

Abstract: The method for fabricating a free-standing group III nitride plate (6) comprises the steps of: growing a first group III nitride layer (2) on a foreign growth substrate (1); treating the first group III nitride layer (2) so as to make it porous; growing at a growth temperature within a growth reactor (7) a second group III nitride layer (4) on the first group III nitride layer (2); and separating the second group III nitride layer (4) from the growth substrate (1) so as to form a free-standing group III nitride plate (6). According to the present invention, the step of separating the second group III nitride layer (4) from the growth substrate (6) is performed at the growth temperature and within a growth reactor (7), and comprises selective chemical etching of the porous first group III nitride layer (2).

Abstract: Techniques for crack-free growth of GaN, and related, films on larger-size substrates via spatially confined epitaxy are described.

Abstract: A process for supplying a mixed material gas that includes a chlorosilane gas and a carrier gas to a surface of a substrate heated at 1200 to 1400° C. from a direction perpendicular to the surface is provided. A supply rate of the chlorosilane gas is equal to or more than 200 ?mol per minute per 1 cm2 of the surface of the substrate. The carrier gas includes a hydrogen gas and at least one or more gases selected from argon, xenon, krypton and neon.

Abstract: A method for producing a group 3-5 nitride semiconductor includes the steps of (i), (ii), (iii) in this order: (i) placing inorganic particles on a substrate, (ii) epitaxially growing a semiconductor layer by using the inorganic particles as a mask, and (iii) separating the substrate and the semiconductor layer by irradiating the interface between the substrate and the semiconductor layer with light; and a method for producing a light emitting device further includes adding electrodes.

Abstract: A method of constructing a solid-state energy-density micro radioisotope power source device. In such embodiments, the method comprises depositing the pre-voltaic semiconductor composition, comprising a semiconductor material and a radioisotope material, into a micro chamber formed within a power source device body. The method additionally includes heating the body to a temperature at which the pre-voltaic semiconductor composition will liquefy within the micro chamber to provide a liquid state composite mixture. Furthermore, the method includes cooling the body and liquid state composite mixture such that liquid state composite mixture solidifies to provide a solid-state composite voltaic semiconductor, thereby providing a solid-state high energy-density micro radioisotope power source device.

Abstract: A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions. The amorphous alumina portions are removed and the remaining dense alumina portions which have an ordered lattice arrangement are employed as an etch mask. After removing the amorphous alumina portions, each dense alumina portion has a width which is also less than 10 nm.

Abstract: A method and apparatus that includes a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume is provided. The showerhead includes one or more cleaning gas conduits configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. The showerhead may include a plurality of metrology ports configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. As a result, the processing chamber components can be cleaned more efficiently and effectively than by introducing cleaning gas into the chamber only through the processing gas channels.

Abstract: A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T1 for a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature T2 below the annealing temperature T1 in the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.

Abstract: A method of introducing a bandgap in single layer graphite on a SiO2 substrate comprising the steps of preparing graphene flakes and CVD grown graphene films on a SiO2/Si substrate and performing hydrogenation of the graphene. Additionally, controlling the majority carrier type via surface adsorbates.

Abstract: A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.

Abstract: Exemplary embodiments of the present invention disclose a method of fabricating a gallium nitride (GaN) based semiconductor device. The method includes growing GaN based semiconductor layers on a first surface of a GaN substrate to form a semiconductor stack, and separating at least a first portion of the GaN substrate from the semiconductor stack using a wire cutting technique.

Abstract: A method of preparing GaN material includes subjecting a GaN substrate to at least two cycles of Ga deposition and desorption, then applying a layer of AlN to the GaN substrate, then growing GaN on the AlN layer by molecular beam epitaxy. This results in reduced concentrations of oxygen, carbon, and silicon impurities.

Abstract: Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon.

Abstract: A method of manufacturing a semiconductor layer with which inactivation of impurity is able to be inhibited by a simple method, a semiconductor layer in which inactivation of impurity is inhibited, a method of manufacturing a laser diode with which inactivation of impurity is able to be inhibited by a simple method, and a laser diode including a semiconductor layer in which inactivation of impurity is inhibited are provided. In the method of manufacturing a semiconductor layer, after a semiconductor layer is formed by epitaxial growth with the use of AsH3, supply of AsH3 is stopped without separately supplying new gas when process temperature is 500 deg C. or more.

Abstract: Method for depositing a layer on a surface of a substrate. The method comprises injecting a precursor gas from a precursor supply into a deposition cavity for contacting the substrate surface, draining part of the injected precursor gas from the deposition cavity, and positioning the deposition cavity and the substrate relative to each other along a plane of the substrate surface. The method further comprising providing a first electrode and a second electrode, positioning the first electrode and the substrate relative to each other, and generating a plasma discharge near the substrate for contacting the substrate by generating a high-voltage difference between the first electrode and the second electrode. The method comprises generating the plasma discharge selectively, for patterning the surface by means of the plasma. A portion of the substrate contacted by the precursor gas selectively overlaps with a portion of the substrate contacted by the plasma.

Abstract: A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium precursor gas is employed to deposit an epitaxial semiconductor alloy material including at least silicon and germanium on a single crystalline surface. The germanium precursor gas effectively reduces the gas phase reaction of the high order silane, thereby improving the thickness uniformity of the deposited epitaxial semiconductor alloy material. The combination of the high order silane and the germanium precursor gas provides a high deposition rate in the Frank-van der Merwe growth mode for deposition of a single crystalline semiconductor alloy material.

Abstract: Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.

Abstract: The purpose of the present invention is to provide a good ohmic contact for an n-type Group-III nitride semiconductor. An n-type GaN layer and a p-type GaN layer are aequentially formed on a lift-off layer (growth step). A p-side electrode is formed on the top face of the p-type GaN layer. A copper block is formed over the entire area of the top face through a cap metal. Then, the lift-off layer is removed by making a chemical treatment (lift-off step). Then, a laminate structure constituted by the n-type GaN layer, with which the surface of the N polar plane has been exposed, and the p-type GaN layer is subjected to anisotropic wet etching (surface etching step). The N-polar surface after the etching has irregularities constituted by {10-1-1} planes. Then, an n-side electrode is formed on the bottom face of the n-type GaN layer (electrode formation step).

Abstract: Methods of performing laser spike annealing (LSA) in forming gallium nitride (GaN) light-emitting diodes (LEDs) as well as GaN LEDs formed using LSA are disclosed. An exemplary method includes forming atop a substrate a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method also includes performing LSA by scanning a laser beam over the p-GaN layer. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.

Abstract: A semiconductor light emitting device made of nitride III-V compound semiconductors including an active layer made of a first nitride III-V compound semiconductor containing In and Ga, such as InGaN; an intermediate layer made of a second nitride III-V compound semiconductor containing In and Ga and different from the first nitride III-V compound semiconductor, such as InGaN; and a cap layer made of a third nitride III-V compound semiconductor containing Al and Ga, such as p-type AlGaN, which are deposited in sequential contact.

Abstract: Methods for chemical mechanical planarization of patterned wafers are provided herein. In some embodiments, methods of processing a substrate having a first surface and a plurality of recesses disposed within the first surface may include: depositing a first material into the plurality of recesses to predominantly fill the plurality of recesses with the first material; depositing a second material different from the first material into the plurality of recesses and atop the substrate to fill the plurality of recesses and to form a layer atop the first surface; and planarizing the second material using a first slurry in a chemical mechanical polishing tool until the first surface is reached. In some embodiments, a second slurry, different than the first slurry, is used to planarize the substrate to a first level.

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.

Abstract: Epitaxially coated semiconductor wafers are produced by minimally the following steps in the order specified: (a) depositing an epitaxial layer on one side of a semiconductor wafer; (b) first polishing the epitaxially coated side of the semiconductor wafer with a polishing pad with fixed abrasive while supplying a polishing solution which is free of solids; (c) CMP polishing of the epitaxially coated side of the semiconductor wafer with a soft polishing pad which contains no fixed abrasive, while supplying a polishing agent suspension; (d) depositing another epitaxial layer on the previously epitaxially coated and polished side of the semiconductor wafer.

Abstract: A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.

Abstract: Semiconductor devices and methods of forming the same. The method includes providing a semiconductor substrate having a channel layer over the substrate. A capping layer including silicon and having a first thickness is formed over the channel layer. The capping layer is partially oxidized to form an oxidized portion of the capping layer. The oxidized portion of the capping layer is removed to form a thinned capping layer having a second thickness less than the first thickness.

Abstract: A photovoltaic device includes a semiconductor nanocrystal and a charge transporting layer that includes an inorganic material. The charge transporting layer can be a hole or electron transporting layer. The inorganic material can be an inorganic semiconductor.

Abstract: Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example.

Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.

Abstract: Semiconductor layer forming gas is introduced into a reaction chamber, and the gas generates a plasma discharge, so that a semiconductor layer is formed. In addition to the gas, impurity gas is introduced into the chamber, and first conductivity type layer forming gas including the semiconductor layer forming gas and the impurity gas generates a plasma discharge, so that a first conductivity type layer of a first conductivity type is formed so as to cover the semiconductor layer. In the step of forming the first conductivity type layer, a composition set value of gas supplied to the chamber is shifted from a composition of the semiconductor layer forming gas to a composition of the first conductivity type layer forming gas in a state where a pressure in the chamber is not reduced to ultimate vacuum even after a plasma discharge processing for forming the semiconductor layer is terminated.

Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.

Abstract: A semiconductor component has a semiconductor layer sequence made of a nitridic composite semiconductor material on a substrate. The substrate includes a silicon surface facing the semiconductor layer sequence. The semiconductor layer sequence includes an active region and at least one intermediate layer made of an oxygen-doped AN composite semiconductor material between the substrate and the active region.

Abstract: Methods for fabricating graphene nanoelectronic devices with semiconductor compatible processes, which allow wafer scale fabrication of graphene nanoelectronic devices, is provided. One method includes the steps of preparing a dispersion of functionalized graphene in a solvent; and applying a coating of said dispersion onto a substrate and evaporating the solvent to form a layer of functionalized graphene; and defunctionalizing the graphene to form a graphene layer on the substrate.

Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Abstract: A manufacturing method of a microelectronic device including at least one semi-conductor zone which rests on a support and which exhibits a germanium concentration gradient in a direction parallel to the principal pane of the support.

Abstract: Methods for making growth templates for the epitaxial growth of compound semiconductors and other materials are provided. The growth templates are thin layers of single-crystalline materials that are themselves grown epitaxially on a substrate that includes a thin layer of sacrificial material. The thin layer of sacrificial material, which creates a coherent strain in the single-crystalline material as it is grown thereon, includes one or more suspended sections and one or more supported sections.