Abstract: A method of selective epitaxial growth for a semiconductor device is disclosed. By employing a hydrogen gas as a selectivity promoting gas in addition to a chlorine gas conventionally used, the method can guarantee the selectivity of epitaxial growth and further increase the growth rate of an epitaxial layer. The method begins with loading a semiconductor substrate into a reaction chamber. The substrate has a mask layer, which is selectively formed thereon to define a first portion exposed beyond the mask layer and a second portion covered by the mask layer. Next, a source gas is supplied into the reaction chamber so that the source gas is adsorbed on the first portion and thus the epitaxial layer is selectively formed on the first portion. Then, the selectivity promoting gas including the H2 gas into the reaction chamber, whereby any nucleus of semiconductor material is removed from the mask layer.

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) is described incorporating growing epitaxial Si1−yGey layers on a semiconductor substrate, implanting hydrogen into a selected Si1−yGey layer to form a hydrogen-rich defective layer, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and separating two substrates at the hydrogen-rich defective layer. The separated substrates may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC.

Abstract: A method of measuring the thickness of an epitaxial layer is disclosed. The method is particularly useful in measuring the epitaxial layer with a doping concentration lower than or similar to the substrate on which the epitaxial layer is formed. The method uses a non-single crystal layer previously formed on the substrate before forming the epitaxial layer over the substrate so that the portion of the epitaxial layer on the non-single crystal layer will be polycrystal. To obtain the thickness of the epitaxial layer, thicknesses of the polycrystal layer and the non-single crystal layer as well as the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer are measured. The thickness of the epitaxial layer equals the result of the total thickness of the polycrystal layer plus the non-single crystal layer minus the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer.

Abstract: First, the substrate temperature is set to 1020° C., and an n-type cladding layer (14) made of n-type Al0.1Ga0.9N, an n-type optical guide layer (15) made of n-type GaN, and a flatness maintenance layer (16) made of n-type Al0.2Ga0.8N for maintaining the surface flatness of the n-type optical guide layer (15) by suppressing re-evaporation of the constituent atoms of the n-type optical guide layer (15), are grown in this order on a substrate (11) made of sapphire. Then, the supply of a group III material gas is stopped, the substrate temperature is decreased to 780° C., and the carrier gas is switched from a hydrogen gas to a nitrogen gas. Then, an active layer (17) having a multiple quantum well structure is grown by introducing NH3 as a group V source and selectively introducing TMI and TMG as a group III source.

Abstract: Generally, a substrate processing apparatus is provided. In one aspect of the invention, a substrate processing apparatus is provided. In one embodiment, the substrate processing apparatus includes one or more chamber bodies coupled to a gas distribution system. The chamber bodies define at least a first processing region and a second processing region within the chamber bodies. The gas distribution system includes a first, a second and a third gas supply circuit. The first gas supply circuit is teed between the first and second processing regions and is adapted to supply a first processing gas thereto. The second gas supply circuit is coupled to the first processing region and adapted to supply a second process gas thereto. The third gas supply circuit is coupled to the second processing region and is adapted to supply a third process gas thereto. Alternatively, the processing regions may be disposed in a single chamber body.

Abstract: A method of fabricating a vertical cavity surface emitting laser comprising the steps of epitaxially growing a first DBR positioned on a substrate wherein the first DBR is epitaxially grown using MOCVD. The substrate is orientated in an off-axis crystallographic direction which increases the radiative efficiency. A first cladding layer is positioned on the first DBR and an active region is epitaxially grown on the first cladding layer wherein the active region is epitaxially grown using plasma assisted MBE. A second DBR is epitaxially grown on the second cladding layer wherein the second DBR is epitaxially grown using MOCVD. The active region is epitaxially grown using plasma assisted MBE to increase the mole fraction of nitrogen (N) incorporation. The DBR's are grown using MOCVD to improve the electrical performance.

Abstract: A low defect density (Ga,Al,In)N material. The (Ga, Al, In)N material may be of large area, crack-free character, having a defect density as low as 3×106 defects/cm2 or lower. Such (Ga,Al,In)N material is useful as a substrate for epitaxial growth of Group III-V nitride device structures thereon.

Abstract: The present invention discloses a method of fabricating a thin film in a chamber where a heater and a suscepter are located. The method includes the steps of disposing an object on the susceptor so as to form the thin film thereon; heating the object; a first sub-step of introducing a first gaseous reactant into the first chamber such that the first gaseous reactant is absorbed on the object to form an absorption layer; a second sub-step of introducing a second gaseous reactant into the first chamber such that the second gaseous reactant reacts with the absorption layer absorbed on the object; and a third sub-step of introducing a reducing gas into the first camber such that the reducing gas reduces by-products and impurities of the first and second gaseous reactants.

Abstract: A semiconductor device includes: a semiconductor substrate; an active layer; and a plasma-processed layer provided between the semiconductor substrate and the active layer. The plasma-processed layer has a deep level. First and second electrodes are electrically connected by ohmic contact with first and second portions of the active layer, respectively. The first and second portions are spaced apart at a predetermined interval from each other. A third electrode is formed on a third respective portion of the active layer and is located between the first and second portions of the active layer.

Abstract: It is an object of the invention to provide a semiconductor wafer obtained by forming a semiconductor thin film with uniform resistivity on a main surface of a semiconductor single crystal substrate of 300 mm or more in diameter. When a process gas is supplied to over a main surface of a silicon single crystal substrate 12 in rotation in almost parallel to the main surface thereof in one direction in a reaction chamber 10 through six inlet ports 18a to 18f disposed in width direction of the reaction chamber 10, H2 gas, a semiconductor raw material gas and a dopant gas are supplied onto an area in the vicinity of the center of the main surface of the silicon single crystal substrate 12 and an intermediate area thereof through the inner inlet ports 18a and 18b and the middle inlet ports 18c and 18d, and only H2 gas and the semiconductor raw material gas without the dopant gas are supplied onto an area in the vicinity of the outer periphery thereof from the outer inlet ports 18e and 18f.

Abstract: The present invention is characterized by providing epitaxial growth of a semiconductor layer on the surface of a wafer not provided with mirror finishing and having irregularity, introducing impurities having different conductivity type in the epitaxially grown semiconductor layer to form at least a pn junction, and further providing rapid thermal anneal by rapid heating-up and rapid cooling-down in any step in the manufacturing process. By so processing, there can be obtained a semiconductor device having high speed switching characteristics in stable manner without causing problems in manufacturing process such as diffusion of heavy metal or irradiation of corpuscular ray.

Abstract: There is provided a single electron device. The device has weak links with bottle-neck figure in place of the tunnel junction of the prior device. The weak links are easily formed on the same substrate by simple processes and thus the integration of the single electron device can be easily achieved.

Abstract: A quantic effect device which functions using a Coulomb blockade phenomenon. The device includes two electron reservoirs, two sets of islands that are separated by a dielectric layer, a protective insulating layer and a control electrode.

Abstract: A method for fabricating an infrared-emitting light-emitting diode in which a layer sequence is applied onto a semiconductor substrate, preferably composed of GaAs. The layer sequence has, proceeding from the semiconductor substrate, a first AlGaAs cover layer, a GaAs and/or AlGaAs containing active layer and a second AlGaAs cover layer. In which case, the first AlGaAs cover layer and the active layer are fabricated by a metal organic vapor phase epitaxy (MOVPE) method and the second AlGaAs cover layer is fabricated by a liquid phase epitaxy (LPE) method. Furthermore, an electrically conductive coupling-out layer having a thickness of at least about 10 &mgr;m is deposited on the second AlGaAs cover layer by the LPE method. The coupling-out layer is optically transparent in the infrared spectral region.

Abstract: Wafer surfaces of the present invention comprise semiconductor and dielectric regions formed in such a way that allows the wafer surface to wet so that residual particles can be removed therefrom during a wet clean. The wafer surface comprises exposed regions of dielectric and semiconductor after a CMP removal process. The percentage of the total wafer surface area that is semiconductor after CMP is less than or equal to than a predetermined fraction, and the remainder of the wafer surface area comprises dielectric. Also, the regions of semiconductor on the wafer surface have a maximum shortest dimension. The combined percentage of semiconductor in the total wafer surface area and the maximum shortest dimensions of each semiconductor region are small enough so that the wafer surface is hydrophilic enough to wet.

Abstract: The present invention provides a method of manufacturing a low resistivity p-type compound semiconductor material over a substrate. The method of the present invention comprises the steps of forming a p-type impurity doped compound semiconductor layer on the substrate by either HVPE, OMVPE or MBE and applying a microwave treatment over the p-type impurity doped compound semiconductor layer for a period of time. The high resistivity p-type impurity doped compound semiconductor layer is converted into a low resistivity p-type compound semiconductor material according to the present invention.

Abstract: There is disclosed a method of manufacturing a capacitor in a semiconductor device. The present invention forms a Ru film as a lower electrode of the capacitor in which a Ta2O5 film is used as a dielectric film by introducing Ru of a raw material, oxygen and NH3 in order to reduce oxygen or a NH3 plasma process as a subsequent process is performed in order to remove oxygen existing on the surface of the Ru film. Therefore, the present invention can prevent oxidization of a diffusion prevention film due to oxygen existing in a Ru film during annealing process performed after deposition of a Ta2O5 film and thus improve reliability of the device.

Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.

Abstract: An atomic layer deposition (ALD) thin film deposition apparatus including a reactor 100 in which a wafer is mounted and a thin film is deposited on the wafer, a first reaction gas supply portion 210 for supplying a first reaction gas to the reactor 100, a second reaction gas supply portion 230 for supplying a second reaction gas to the reactor 100, a first reaction gas supply line 220 for connecting the first reaction gas supply portion 210 to the reactor 100, a second reaction gas supply line 240 for connecting the second reaction gas supply portion 230 to the reactor 100, a first inert gas supply line 260 for supplying an inert gas from an inert gas supply source 250 to the first reaction gas supply line 220, a second inert gas supply line 270 for supplying an inert gas from the inert gas supply source 250 to the second reaction gas supply line 240, and an exhaust line 400 for exhausting the gas within the rector 100 to the outside.

Abstract: A method of fabricating an integrated circuit provides a transistor having less susceptibility to short channel effects. The transistor utilizes a U-shaped gate conductor and a main gate conductor. The U-shaped gate conductor can provide electrically induced source/drain extensions. The transistor can be a PMOS or NMOS transistor.

Abstract: A method for upgrading qualities of DRAM capacitors and wafer-to-wafer uniformity is disclosed. In order to effectively prevent wafers from contaminations, the invention uses an additional silane purge process in situ before performing a SHSG seeding process on the wafers. The silane purge process of this invention utilizes the original silane seeding gas inlet. In this manner, not only thicknesses and surface areas of the SHSG seeds and capacitances of DRAMs can be increased, but also wafer-to-wafer uniformity can be upgraded.

Abstract: In a semiconductor thin-film formation process comprising feeding a semiconductor thin-film material gas into a discharge space, and applying a high-frequency power thereto to cause plasma to take place and decompose the material gas to form an amorphous semiconductor thin film on a desired substrate, the high-frequency power is applied changing its power density continuously or stepwise from a high power density to a low power density and thereafter again changing the power density continuously or stepwise from a low power density to a high power density, to form a semiconductor thin film made different in film quality in the direction of layer thickness while retaining the same conductivity type This process enables formation of high-quality semiconductor thin films by plasma CVD.

Abstract: A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). The growth of the nanoclusters (19) may be accomplished using low pressure chemical vapor deposition (LPCVD) or ultra high vacuum chemical vapor deposition (UHCVD) processes. Such growth may be facilitated by formation of a nitrogen-containing layer (502) overlying the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20).

Abstract: Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.

Abstract: Techniques for etching a wafer layer using multiple layers of the same photoresistant material and structures formed using such techniques are provided. In a method, first, multiple layers of the same photoresist material are formed over the wafer layer to form a composite photoresist layer. The composite photoresist layer is patterned and developed to form a patterned photoresist layer. Exposed portions of the wafer layer are then removed using the pattern photoresist layer. Each of the multiple layers of photoresist may, for example, be formed to a maximum rated thickness for the photoresist material. Structures formed using this process may have relatively small dimensions (e.g., widths of 5 microns or less or a spacing or pitch of 5 microns or less). In addition, structures may also have sidewalls which are relatively long, smooth, and/or vertical.

Abstract: In order to fabricate a high performance thin film semiconductor device using a temperature process in which it is possible to use inexpensive glass substrates, a highly crystalline mixed-crystallinity semiconductor film is deposited by means of PECVD using a silane as the source gas and argon as the dilution gas, then the crystallinity of this film is improved by such means as laser irradiation. Thin film semiconductor devices fabricated in this way are used in the manufacture of such things as liquid crystal displays and electronic devices.

Abstract: A layer configuration includes a material layer and a diffusion barrier which blocks diffusing material components. The barrier is disposed in the vicinity of a layer boundary of the material layer and is formed predominantly in grain boundaries of the material layer. A process for producing a diffusion barrier is also provided.

Abstract: The present invention is characterized by providing epitaxial growth of a semiconductor layer on the surface of a wafer not provided with mirror finishing and having irregularity, introducing impurities having different conductivity type in the epitaxially grown semiconductor layer to form at least a pn junction, and further providing rapid thermal anneal by rapid heating-up and rapid cooling-down in any step in the manufacturing process. By so processing, there can be obtained a semiconductor device having high speed switching characteristics in stable manner without causing problems in manufacturing process such as diffusion of heavy metal or irradiation of corpuscular ray.

Abstract: In this invention, one or more metal-containing sources and one or more ammonium halides are heated such that they evaporate into a vacuum environment (except that, in MOMBE, a beam of the organometallic source compound may be created by other means) and made to impinge on a substrate. The materials interact on the substrate to form a film of the desired nitride compound or alloy; the substrate usually will be heated to promote chemical reaction and good film properties such as high crystallinity. Other sources—to provide dopant impurities like silicon or magnesium, for example—would be part of a deposition system envisioned in this invention. Multiple film layers, including quantum wells and superlattices, may be formed using this method, in addition to a single film.

Abstract: A film, typically a silicon-based film, is formed on a substrate by means of a plasma CVD process using a high frequency wave in a condition where a resistance element made of a different material than that of the substrate is provided on the electric path between the substrate and the earth. The resultant film shows a high quality and an improved adhesion strength while it can be formed at a practically high rate.

Abstract: A method is designed to manufacture a silicon epitaxial wafer exhibiting sufficient gettering capability from the initial stage of the device process. Specifically, the method is to manufacture the silicon wafer with a nitrogen concentration of at least 1×1012 atoms/cm3 and an oxygen concentration of 10˜18×1017 atoms/cm3 by annealing at a temperature of 800 ˜1,100° C.

Abstract: In growing single AlN thin films on a semiconductor substrate by rapidly cooling a beam of atomic Al and atomic or molecular N obtained by exciting or decomposing N2 with an electromagnetic wave on the semiconductor substrate, an n-type dopant and a p-type dopant in the form of atomic beams are simultaneously doped in a crystal, so that pairs of an n-type dopant and a p-type dopant are formed in the crystal to synthesize single crystal AlN thin films of low resistivity n-type and low resistivity p-type.

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850° C. As the substrate is heated to a temperature of 1050° C., N+ dopant gas is injected into the carrier gas to suppress auto doping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080° C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080° C.

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850° C. As the substrate is heated to a temperature of 1050° C., N+ dopant gas is injected into the carrier gas to suppress auto doping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080° C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080° C.

Abstract: The present invention concerns a method for optimising the etching rate of a polycrystalline layer having a predetermined composition comprising at least two chemical species arranged in the form of grains and grain boundaries, this layer having to be formed on a semiconductor substrate by a deposition process whose parameters have to be determined, and by a etching process with a reactive agent capable of reacting with the preponderant species in the layer. This method defines a structure parameter representing the grain boundary density of the layer, and comprises a step consisting in determining the smallest structure parameter value from among different samples having the predetermined composition, this value being considered as that which optimises the etching rate.

Abstract: A compound semiconductor device includes a low resistance source and drain region covered by a protective layer of a compound semiconductor device carrying thereon a source electrode or a drain electrode. Further, a low resistance source and drain region formed by a regrowth process of a compound semiconductor material is disclosed.

Abstract: A method for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate. A step of increasing a built-in energy state of the substrate is also included.

Abstract: A process for producing an SOI substrate is disclosed which is useful for saving resources and lowering production cost. Further, a process for producing a photoelectric conversion device such as a solar cell is disclosed which can successfully separate a substrate by a porous Si layer, does not require a strong adhesion between a substrate and a jig, and can save resources and lower production cost. In a substrate having a porous layer on a nonporous layer and further having on the porous layer a layer small in porosity, the nonporous layer and the layer small in porosity are separated by the porous layer to form a thin film. A metal wire is wound around a side surface of the substrate, and a current is made to flow into the metal wire to generate a heat from the metal wire and transfer the heat preferentially to the porous layer, thus conducting the separation.

Abstract: A semiconductor light-emitting device with a double hetero structure, including: an active layer made of Ga.sub.1-x In.sub.x N (0.ltoreq.x.ltoreq.0.3) doped with a p-type impurity and an n-type impurity; and first and second cladding layers provided so as to sandwich the active layer.

Abstract: A quantum dot and quantum fine wire forming method is provided which can allow control of the position for crystalline particle growth and enables formation of particles with high uniformity in size and density and with high reproducibility. After an Si substrate is formed with a step by a dry etching method, an SiO.sub.2 film is formed on the surface of the substrate. The interior of a reaction chamber is evacuated to a vacuum of 10.sup.-8 Torr, and then an Si.sub.2 H.sub.6 gas is introduced into the reaction chamber to flow therein so that Si crystal particles (quantum dots) are formed along the step. The step is formed by conventional photolithography and dry etching; therefore, the position for quantum dot growth can be easily controlled. By controlling the rate and time period of gas flow and the temperature of the substrate it is possible to form quantum fine wires, and to control the size of quantum dots and/or thickness of quantum fine wires.

Abstract: A base layer of electode made of at least a metal selected from V, Nb, and Zr, or an alloy containing such metal on an n-type GaN compound semiconductor layer. Further, a main electrode layer made of other metal is formed on the base layer. Then, an n electrode is formed by subjecting the semiconductor layer, the base layer, and the main electrode layer to a heat treatment.

Abstract: A method for forming a conductive film for a semiconductor device wherein a conductive film is formed on each wafer loaded in a boat of a vertical furnace of a low pressure chemical vapor deposition apparatus provided with a chamber, a reaction tube in a center portion of the chamber, a boat loaded in the reaction chamber and a heater surrounding the chamber. The method includes a decompression step for reducing pressure in the chamber to a vacuum condition, a deposition step for depositing a conductive film on each wafer by introducing reaction gas into the chamber in the vacuum condition, a purge step for removing from the chamber toxic gas generated in the deposition step, and a normal pressure step for increasing pressure and temperature in the chamber, wherein the pressure increases from the normal pressure step and the temperature increases from the purge step.

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850.degree. C. As the substrate is heated to a temperature of 1050.degree. C. N+ dopant gas is injected into the carrier gas to suppress autodoping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080.degree. C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080.degree. C.

Abstract: A method of growing a p-type doped Group II-VI semiconductor film includes the steps of forming a lattice comprising a Group II material and a Group VI material wherein a cation-rich condition is established at a surface of the lattice. The method further includes the steps of generating an elemental Group V flux by evaporating an elemental Group V material and providing the elemental Group V flux to a Group VI sublattice of the lattice.

Abstract: In a silicon conductor doped with an impurity of 100 nm or less thick, a method is provided for manufacturing a silicon thin film conductive element which can prevent the increase of resistance with a low impurity concentration. The method includes the step in which, after the formation of an impurity-containing amorphous silicon film, a crystallization is performed without removing the film from a film forming device by performing a heat treatment while flowing a gas containing the impurity.

Abstract: In a method of manufacturing a semiconductor device which includes a quartz substrate having a z-cut plane of (0001) plane on a surface, a GaN film is first deposited on the surface. Finally, the quartz substrate is removed from the GaN film. The removed GaN film is used as a real substrate for forming GaN based compound semiconductor layers thereon.

Abstract: The formation of self-assembled GaAs quantum dots on (100) GaAs via chemical beam epitaxy (CBE) technique using triethylgallium (TEGa) and arsine (AsH.sub.3) is disclosed. GaAs quantum dots are easy to grow from Ga-droplets which are successively supplied with arsine with neither pattern definition nor pre-treatment steps prior to the growth. The density and the size of Ga-droplets are found to be sensitive to the growth conditions, such as the growth temperature, the beam equivalent pressure of TEGa, and the amount of TEGa supplied. This invention suggests that, unlike Stranski-Krastanow growth, the Ga-droplet-induced CBE technique can be a useful method for the fabrication of quantum dot structure by simple change of gas supply mode, even in lattice-matched system.

Abstract: A manufacturing method for high quality GaN-based light emitting devices. The method enable effective growth of an Al.sub.y Ga.sub.1-y N (0.ltoreq.y.ltoreq.1) layer on an In.sub.x Ga.sub.1- N (0.ltoreq.x.ltoreq.1) layer by CVD. While holding or increasing the temperature after growing the InGaN layer at the temperature of T0 before growing the AlGaN at the temperature of T1 (T0.ltoreq.T1) in an atmosphere including a source of group V of elements, the present invention applies an inert gas as the carrier gas which includes a source of the group V elements. Therefore, the concentration of group V elements near the surface of the InGaN layer increases and the sublimation of the InGaN layer is prevented by increasing the steam pressure of the group V elements near the surface of the InGaN layer.

Abstract: Process for the preparation of an epitaxial wafer having a total thickness variation and/or site total indicated reading of less than about 1.0 .mu.ms. The distance between the front and back surfaces of the epitaxial wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the epitaxial wafer in a stock removal step to reduce the thickness of the epitaxial wafer to the target thickness, T.sub.t, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and T.sub.t.

Abstract: In a semiconductor single crystalline substrate provided with a protecting film to prevent autodoping on the reverse surface thereof, for growing a vapor-phase epitaxial layer on the main obverse surface thereof, a width of a chamfer is set for locating an edge-crown occurred in consequence of a vapor-phase epitaxial growth on the chamfer, and a gap of a distance is formed between a periphery of the protecting film and an innermost part of the chamfer on the reverse surface.