Fluid Growth From Gaseous State Combined With Subsequent Diverse Operation Patents (Class 438/507)
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Patent number: 5970314Abstract: A process for forming a high quality epitaxial compound semiconductor layer of indium gallium nitride In.sub.x Ga.sub.1-x N, (where 0<x<1) on a substrate. A first gas including indium trichloride (InCl.sub.3) and a second gas including ammonia (NH.sub.3) are introduced into a reaction chamber and heated at a first temperature. Indium nitride (InN) is grown epitaxially on the substrate by nitrogen (N.sub.2) carrier gas to form an InN buffer layer. Thereafter, a third gas including hydrogen chloride (H1) and gallium (Ga) is introduced with the first and second gases into a chamber heated at a second temperature higher than the first temperature and an epitaxial In.sub.x Ga.sub.1-x N layer is grown on the buffer layer by N.sub.2 gas. By using helium, instead of N.sub.2, as carrier gas, the In.sub.x Ga.sub.1-x N layer with more homogeneous quality is obtained. In addition, the InN buffer layer is allowed to be modified into a GaN buffer layer.Type: GrantFiled: March 24, 1997Date of Patent: October 19, 1999Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takuji Okahisa, Mitsuru Shimazu, Masato Matsushima, Yoshiki Miura, Kensaku Motoki, Hisashi Seki, Akinori Koukitu
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Patent number: 5966625Abstract: A single crystal silicon wafer is sliced off so as to have a slant surface that is inclined from plane (001) such that the normal of the slant surface is inclined by 0.01.degree. to 0.2.degree. from direction [001] toward direction [110]. After being cleaned, the silicon wafer is heat-treated at 600-1,300.degree. C. for not less than 1 minute in an ultrapure argon or hydrogen atmosphere containing nitrogen at not more than 0.1 ppm, to thereby cause the slant surface to have a stepped crystal surface structure. The stepped crystal surface structure is constituted of step walls Sa and Sb when it has been formed by a heat treatment in an argon atmosphere, and substantially all of its step walls are of a type Sb when it has been formed by a heat treatment in a hydrogen atmosphere.Type: GrantFiled: November 6, 1998Date of Patent: October 12, 1999Assignee: Toshiba Ceramics Co., Ltd.Inventors: Lei Zhong, Norihiro Shimoi, Yoshio Kirino
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Patent number: 5956602Abstract: The present invention provides a method for depositing polycrystal Si films, including n-type and p-type polycrystal Si films, using a material gas, a doping gas, and hydrogen gas. This method comprises a film-forming time-period having:(a) a time-period for depositing a film;(b) a time-period for diffusing dopants in the deposited film; and(c) a time-period for treating the film surface with hydrogen plasma. According to this method, an n-type or p-type polycrystal Si film with excellent crystallinity can be provided using the material gas and the doping gas. Further, this method is able to proceed at a low temperature and achieve satisfactory structural relaxation of the resulting film.Type: GrantFiled: March 8, 1996Date of Patent: September 21, 1999Assignee: Canon Kabushiki KaishaInventor: Shunichi Ishihara
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Patent number: 5937313Abstract: Disclosed is a method of forming quantum wires for compound semiconductors capable of forming a large number of quantum wires. Quantum wires for compound semiconductors according to the present invention are formed by the following processes. First, a compound semiconductor substrate is provided and Al.sub.X Ga.sub.1-X As layers and GaAs layers are then formed alternately on the substrate to predetermined times to form a quantum well. Next, a plurality of grooves are formed in the upper most GaAs layer to a predetermined depth wherein the grooves are separated with a predetermined space from each other. Stress is applied to the quantum well such that the Al.sub.X Ga.sub.1-X As layers surround the GaAs layers to thereby form a large number of quantum wires.Type: GrantFiled: December 9, 1997Date of Patent: August 10, 1999Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Joon-Mo Kang
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Patent number: 5930656Abstract: A substrate for forming a compound semiconductor device is placed in a reaction chamber. An MOCVD method or a GS-MBE method is used to grow compound semiconductor layers on the substrate. The grown layers include, for example, a GaN buffer layer, an n-GaN layer, an InGaN active layer, a p-AlGaN layer, and a p.sup.+ -GaN contact layer. After the growth of the layers, the substrate is kept in the reaction chamber, and a passivation film of, for example, SiNx, SiO2, or SiON is formed on top of the grown layers according to a CVD or GS-MBE method. Since the top of the grown layers is not exposed to air outside the reaction chamber, no oxidization or contamination occurs on the top of the grown layers. The compound semiconductor device is manufactured through simpler processes compared with a prior art that needs separate apparatuses for growing and forming the layers and passivation film.Type: GrantFiled: October 17, 1997Date of Patent: July 27, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Chisato Furukawa, Masayuki Ishikawa, Hideto Sugawara, Kenji Isomoto
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Patent number: 5926726Abstract: A method of manufacturing a p-type III-V nitride compound semiconductor utilizing vapor phase epitaxy is carried out in a MOCVD reactor by growing a III-V nitride compound semiconductor in the reactor employing a reaction gas containing a p-type impurity and then annealing in-situ the nitride compound semiconductor to bring about acceptor activation, the annealing carried out at a temperature below the growth temperature of the III-V nitride compound semiconductor during reactor cooldown. A nitrogen (N) reactant or precursor is provided in the reactor during the annealing step which can produce a reactive form of N capable of suppressing surface decomposition and does not produce atomic hydrogen. Also, acceptor activation is achieved through the employment of a cap layer comprising a n-type Group III-V nitride material, e.g., n-GaN, grown on the p-doped Group III-V nitride layer preventing the occurrence of hydrogenation of the underlying p-doped layer during cooldown.Type: GrantFiled: September 12, 1997Date of Patent: July 20, 1999Assignees: SDL, Inc., Xerox CorporationInventors: David P. Bour, G.A. Neville Connell, Donald R. Scifres
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Patent number: 5908305Abstract: The device comprises a layer of silicon separated from a substrate by a layer of insulating material. A rib having an upper surface and two side surfaces is formed in the layer of silicon to provide a waveguide for the transmission of optical signals. A lateral doped junction is formed between the side surfaces of the rib such that an electrical signal can be applied across the junction to control the density of charge carriers across a substantial part of the cross-sectional area of the rib thereby actively altering the effective refractive index of the waveguide.Type: GrantFiled: May 22, 1998Date of Patent: June 1, 1999Assignee: Bookham Technology LimitedInventors: Stephen James Crampton, Arnold Peter Roscoe Harpin, Andrew George Rickman
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Patent number: 5895260Abstract: Fabricating a device including a Schottky diode by growing a dielectric film on a SiC substrate structure and forming an ohmic contact on the opposite surface of the substrate structure by depositing a layer of metal and annealing at a temperature above 900.degree. C. Implanting doping material in the substrate structure through spaced apart openings to form high resistivity areas and depositing a dielectric layer on the dielectric film to define a contact opening positioned between the spaced apart high resistivity areas. Annealing the implant at a temperature less than approximately 400.degree. C. to reduce reverse leakage current and depositing metal in the contact opening to form a Schottky contact.Type: GrantFiled: March 29, 1996Date of Patent: April 20, 1999Assignee: Motorola, Inc.Inventors: Mohit Bhatnagar, Charles E. Weitzel, Christine Thero
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Patent number: 5891790Abstract: Growth of doped gallium nitride, especially p-type gallium nitride, without using post-growth processing is achieved by eliminating hydrogen containing molecules from the growth process before cooling down the substrate. Rapid cooling of the substrate with nitrogen gas prevents the reaction of p-type dopant atoms with hydrogen, and the use of the nitrogen gas also keeps the nitrogen intact within the crystalline structure.Type: GrantFiled: June 17, 1997Date of Patent: April 6, 1999Assignee: The Regents of the University of CaliforniaInventors: Stacia Keller, Peter Kozodoy, Umesh K. Mishra, Steven P. Denbaars
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Patent number: 5879970Abstract: Polycrystalline silicon-germanium alloy is grown on a glass substrate through a chemical vapor deposition under the conditions where the substrate temperature ranges from 350 degrees to 450 degrees in centigrade, the ratio between gas flow rate of Si.sub.2 H.sub.6 and the gas flow rate of GeF.sub.4 ranges from 20:0.9 to 40:0.9 and the dilution gas is selected from the group consisting of helium, argon, nitrogen and hydrogen, and the composition ratio of silicon of the polycrystalline silicon-germanium is equal to or greater than 80 percent so that the carrier mobility is drastically improved.Type: GrantFiled: September 3, 1997Date of Patent: March 9, 1999Assignee: NEC CorporationInventors: Kunihiko Shiota, Jun-ichi Hanna
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Patent number: 5874349Abstract: In a method of forming a II-VI compound semiconductor thin film on an InP substrate, a layer of III-V compound semiconductor mixed crystal is first formed on the InP substrate. The desorption rate of a group V element constituting the III-V compound semiconductor mixed crystal at a decomposition temperature of a native oxide layer formed on a surface of the III-V compound semiconductor mixed crystal layer is lower than a desorption rate of P of the InP substrate at a decomposition temperature of a native oxide layer formed on a surface of the InP substrate. A II-VI compound semiconductor thin film layer is formed on the first III-V compound semiconductor mixed crystal layer.Type: GrantFiled: January 31, 1997Date of Patent: February 23, 1999Assignee: NEC CorporationInventors: Kouichi Naniwae, Toru Suzuki
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Patent number: 5854123Abstract: A method is provided for producing, with high reproducibility, an SOI substrate which is flat and high in quality, and simultaneously for achieving resources saving and reduction in cost through recycling of a substrate member. For accomplishing this, a porous-forming step is performed forming a porous Si layer on at least a surface of an Si substrate and a large porosity layer forming step is performed for forming a large porosity layer in the porous Si layer. This large porosity layer forming step is performed by implanting ions into the porous Si layer with a given projection range or by changing current density of anodization in said porous-forming step. At this time, a non-porous single-crystal Si layer is epitaxial-grown on the porous Si layer. Thereafter, the surface of the porous Si layer and a support substrate are bonded together, and then separation is performed at the porous Si layer with the large porosity. Subsequently, selective etching is performed to remove the porous Si layer.Type: GrantFiled: October 7, 1996Date of Patent: December 29, 1998Assignee: Canon Kabushiki KaishaInventors: Nobuhiko Sato, Takao Yonehara, Kiyofumi Sakaguchi
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Patent number: 5834362Abstract: A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.Type: GrantFiled: March 21, 1996Date of Patent: November 10, 1998Assignee: Fujitsu LimitedInventors: Shinji Miyagaki, Takashi Eshita, Satoshi Ohkubo, Kazuaki Takai
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Patent number: 5834363Abstract: There is disclosed a method of manufacturing a semiconductor wafer which has a dopant evaporation preventive film formed on one of main surfaces thereof, wherein a film serving as the dopant evaporation preventive film is formed on the one of the main surface by a plasma CVD method. There is also disclosed a method of manufacturing a semiconductor wafer having a plasma CVD film on one of main surfaces, wherein the plasma CVD film is formed on the one of the main surfaces of the semiconductor wafer so that a stress between the plasma CVD film and the semiconductor wafer falls in a range of 1.times.10.sup.8 -1.times.10.sup.9 dyne/cm.sup.2. Finally, a semiconductor wafer is disclosed having a plasma CVD film formed on only one face that serves as a barrier to autodoping during processing and which may function to create within the semiconductor wafer a strained layer that can getter impurities.Type: GrantFiled: March 27, 1997Date of Patent: November 10, 1998Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Mayuzumi Masanori
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Patent number: 5811349Abstract: A fluid switching valve comprises a valve box and a rotary valve element. The valve box is provided with a plurality of fluid inlets and a single fluid outlet connected with each other by a fluid passage, wherein the rotary valve element is formed to block the fluid passage for an arbitrary rotational angle of the valve element, by engaging with an inner wall of the fluid passage. The valve element carries on an outer surface thereof a plurality of grooves in correspondence to the plurality of fluid inlets, wherein each of the grooves has a cross sectional area that changes from a first end to a second end, such that a sum of the cross sectional areas of the plurality of grooves is maintained substantially constant.Type: GrantFiled: November 4, 1996Date of Patent: September 22, 1998Assignee: Fujitsu LimitedInventor: Masahiro Watabe
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Patent number: 5744380Abstract: There is provided a high quality epitaxial water on which the density of microscopic defects in the epitaxial layer is reduced to keep the GOI thereof sufficiently high and to reduce a leakage current at the P-N junction thereof when devices are incorporated, to thereby improve the yield of such devices. In an epitaxial wafer obtained by forming an epitaxial layer on a substrate, the density of IR laser scatterers is 5.times.10.sup.5 pieces/cm.sup.3 or less throughout the epitaxial layer.Type: GrantFiled: February 26, 1997Date of Patent: April 28, 1998Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Noriyuki Uemura, Hisami Motoura, Masashi Nishimura, Mitsuo Kohno
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Patent number: 5630905Abstract: A quantum bridge structure including wires of a semiconductor material such as silicon which are formed by selectively etching a superlattice of alternating layers of at least two semiconductor materials. The quantum bridge is useful as a photo emission device, a photo detector device, and a chemical sensor. The wires exhibit improved electrical conduction properties due to decreased Coulomb scattering.Type: GrantFiled: June 5, 1995Date of Patent: May 20, 1997Assignee: The Regents of the University of CaliforniaInventors: William T. Lynch, Kang L. Wang, Martin O. Tanner
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Patent number: 5620557Abstract: A method of manufacturing two sapphireless layers (3a, 3b) at one time made of Group III nitride compound semiconductor satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0, and x=y=0, and a LED (10) utilizing one of the semiconductor layers (3a, 3b) as a substrate (3) includes the steps of forming two zinc oxide (ZnO) intermediate layers (2a, 2b) on each side of a sapphire substrate (1), forming two Group III nitride compound semiconductor layers (3a, 3b) satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0, and x=y=0, each laminated on each of the intermediate ZnO layers (2a, 2b), and separating the intermediate ZnO layers (2a, 2b) from the sapphire substrate (1) by etching with an etching liquid only for the ZnO layers (2a, 2b).Type: GrantFiled: June 26, 1995Date of Patent: April 15, 1997Assignee: Toyoda Gosei Co., Ltd.Inventors: Katsuhide Manabe, Masayoshi Koike, Hisaki Kato, Norikatsu Koide, Isamu Akasaki, Hiroshi Amano
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Patent number: 5616515Abstract: A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides.Type: GrantFiled: June 7, 1995Date of Patent: April 1, 1997Assignee: Texas Instruments IncorporatedInventor: Yasutoshi Okuno