Abstract: There are now provided thin-film solar cells and method of making. The devices comprise a low-cost, low thermal stability substrate with a semiconductor body deposited thereon by a deposition gas. The deposited body is treated with a conversion gas to provide a microcrystalline silicon body. The deposition gas and the conversion gas are subjected to a pulsed electromagnetic radiation to effectuate deposition and conversion.

Abstract: Methods for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on multiple synthesis sites carried by a substrate and structures formed thereby. After an initial growth stage, synthesis sites bearing conducting carbon nanotubes are altered to discontinue synthesis at these specific synthesis sites and, thereby, halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration so that semiconducting carbon nanotubes may be lengthened to a greater length than the conducting carbon nanotubes.

Abstract: The active region of a long-wavelength light emitting device is made by providing an organometallic vapor phase epitaxy (OMVPE) reactor, placing a substrate wafer capable of supporting growth of indium gallium arsenide nitride in the reactor, supplying a Group III–V precursor mixture comprising an arsenic precursor, a nitrogen precursor, a gallium precursor, an indium precursor and a carrier gas to the reactor and pressurizing the reactor to a sub-atmospheric elevated growth pressure no higher than that at which a layer of indium gallium arsenide layer having a nitrogen fraction commensurate with light emission at a wavelength longer than 1.2 ?m is deposited over the substrate wafer.

Abstract: A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

Abstract: The present invention has its object to obtain an SiC monitor wafer which can flatten the surface until particle detection is possible. SiC of a crystal system 3C is deposited on a substrate by a CVD (Chemical Vapor Deposition) method, and the SiC is detached from a substrate. After the SiC surface is flattened by using mechanical polishing alone or in combination with CMP (Chemo Mechanical Polishing), GCIB (Gas Cluster Ion Beam) is irradiated to the surface until the surface roughness becomes Ra=0.5 nm or less and the impurity density of the wafer surface becomes 1*1011 atoms/cm2 or less to produce the SiC monitor wafer.

Abstract: A method for forming strain-relaxed SiGe films comprises depositing a graded strained SiGe layer on a substrate in which the concentration of Ge is greater at the interface with the substrate than at the top of the layer. The strained SiGe film is subsequently oxidized, producing a strain-relaxed SiGe film with a substantially uniform Ge concentration across the thickness of the film. The relaxed SiGe layer may be used to form a strained silicon layer on a substrate.

Abstract: A method is disclosed for preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (Vf) drift in silicon carbide-based bipolar devices. The method includes the steps of etching the surface of a silicon carbide substrate with a nonselective etch to remove both surface and sub-surface damage, thereafter etching the same surface with a selective etch to thereby develop etch-generated structures from at least any basal plane dislocation reaching the substrate surface that will thereafter tend to either terminate or propagate as threading defects during subsequent epilayer growth on the substrate surface, and thereafter growing a first epitaxial layer of silicon carbide on the twice-etched surface.

Abstract: An electrode manufacturing method comprises: forming plural protruding portions on a surface of a substrate; introducing first particles having a size that changes according to heat, light, or a first solvent between said plural protruding portions; changing the size of the first particles by applying heat, light, or the first solvent to said first particles; and depositing an electrode material onto the surface of said substrate.

Abstract: A method of forming a film on a substrate using Group IIIA metal complexes. The complexes and methods are particularly suitable for the preparation of semiconductor structures using chemical vapor deposition techniques and systems.

Abstract: A system for fabricating a light emitting device is disclosed. The system contains a growth chamber and at least one nitrogen precursor that is introduced to the growth chamber. The at least one nitrogen precursor has a direct bond between at least one group III atom and at least one nitrogen atom. In addition, the nitrogen precursor is used to fabricate a layer constituting part of an active region of the light emitting device containing indium, gallium, arsenic, and nitrogen, wherein the active region produces light having a wavelength in the range of approximately 1.2 to 1.6 micrometers. A method for fabricating a semiconductor structure is also disclosed. The method comprises providing a substrate and growing over the substrate a layer comprising indium, gallium, arsenic, and nitrogen using at least one nitrogen precursor having a direct bond between at least one group III atom and at least one nitrogen atom.

Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.

Abstract: A nitride semiconductor having a large low-defect region in a surface thereof, and a semiconductor device using the same are provided. Also, a manufacturing method for a nitride semiconductor comprising a layer formation step using a transverse growth technique where surface defects can easily be reduced, and a manufacturing method for a semiconductor device using the same are provided. On a substrate, a seed crystal part is formed in a stripe pattern with a buffer layer in between. Next, crystals are grown from the seed crystal part in two stages of growth conditions to form a nitride semiconductor layer. Low temperature growing parts with a trapezoid shaped cross section are formed at a growth temperature of 1030° C. in the first stage and a transverse growth is dominantly advanced at a growth temperature of 1070° C. to form a high temperature growing part between the low temperature growing parts in the second stage.

Abstract: A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

Abstract: Atomic hydrogen flux impinging on the surface of a growing layer of III-V compounds during VCSEL processing can prevent three-dimensional growth and related misfit dislocations. Use of hydrogen during semiconductor processing can allow, for example, more indium in InGaAs quantum wells grown on GaAs. Atomic hydrogen use can also promote good quality growth at lower temperatures, which makes nitrogen incorporated in a non-segregated fashion producing better material. Quantum wells and associated barriers layers can be grown to include nitrogen (N), aluminum (Al), antimony (Sb), and/or indium (In) placed within or about a typical GaAs substrate to achieve long wavelength VCSEL performance, e.g., within the 1260 to 1650 nm range.

Abstract: A method for fabricating thin films of an icosahedral boride on a silicon carbide (SiC) substrate is provided. Preferably the icosahedral boride layer is comprised of either boron phosphide (B12P2) or boron arsenide (B12As2). The provided method achieves improved film crystallinity and lowered impurity concentrations. In one aspect, an epitaxially grown layer of B12P2 with a base layer or substrate of SiC is provided. In another aspect, an epitaxially grown layer of B12As2 with a base layer or substrate of SiC is provided. In yet another aspect, thin films of B12P2 or B12As2 are formed on SiC using CVD or other vapor deposition means. If CVD techniques are employed, preferably the deposition temperature is above 1050° C., more preferably in the range of 1100° C. to 1400° C., and still more preferably approximately 1150° C.

Abstract: A method for producing a laminate having resin layers and thin metal layers by repeating a process unit comprising a step of laminating a resin layer by applying a resin material, a step of depositing a patterning material on the resin layer and a step of laminating a thin metal layer, predetermined times on a turning support (511), wherein the patterning material is stuck on the surface of the resin layer in a noncontact way. A laminate comprising a large number of laminate units each comprising a resin layer and a thin metal layer divided at an electric insulation stripe part can be produced stably. The laminate is applicable to production of a high performance small capacitor at low cost.

Abstract: A process for producing brightly photoluminescent silicon nanoparticles with an emission spanning the visible spectrum is disclosed. In one aspect, the process involves reacting a silicon precursor in the presence of a sheath gas with heat from a radiation beam under conditions effective to produce silicon nanoparticles and acid etching the silicon nanoparticles under conditions effective to produce photoluminescent silicon nanoparticles. Methods for stabilizing photoluminescence of photoluminescent silicon nanoparticles are also disclosed.

Abstract: The present invention includes a method for creating a reconfigurable nanometer-scale electronic network. One embodiment of the invention is made up of the following steps. The first step entails depositing nanometer-scale electrically conducting islands on an insulating substrate. The next step entails engineering electrically conducting molecules to preferentially attach to the nanometer-scale electrically conducting islands, forming a semi-regular array of current-conducting elements. The next step entails selecting individual nodes for bond breaking by applying electrical currents through two orthogonal molecular filaments, this current heating both the molecules and islands raising the temperature of the current-conducting elements at individual nodes and breaking bonds in accordance with a pre-selected network design. The next step entails repeating the step of selecting individual nodes for bond breaking to produce thereby the nanometer-scale electronic network.

Abstract: A light-emitting element (24) is disclosed. A light emitting diode (LED) includes a sapphire substrate (26) having front and back sides (33, 35), and a plurality of semiconductor layers (28, 30, 32) deposited on the front side (33) of the sapphire substrate (26). The semiconductor layers (28, 30, 32) define a light-emitting structure that emits light responsive to an electrical input. A metallization stack (40) includes an adhesion layer (34) deposited on the back side (35) of the sapphire substrate (26), and a solderable layer (38) connected to the adhesion layer (34) such that the solderable layer (38) is secured to the sapphire substrate (26) by the adhesion layer (34). A support structure (42) is provided on which the LED is disposed. A solder bond (44) is arranged between the LED and the support structure (42). The solder bond (44) secures the LED to the support structure (42).

Abstract: A method of forming an electronic component having elevated active areas is disclosed. The method comprises providing a semiconductor substrate in a processing chamber. The semiconductor substrate has disposed thereon a polycrystalline silicon gate and exposed active areas. The method further comprises performing a deposition process in which a silicon-source gas is supplied into the processing chamber to cause polycrystalline growth on the gate and epitaxial deposition on the active areas. The method further comprises performing a flash etch back process in which polycrystalline material is etched from the gate at a first etching rate and the epitaxial layer is etched from the active areas at a second etching rate. The first etching rate is faster than the second etching rate. The deposition process and the flash etch back process can be repeated cyclically, if desired.

Abstract: A production method of silicon which comprises the steps of bringing a silane into contact with a surface of a substrate so as to cause silicon to be deposited while the surface of the substrate is heated to and kept at a temperature lower than the melting point of the silicon, and raising the temperature of the surface of the substrate so as to cause a portion or all of the deposited silicon to melt and drop from the surface of the substrate and be recovered.

Abstract: A method for making high quality InGaAsN semiconductor devices is presented. The method allows the making of high quality InGaAsN semiconductor devices using a single MOCVD reactor while avoiding aluminum contamination.

Abstract: A method of forming a dielectric layer includes placing a semiconductor wafer in a reaction chamber. Oxygen, hafnium and silicon sources are separately provided to the reaction chamber to react with the wafer. After each source has reacted, a monolayer or near-monolayer film is produced. Each source may also be provided to the reaction chamber a number of times to achieve a film having the desired thickness.

Abstract: Bonding of flip-chip mounted light emitting devices having an irregular configuration is provided. Light emitting diodes having a shaped substrate are bonded to a submount by applying forces to the substrate an a manner such that shear forces within the substrate do not exceed a failure threshold of the substrate. Bonding a light emitting diode to a submount may be provided by applying force to a surface of a substrate of the light emitting diode that is oblique to a direction of motion of the light emitting diode to thermosonically bond the light emitting diode to the submount. Collets for use in bonding shaped substrates to a submount and systems for bonding shaped substrates to a submount are also provided.

Abstract: A method of fabricating a semiconductor device, such as a high electron mobility transistor, a vertical cavity surface emitting laser, an edge emitting laser, a heterostructure bipolar transistor, a resonant tunneling diode, and the like, is disclosed that includes the steps of depositing a plurality of layers of semiconductor material including at least one active area with opposed major surfaces and a cladding layer adjacent each opposed major surface. In the disclosure, the semiconductor material is in an aluminum/gallium arsenide semiconductor system. At least one of the active area and the cladding layers are deposited at relatively low temperatures in the presence of a surfactant, such as antimony, indium, bismuth or thallium to produce greatly improved carrier mobility and surface morphology.

Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.

Abstract: The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, or drain for the transistor. In embodiments of the invention, nickel is blanket deposited over the source, drain, and gate regions of the germanium-based transistor, annealed to cause the nickel to react with the germanium, and wet etched to remove un-reacted nickel from dielectric regions (e.g., shallow trench isolation (STI) regions) but leave NiGe in the source, gate, and drain regions. The wet etch is a mild oxidizing solution at room temperature.

Abstract: Provided are a compound semiconductor crystal substrate capable of reducing planar defects such as twins and anti-phase boundaries occurring in epitaxially grown crystals without additional steps beyond epitaxial growth, and a method of manufacturing the same. A compound single crystal substrate, the basal plane of which is a nonpolar face, with said basal plane having a partial surface having polarity (a partial polar surface). Said partial polar surface is a polar portion of higher surface energy than said basal plane.

Abstract: In one example embodiment, an integrated semiconductor circuit (400) is provided. The integrated circuit (400) comprises a substrate (430) comprising a first material and a first electronic device (455) comprising a first depressed region (415) within the substrate (430) and a set of first device contact locations (475) in a contact level (300). The integrated circuit (400) further comprises a second electronic device 450 comprising a set of second device contact locations (451) in the contact level (300) and a second material (420) in the first depressed (415) region having a lattice mismatch with the first material.

Abstract: In the fabricating of a light emitting device, a light emitting layer portion 24 and a current spreading layer 7, respectively composed of a Group III-V compound semiconductor, are stacked on a single crystal substrate. The light emitting layer portion 24 is formed by a metal organic vapor-phase epitaxy process, and the current spreading layer 7, on such light emitting layer portion 24, is formed to have conductivity type of n-type by a hydride vapor-phase epitaxy process.

Abstract: Disclosed is a method of forming a quantum dots array. In the method of the present invention, a structure of wire-like quantum dots with good quality is formed in materials having an inconsistency in the lattice constant on a tilted substrate by using the binding property of atomic bonding due to chemical bonding steps of the tilted substrate, and the spacing of the wire-like quantum dots is varied by using the step width of the tilted substrate which is transformed due to a partial pressure of a source gas and the thickness of a buffer layer. The invention allows materials having an inconsistency in the lattice constant to be freely formed in the form of quantum wires with a growing technique only and accordingly to be used as base materials in use for manufacture of novel concept of optoelectronic devices which have not been obtained so far.

Abstract: A method for producing a semiconductor device of the present invention includes: heating a first semiconductor layer made of a Group III nitride-based compound semiconductor in gas containing nitrogen atoms; and growing a second semiconductor layer made of a Group III nitride-based compound semiconductor on the first semiconductor layer.

Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

Abstract: One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. The two-step growth produces a lower density of threading defects.

Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.

Abstract: A protector film is formed on the surface of a substrate to cover at least the side surface thereof. Then, a compound semiconductor film including nitrogen is grown through epitaxial growth on the substrate at an exposed portion. Then, the substrate and the compound semiconductor film are separated from each other by irradiation of laser light, polishing of the substrate, etching, cutting, etc. Consequently, the resulting compound semiconductor film is used as a free-standing wafer.

Abstract: Disclosed is a thin film deposition apparatus for depositing a thin film on a display panel including a deposition source having a groove in one surface wherein the groove is filed with a thin film material to be deposited on the panel, a heater applying heat to the deposition source so as to sublimate the thin film material, and a mask loaded on the deposition source so as to cover the groove of the deposition source, the mask having a plurality of holes to adjust a deposition quantity of the thin film material deposited on the panel.

Abstract: A method for making high quality InGaAsN semiconductor devices is presented. The method allows the making of high quality InGaAsN semiconductor devices using a single MOCVD reactor while avoiding aluminum contamination.

Abstract: A vapor-phase growth method for forming a boron-phosphide-based semiconductor layer on a single-crystal silicon (Si) substrate in a vapor-phase growth reactor. The method includes preliminary feeding of a boron (B)containing gas, a phosphorus (P)-containing gas, and a carrier gas for carrying these gases into a vapor-phase growth reactor to thereby form a film containing boron and phosphorus on the inner wall of the vapor-phase growth reactor; and subsequently vapor-growing a boron-phosphide-based semiconductor layer on a single-crystal silicon substrate. Also disclosed is a boron-phosphide-based semiconductor layer prepared by the vapor-phase growth method.

Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.

Abstract: A method for transferring a porous layer includes forming a porous layer on one side of a crystalline silicon member by anodization, fixing a supporting substrate onto the surface of the porous layer, and applying force to any one of the supporting substrate and the porous layer, whereby at least part of the porous layer is cleaved from the crystalline silicon member and is transferred onto the supporting substrate. The crystalline silicon member can be recycled and this method is suitable for mass production of semiconductor devices or solar batteries at low cost.

Abstract: A method for operating a multi-station processing chamber is described. A wafer is loaded onto the first station then indexed to the second station prior to processing. The indexing causes the wafer to be well-seated on it spindle before being processed. This prevents an improperly seated wafer from being processed at the first station.

Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.

Abstract: A stratum or discontinuous monolayer of dielectric-coated semiconductor particles includes a high density of semiconductor nanoparticles with a tightly controlled range of particle sizes in the nanometer range. In an exemplary embodiment, the nanoparticles of the stratum are substantially the same size and include cores which are crystalline, preferably single crystalline, and include a density which is approximately the same as the bulk density of the semiconductor material of which the particle cores are formed. In an exemplary embodiment, the cores and particles are preferably spherical in shape. The stratum is characterized by a uniform particle density on the order of 1012 to 1013 particles/cm2. A plurality of adjacent particles contact each other, but the dielectric shells provide electrical isolation and prevent lateral conduction between the particles of the stratum. The stratum includes a density of foreign atom contamination of less than 1011 atoms/cm2.

Abstract: A single opening is formed in a central portion of a susceptor of a vapor phase epitaxial growth system. Consequently, any dopant diffused off outwardly from the back surface of a wafer during an epitaxial growth process can be exhausted through the opening to the beneath side with respect to the susceptor. As a result, it may become difficult for auto-doping to be induced, even with no protective film formed on a back surface of the wafer. Uniformity in a dopant concentration in the surface may be improved and thus a resistivity may be made uniform. Further, since a temperature of the back surface of the wafer is measured through the opening, a heating temperature can be controlled stably, thus allowing a precise temperature control thereof. Consequently, the epitaxial film as well as the distribution of its resistivity may be made uniform across the entire wafer.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer.

Abstract: A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor having carbon incorporated therein to suppress boron up-diffusion from lower heavily boron-doped buried layers into upper PNP structures. According to an embodiment of the invention, an epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas and pre-baked at a temperature of approximately 850° C. for a time. The temperature is then increased to approximately 1050° C. and subjected to a high temperature bake cycle. A thin carbon-doped epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at approximately 1080° C.

Abstract: A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i.e., utilizing the conventional gallium source) and thin layers (i.e., utilizing the slow growth rate gallium source).

Abstract: The present invention relates to a light-emitting device utilizing amorphous silicon quantum dot nanostructures, wherein the light-emitting device can be fabricated using the existing silicon semiconductor fabrication technology, is excellent in light-emitting efficiency, and can emit light in the visible region including short wavelength region such as green and blue.

Abstract: Systems and methods are described for synthesis of films, coatings or layers using templates. A method includes locating a template within at least one of a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.