Abstract: Cesium is implanted into the gate oxide layer of a vertical trench-gated MOSFET. The cesium, which is an electropositive material, reduces the threshold voltage of the device and lowers the on-resistance by improving the accumulation region adjacent the bottom of the trench.

Abstract: A method for suppressing silicidation retardation effects caused by high dopant concentrations, in particular high Arsenic concentrations, at the surface of a semiconductor substrate. The method includes implanting a preamorphization substance into the substrate to define the boundary of the source/drain, then implanting the dopant at high energy to establish a dopant concentration peak that is distanced from the surface of the substrate. The dopant is activated by rapid thermal annealing, with the relatively deep dopant concentration peak facilitating subsequent improved formation of silicide on the surface of the substrate.

Abstract: A method of forming a pocket implant region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an indium pocket implant region, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, an ion implantation procedure is used to place antimony ions in the indium pocket implant region. The presence of antimony ions limits the broadening of the indium pocket implant profile during subsequent anneal procedures, used to activate implanted ions. Formation of an implanted, lightly doped, N type source/drain region, insulator spacers on the sides of a gate structure, and formation of a heavily doped, N type, source/drain region, complete the process sequence used to form the NMOS, transfer gate transistor.

Abstract: Different symmetrical and asymmetrical devices are formed on the same chip using non-critical block masks and angled implants. A barrier is selectively formed adjacent one side of a structure and this barrier blocks dopant implanted at an angle toward the structure. Other structures have no barrier or have two barriers. Source and drain engineering can be performed for LDD, halo, and other desired implants.

Abstract: In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain side is restrained by the pining regions 105, a short-channel effect can be restrained effectively. Also, because a passage through which carriers move is ensured, high mobility can be maintained.

Abstract: A method to form asymmetric MOS transistors using a replacement gate design. The method involves forming implanted regions (140) and (145) in the channel region after removal of the replacement gate structure (110) to produce high threshold voltage regions and low threshold voltage regions.

Abstract: A method for forming an etching mask structure on a substrate comprises etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotropic or anisotropic. The self-aligned metal layer can be distanced from the original etching masked area based on the extent of the intentionally laterally expanded etching mask layer. Following metal deposition, the initial mask structure can be removed, thus lifting off the metal atop it. The etching mask structure can be a resist and can be formed using conventional photolithography materials and techniques and can have nearly vertical sidewalls. The lateral extension can include a silylation technique of the etching mask layer following etching. The above method can be utilized to form bipolar, hetero-bipolar, or field effect transistors.

Abstract: A method for forming a junction in a semiconductor device including the steps of: forming a photoresist film pattern on a semiconductor substrate excluding a halo implant region; performing a first halo implant process on the halo implant region of the semiconductor substrate by using a tilt angle of about 45°; and performing a second halo implant process on the halo implant region of the semiconductor substrate by using a tilt angle of about 0°.

Abstract: A method of manufacturing a semiconductor device including a PMOS transistor (6) and an NMOS transistor (5) comprises the steps of: (a) providing a semiconductor substrate (1) having a P-well region (3), which is to be provided with the NMOS transistor (5), and an N-well region (2), which is to be provided with the PMOS transistor (6); (b) forming gate electrodes (8) on the P-well region (3) and the N-well region (2); (c) applying a hard mask (10), which covers either the P-well region (3) or the N-well region (2); (d) implanting a source and a drain in the region that is not covered by the hard mask (10), followed by heat activation; (e) implanting pocket implants in the region that is not covered by the hard mask (10), followed by heat activation; (f) removing the hard mask (10).

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and performing a resist flow operation on the semiconductor substrate after implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the resist flow operation on the semiconductor substrate includes baking the semiconductor substrate in an oven at about 100° C. to about 300° C. for about 5 minutes to about 30 minutes to thin down the resist mask and cause the edges of the resist mask to become rounded.

Abstract: The present invention relates to a halo ion implantation method for a semiconductor device, and in a semiconductor device formed of a cell array region with a relatively high concentration of pattern and a peripheral circuit region with a relatively low concentration of pattern. The present invention can improve the data maintenance characteristics by not allowing a source/drain junction in the cell array region to be exposed. In a halo ion implantation method for a semiconductor device of the present invention, a semiconductor substrate having at least one flat zone 31 is prepared, a gate oxide film is formed on the semiconductor substrate, and a plurality of gate electrodes are formed on the gate oxide film. Halo ion implantation is implemented in directions in which a wafer(semiconductor substrate) is horizontally rotated by 45, 135, 225 and 315 degrees at the position of the flat zone when each of the gate electrodes 32a is made arranged in a direction horizontal to the flat zone.

Abstract: A spot-implant method for MOS transistors. An asymmetric masking film (50) is formed on a semiconductor substrate and on a transistor gate (30) with an opening (45) adjacent to the transistor gate (30). A spot region (70) is formed adjacent to the transistor gate (30) by ion implantation (60).

Abstract: A fabrication method for a metal oxide semiconductor transistor is described. A source/drain implantation is conducted on a substrate beside the spacer that is on the sidewall of the gate to form a source/drain region in the substrate beside the spacer. A self-aligned silicide layer is further formed on the gate and the source/drain region. A portion of the spacer is removed to form a triangular spacer with a sharp corner, followed by performing a tilt angle implantation on the substrate to form a source/drain extension region in the substrate under the side of the gate and the spacer with the sharp corner. A thermal cycle is further conducted to adjust the junction depth and the dopant profile of the source/drain extension region.

Abstract: A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.

Abstract: A method for preventing electron secondary injection in a pocket implantation process performed on a nitride read only memory (NROM). The NROM has an oxide-nitride-oxide (ONO) layer formed on a silicon substrate. A plurality of bit line masks, arranged in a column, is formed on the surface of the ONO layer. A plurality of N type bit lines is formed in a region of the substrate not covered by the bit line masks. The method starts by performing a pocket implantation process of Indium ions with low energy, high dosage and using an angle nearly parallel to the ONO layer, so as to prevent electron secondary injection. Also, a plurality of P-type ultra-shallow junctions is formed in the region of the substrate not covered by the bit line masks.

Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

Abstract: A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.

Abstract: A method of fabricating a mask ROM, in which conductive strips are formed with a cap layer on each of them, then a plurality of spacers are formed on the side-walls of the conductive strips, while the substrate under the spacers are used as the coding regions. The buried bit-lines are formed in the substrate between the spacers, then a two-step coding process is performed, wherein the coding regions at the first and the second side of the conductive strips are selectively doped by a first and a second tilt coding implantation with a first and a second coding mask. After the second mask layer and the cap layer are removed, a conductive layer is formed over the substrate, then the conductive layer and the conductive strips are patterned successively to form a plurality of word-lines and plural gates, respectively.

Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

Abstract: A semiconductor substrate has at least one PN junction with dopant atoms at the junction. A non-dopant at the junction provides interstitial traps to prevent diffusion during annealing. In a process for making this, a non-dopant diffusion barrier, e.g., C, N, Si, F, etc., is implanted into the “halo” region of a semiconductor device, e.g. diode, bipolar transistor, or CMOSFET. This combined with a lower annealing budget (“Spike Annealing”) allows a steeper halo dopant profile to be generated. The invention is especially useful in CMOSFETs with gate lengths less than about 50 nm.

Abstract: The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base, to form a base contacting region. A second portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor emitter, to form an emitter contacting region.

Abstract: A method for interconnecting bit contacts and digit lines of a semiconductor device. A mask, through which portions of sidewall spacers of the digit lines located proximate the bit contacts are exposed, is positioned over the digit lines. Dopant is directed toward the semiconductor device at a non-perpendicular angle to a plane of the semiconductor device so as to dope portions of the sidewall spacers on one side of each of the digit lines while sidewall spacers opposed thereto and adjacent bit contacts are shielded from the dopant. Doped regions of the sidewall spacers may be removed with selectivity over undoped regions thereof to expose connect regions of each conductive element of each digit line. A conductive strap may then be formed to electrically link each connect region to its corresponding bit contact. Semiconductor devices including the conductive straps are also disclosed.

Abstract: The present invention provides a method of forming a diffusion layer which extends on bottoms and side walls of trench grooves as well as on top portions of ridged portions separating the trench grooves, and the trench grooves being separated by ridged portions of the substrate so that the trench grooves and the ridged portions are aligned between adjacent two of gate electrode structures, the method comprising the steps of: carrying out a first ion-implantation in a vertical direction to introduce an impurity into the bottoms of the trench grooves and into top portions of the ridged portions by use of gate electrode structures; forming side wall insulation films on side wails of the gate electrode structures; and carrying out a second ion-implantation in an oblique direction with a rotation of the substrate by use of the gate electrode structures and the side walls.

Abstract: Short channel effects are curtailed thereby increasing integrated circuit speed by forming a channel dopant with an asymmetric impurity concentration profile. Embodiments include ion implanting Si or Ge at a large tilt angle to amorphize a portion of a designated channel region with a varying degree of amorphization decreasing from the intended drain region to the intended source region, substantially vertically ion implanting channel dopant impurities and annealing. During annealing, diffusion is retarded in areas of increased amorphization, thereby forming an asymmetric impurity concentration gradient across the channel region increasing in the direction of the source region.

Abstract: A semiconductor device includes a silicon substrate (1), a pair of isolating insulation films (9), a channel region (2), a pair of source/drain regions (3), a pair of silicon oxide films (4) formed on an upper surface of the silicon substrate (1) so as to overlie the source/drain regions (3), and a gate structure (8) formed in a first recess defined by the upper surface of the silicon substrate (1) over the channel region (2) and side surfaces of the pair of silicon oxide films (4). The gate structure (8) includes a gate oxide film (5) formed on the upper surface of the silicon substrate (1), a pair of silicon oxide films (6) formed on lower part of the side surfaces of the pair of silicon oxide films (4), and a metal film (7) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films (4), the silicon oxide films (6) and the gate oxide film (5).

Abstract: An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0° to 60° from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0° to 60° from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

Abstract: A method for implanting ions into a surface of a semiconductor structure covered by a layer of insulating material, for example into a trench wall covered by a layer of oxide. A beam of ions is directed at a glancing angle to the layer of insulating material such that a substantial proportion of ions which are implanted into the semiconductor structure surface are scattered from the beam by the layer of insulating material. It is possible therefore to implant ions into a trench wall without requiring a beam source arranged to deliver a beam at a large angle to the trench wall surface.

Abstract: A method of semiconductor device fabrication comprising forming at least the indentation in a surface of a semiconductor body. The indentation is partially filled with a filler material such that walls of the indentation are exposed above an upper surface of the filler material. First and second dopants are introduced through the exposed walls of the indentation and first and second doped regions formed. The first doped region extends into the semiconductor body around the filled portion of the indentation to a first region boundary which is at a predetermined first depth relative to the upper surface of the filler material. The second doped region extends into the semiconductor body around the filled portion of the indentation to a second region boundary which is at a predetermined second depth relative to the upper surface of the filler material.

Abstract: A method of manufacturing devices with source, drain and extension regions is provided. To achieve in the extensions a depth and dopant levels different from the source and drain regions, a channel-shaped oxide structure is formed surrounding a polysilicon gate. The channel-shaped oxide structures forms an implantation barrier over the extensions region. Thus, when the source and drain implantation is carried out at a given energy, the extension regions receives a 35-40 percent dopant dose, as compared to the dose received by the source region and the drain region.

Abstract: The present invention relates to methods of testing a chip package wherein contact to chip leads is made by a configuration of testing probes in such a manner so as to allow for shorter, tighter-pitch, and more robust chip leads that will not short out into neighboring adjacent chip leads. The present invention also relates to methods of testing a chip package wherein the terminal ends of the chip leads are constrained in a dielectric medium such that package testing may be carried out before final sizing of chip lead lengths.

Abstract: A semiconductor device includes a MOS-type field effect transistor (SOI-MOSFET) formed on a thin silicon layer on an insulator layer. The SOI-MOSFET has a gate overlap-type LDD structure in which additional source/drain regions having an impurity concentration of 3×1017 to 3×1018/cm3 overlapping with a gate electrode are provided in the silicon layer. According to this structure, when the SOI-MOSFET is on operation, only the additional source/drain regions are depleted, so that it is possible to obtain satisfactory transistor characteristics. Additional source/drain regions in this structure are formed by combination of vertical ion implantation using the gate electrode as a mask and thermal diffusion or oblique ion implantation using the gate electrode as a mask.

Abstract: A method of fabricating an IC comprises the steps of: (a) forming trench isolation regions in a surface of a semiconductor body; and (b) forming a tub-tie region between at least one pair of the trench isolation regions (when viewed in cross-section) by a process that includes the following steps: (b1) forming a first photolithographic mask that covers and is in registration with the tub-tie region; (b2) implanting ions of a first conductivity-type to form a tub region adjacent the tub-tie region; (b3) removing the first mask; (b4) forming a second photolithographic mask that has an opening that exposes most of the underlying tub-tie region but overlaps a first peripheral section on one side of the tub-tie region; (b5) implanting ions to form a pedestal portion of a second conductivity-type within the tub-tie region; and (b6) implanting ions of the first conductivity-type at an acute (preferably non-zero) angle −⊕ with respect to the normal to the surface to the body so as to form a conductivity-t

Abstract: A shielding layer 23 is selectively formed on a single crystal silicon layer, an active area 25 is formed in the single crystal silicon layer by using the shielding layer 23 as a mask and an impurity layer 26 is formed at the edges at the sides of the active area 25 by using the shielding layer 23 as a mask and implanting an impurity diagonally from above. As a result, since an impurity layer can be formed by implanting ions of the impurity at the edges at the sides of the active area even when the size of the active area is reduced to the absolute limit, the occurrence of the parasitic transistor phenomenon or the edge transistor phenomenon along the edges at the sides of the active area can be prevented.

Abstract: A spot-implant method for MOS transistors. An asymmetric masking film (50) is formed on a semiconductor substrate and on a transistor gate (30) with an opening (45) adjacent to the transistor gate (30). A spot region (70) is formed adjacent to the transistor gate (30) by ion implantation (60).

Abstract: A method of interconnecting bit contacts to corresponding digit lines of a semiconductor memory device. The method is particularly useful for fabricating semiconductor memory devices having digit lines that are less than about 0.2 microns wide and spaced less than about 0.2 microns apart from one another. A mask, which shields portions of the digit lines of the semiconductor device, through which portions of the digit lines proximate the bit contacts are exposed, is disposed over the semiconductor device. The mask preferably includes elongated apertures alignable transversely to the digit lines. Dopant is directed toward the semiconductor device at a non-perpendicular angle to a plane of the semiconductor device. Thus, portions of the sidewall spacers of one side of each of the digit lines, sidewall spacers on the opposite sides of the digit lines, or the bit contacts may not be exposed to dopant.

Abstract: A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is substantially blocked from the second transistor area (302). The angled implant forms pocket regions in the first transistor area (304). The same masking layer (214) may then be used to implant source and drain extension regions in both the first and second transistor areas (304, 302).

Abstract: A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.

Abstract: The method for fabricating a semiconductor device comprises the steps of forming on a semiconductor substrate a gate electrode, and an eave-shaped film of an inorganic material formed on the upper surface of the gate electrode and having a eave-shaped portion projected beyond the edge of the gate electrode; and ion-implanting a dopant with the gate electrode as a mask and with the eave-shaped portion of the eave-shaped film as a through film to form a first diffusion layer in the semiconductor substrate immediately below the eave-shaped portion and a second diffusion layer which is connected to the first diffusion layer, and is deeper and has a higher dopant concentration than the first diffusion layer, in the semiconductor substrate in a region where the eave-shaped film is not formed.

Abstract: Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10°, and the deflection angle &phgr; is set to such four directions (X, X+90°, X+180°, and X+270°, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.

Abstract: A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).

Abstract: A method for depositing a sacrificial oxide for fabricating a semiconductor device includes preparing p-doped silicon regions on a semiconductor wafer for depositing a sacrificial oxide on the p-doped silicon regions. The method also includes the step of placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the p-doped silicon regions to form a sacrificial oxide on the p-doped silicon regions when a potential difference is provided between the wafer and the solution. Processing the wafer using the sacrificial oxide layer is also included.

Abstract: A semiconductor substrate has a first main surface with a plurality of trenches 5a sandwiching a region in which p and n diffusions regions 2 and 3 are formed to provide a p-n junction along the depth of the trenches. P diffusion region 2 has a doping concentration profile provided by a p dopant diffused from a sidewall surface of one trench 5a, and n diffusion region 3 has a doping concentration profile provided by an n dopant diffused from a sidewall surface of the other trench 5a. A heavily doped n+ substrate region 1 is provided at a second main surface side of p and n diffusion regions 2 and 3. A depth Ld of trench 5a from the first main surface is greater than a depth Nd of p and n diffusion regions 2, 3 from the first main surface by at least a diffusion length L of the p dopant in p diffusion region 2 or the n dopant in n diffusion region 3 in manufacturing the semiconductor device. A high withstand voltage and low ON-resistance semiconductor device can thus be obtained.

Abstract: A device and method to modulate a gate polysilicon doping profile by performing a sidewall implantation. The method includes forming a gate on a substrate and implanting ions through a sidewall in the gate. The ion implantation is performed by projecting the ions at an angle that is not perpendicular to the top surface of substrate and in a direction that is towards the surface of sidewall. The ion implantation process can be performed using a type of dopant that either increases or decreases the net dopant concentration in a gate polysilicon layer in a region of the gate adjacent the sidewall and adjacent a gate oxide layer.

Abstract: A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).

Abstract: One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first dopant material. A halo region is formed in the substrate under the spacer and adjacent to the active region using a second dopant material of a conductivity type different than the first dopant material. The halo region may be formed by implanting the second dopant region into the substrate at an angle substantially less than 90° relative to a surface of the substrate. A portion of the spacer is then removed and a lightly-doped region is formed in the substrate adjacent to the active region and the gate electrode and shallower than the halo region using a third dopant material of a same conductivity type as the first dopant material.

Abstract: In a method is described for producing an MOS transistor structure with elevated body conductivity, a substrate layer is prepared and body regions are formed therein the body regions defining a main surface of the transistor structure and at least one channel region is also formed. Gate oxide and gate electrodes are formed in the region of the main surface, and source regions are formed that extend from the main surface into the body regions. An implantation of dopant of a first conductivity type occurs in at least a part of the channel region, this implantation dosage being controlled such that a re-doping of the body region into an area of the first conductivity type does not occur in the implantation region.

Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.

Abstract: A method for forming a transistor comprises the steps of: forming a gate stack on the surface of a semiconductor substrate; implanting a first dose of an impurity into the substrate at a sufficient energy to penetrate at least a portion of the gate stack to provide a portion of the impurity on the first and second sides of the gate stack, and a portion of the impurity under the gate stack; and forming source/drain regions on the first and second sides of the gate stack. The implant may be at an angle normal to the surface of the substrate at an energy sufficient such that the impurity penetrates the gate stack to reach the channel region. Alternatively, a pair of angled implants at an angle relative to a line normal to the surface of the substrate may be used.

Abstract: A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

Abstract: A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region and a drain extension are formed from two separate tilted ion implantation processes, after the deposition of the gate electrode. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. A second tilted implant process forms a drain extension region under the gate electrode, adjacent the drain. Elimination of LDD areas reduces the number of masking and doping steps required to manufacture a transistor. Further, the drain extension area promotes transistor performance, by eliminating source resistance. At the same time, sufficient doping of the drain extension area insures that the drain resistance through the drain extension remains low.