Abstract: An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpendicular to the main surface of a semiconductor substrate in the sidewall oxide film has a peak at the interface between the semiconductor substrate and the sidewall oxide film. As a result, an interface state at the interface between the sidewall oxide film and the main surface of the semiconductor substrate is suppressed, resulting in decrease of the probability at which hot carriers are trapped in the interface state. Accordingly, the hot carrier resistance is improved.

Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening.

Abstract: Drain and source extensions that are abrupt and shallow and that have high concentration of dopant are fabricated for a field effect transistor, using a laser thermal process. A drain amorphous region is formed by implanting a neutral species into a drain region of the field effect transistor at an angle directed toward a gate of the field effect transistor such that the drain amorphous region is a trapezoidal shape that extends to be sufficiently under the gate of the field effect transistor. A source amorphous region is formed by implanting the neutral species into a source region of the field effect transistor at an angle directed toward the gate of the field effect transistor such that the source amorphous region is a trapezoidal shape that extends to be sufficiently under the gate of the field effect transistor. A drain and source dopant is implanted into the drain and source amorphous regions at an angle directed toward the gate of the field effect transistor.

Abstract: A method of forming a gate electrode with a titanium polycide which can prevent particle creation and abnormal oxidation of the gate electrode, is disclosed. In the present invention, a gate oxidation process is performed after implanting Si ions into the side wall or overall surface of the titanium silicide layer, thereby preventing abnormal oxidation of the titanium silicide during the gate oxidation process. Furthermore, a titanium silicide layer is deposited to a low mole ratio of Si/Ti, thereby minimizing particle creation.

Abstract: A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or both.

Abstract: The inventive method and apparatus provides improved semiconductor devices, such as MOSFET's with a delayed threshold voltage roll-off and short channel effects, making the semiconductor devices more tolerant of gate variations for short gate length devices. The invention provides a semiconductor device with an asymmetric channel doping profile. A first pocket dopant implantation with a 0° tilt is used to create a first source dopant pocket and a drain dopant pocket. A second pocket dopant implantation with a 30-60° tilt creates a second source dopant pocket without creating an additional drain dopant pocket, thus creating the asymmetric doping profile.

Abstract: The method for fabricating a semiconductor integrated circuit device disclosed includes the steps wherein an active region is defined so as to be surrounded by an insulating film on a silicon substrate, a surface of the active region and a semiconductor layer that extends underneath the insulating film are changed to an amorphous state by implantation of ions from oblique angles, a metal film is formed over the silicon substrate, and a metal silicide layer is formed by a thermal-treatment causing the metal film and silicon in the amorphous state to react with each other. In this way, it is possible to form a sufficiently thick silicide layer even on a narrow line width diffusion layer.

Abstract: A highly reliable semiconductor device and a manufacturing method thereof are provided, without lowering the mobility of carriers, by increasing the nitrogen concentration of part of a gate insulating film. Nitrogen containing regions containing nitrogen are provided on both end portions of a gate insulating film which is formed into a uniform thickness.

Abstract: A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative proximal to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate.

Abstract: The triple-well according to the present invention reduces a photo process forming a well isolation region which is used in a method for forming a prior well. That is, two times of photo processes are reduced to be one time, thereby simplifying a method for forming a triple-well of the DRAM device and reducing time and expenditure.

Abstract: A semiconductor device includes a substrate, a gate structure, a plurality of sidewall spacers, and a plurality of first silicide layers. The gate structure is positioned above the substrate. The plurality of sidewall spacers are positioned adjacent to the gate structure. The first silicide layers are positioned in the substrate and have first ends that extend underneath the sidewall spacers. A method for forming a semiconductor device includes forming a gate structure above a substrate. A plurality of sidewall spacers are formed adjacent the gate structure. An implant material is disposed into the substrate using a tilted implantation process that is adapted to form first implant regions in the substrate. The implant regions have first ends that extend underneath the sidewall spacers by a first distance.

Abstract: A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction suitable for Fowler-Nordheim tunneling on each side of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit line.

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate which lies in an x-y plane, the method comprising the steps of: forming a semiconductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); amorphizing a portion of the conductive structure by introducing an amorphizing substance into the semiconductive structure at an angle, theta, which is greater than seven degrees from a z-axis which is normal to the semiconductor substrate (step 310 of FIG. 3); forming a metal layer on the conductive structure (step 312 of FIG. 3); and wherein the metal layer interacts with the semiconductive structure in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure (step 314 of FIG. 3).

Abstract: A method for making a ULSI MOSFET chip includes masking areas such as transistor gates with photoresist mask regions. Prior to ion implantation, the top shoulders of the mask regions are etched away, to round off the shoulders. This promotes subsequent efficient quasi-vertical ion implantation, commonly referred to as “high aspect ratio implantation” in the semiconductor industry.

Abstract: In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

Abstract: A channel region is formed in a device after the source and drain regions are formed by implanting ions into the channel region with a tilt angle using multiple rotations. A rapid thermal annealing step is performed to activate the channel dopant. Because the source and drain regions are already formed, a relatively low temperature, e.g., 990 to 1010 degrees Celsius, and short, e.g., 1 to 5 seconds, rapid thermal annealing step may be performed to activate the channel region. Thus, the dopant concentration in the channel region may be well localized and accurately controlled.

Abstract: A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in an oxide layer is defined and partially filled by insertion of nitride spacers to define an actual gate window opening. The small angle tilted implant technique has the equivalent doping effect of large angle tilted implants, and circumvents the maximum angle limit (&thgr;MAX) that occurs in the large angle implant method. The small angle tilted implant technique also automatically provides self alignment of the pocket/halo/extension implant to the gate of the device.

Abstract: A method of fabricating a high voltage semiconductor device. A semiconductor substrate doped with a first type dopant and comprising a gate is provided. A cap oxide layer is formed on the gate optionally. A first ion implantation with a light second type dopant at a wide angle is performed to form a lightly doped region. A spacer is formed on a side wall of the gate. A second ion implantation with a heavy second type dopant is performed, so that a heavily doped region is formed within the lightly doped region.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: Channel doping is implemented such that dopants remain localized under the gate without migrating under the source/drain juctions during processing, thereby avoiding performance degradation of the finished device. Embodiments include implanting impurities at an acute angle to form a lateral channel implant localized below the gate after activation of source/drain regions, and activating the lateral channel implant by a low-temperature RTA during subsequent metal silicide formation. The use of a low-temperature RTA for electrical activation of the lateral channel implant avoids impurity migration under the source/drain junctions, thereby lowering parasitic junction capacitance and enabling the manufacture of semiconductor devices exhibiting higher circuit speeds with improved threshold voltage control.

Abstract: A semiconductor device in which a salicide structure is applied to a buried gate transistor to largely reduce a difference of level or height in a element and to reduce the resistance of a gate electrode and a source/drain structure, thus enabling reliable high speed operations while maintaining high performance. For manufacturing the semiconductor device, a silicon substrate is formed with a groove for a buried gate. A gate insulating film is formed on the bottom surface of the groove. Then, side-wall insulating films are formed on both side surfaces of the groove in a large thickness as compared with that of the gate insulating film. Next, after a gate electrode is formed from a polycrystalline silicon film, a source/drain structure is formed in the silicon substrate through the gate electrode and the side-wall insulating film. Then, a Ti film is formed and annealed to form silicide layers on the gate electrode and on the source/drain electrodes, thus completing a salicide structure.

Abstract: A nonvolatile semiconductor memory device having a semiconductor substrate of a first conductive type, a floating gate and a control gate provided on the semiconductor substrate, at least a pair of impurity diffusion layers of a second conductive type defining source and drain and disposed in the semiconductor substrate in a spaced relation to each other so as to define a channel having a region covered with the floating gate and a region uncovered with the floating gate, the region uncovered with the floating gate defining a split gate, a first impurity diffusion layer region formed in the semiconductor substrate so as to be disposed at least at an area between the pair of diffusion layers, and a second impurity diffusion layer region having an impurity concentration lower than the first impurity diffusion layer region and formed in the semiconductor substrate so as to be disposed at the split gate.

Abstract: An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpendicular to the main surface of a semiconductor substrate in the sidewall oxide film has a peak at the interface between the semiconductor substrate and the sidewall oxide film. As a result, an interface state at the interface between the sidewall oxide film and the main surface of the semiconductor substrate is suppressed, resulting in decrease of the probability at which hot carriers are trapped in the interface state. Accordingly, the hot carrier resistance is improved.

Abstract: A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.

Abstract: A P-type dopant is implanted into a substrate region 94 under a select drain gate transistor field oxide region 75 at a large tilt angle .alpha., to prevent field turn-on under the select drain gate transistor field oxide region 75 in a non-volatile memory device such as a NAND flash memory device. A substrate region 114 under a select source gate transistor field oxide region 77 can also be implanted with a P-type dopant to prevent field turn-on under the region 77 if select source gates 90 and 92 are to be supplied with a voltage in operation rather than grounded. The substrate regions 94 and 114 under both the select drain gate transistor field oxide region 75 and the select source gate transistor field oxide region 77 can be implanted with the P-type dopant using a fixed-angle ion beam 120, by rotating the wafer 124 between the step of implanting one of the substrate regions and the step of implanting the other region.

Abstract: Semiconductor processing methods, semiconductor processing methods of forming diodes, and semiconductor processing methods of forming Schottky diodes are described. In one embodiment, a first layer of material is formed over a substrate. A second layer of material is formed over the first layer of material. An opening is formed to extend through the first and second layers sufficient to expose a portion of the substrate. An angled ion implant is conducted through the opening and into the substrate. After the conducting of the angled ion implant, the second layer of material is removed. In another embodiment, a diode opening is formed in a layer of material over a semiconductive substrate. In another embodiment, a Schottky diode is formed by forming an opening in a layer of material which is formed over a semiconductive substrate, wherein the opening exposes a substrate portion. An angled ion implant is conducted through the opening and into the semiconductive substrate. A conductive layer of material, e.g.

Abstract: Various methods of fabricating a silicide layer, and devices incorporating the same are provided. In one aspect, a method of fabricating a silicide layer on a substrate is provided. The method includes the steps of damaging the crystal structure of a portion of the substrate positioned beneath the spacer and depositing a layer of metal on the substrate. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer, whereby a portion of the silicide layer extends laterally beneath the spacer. Any unreacted metal is removed. The method enables fabrication of silicide layers with substantial lateral encroachment into LDD structures, resulting in lower possible source-to-drain resistance and enhanced performance for transistors.

Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.

Abstract: A memory cell having an asymmetric source and drain connection to virtual ground bit-lines. A main diffusion, adjacent the drain and displaced from the source, allows Fowler-Nordheim (FN) tunneling erasure on the drain side of the floating gate. A pocket diffusion, between the main diffusion and the source, concentrates the electric field and thereby enhances the efficiency of programming by electron injection on the source side of the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells, in which adjacent columns of cells share a single virtual ground bit line.

Abstract: A process for forming implanted regions at an optimal location in a semiconductor substrate underneath a patterned polysilicon gate of an MOS transistor. The process includes steps of first providing a semiconductor substrate (e.g. a silicon wafer) with a gate oxide layer on its surface, followed by the formation of a polysilicon gate layer on the gate oxide layer. An additional oxide layer is subsequently formed on the polysilicon gate layer. The resulting structure is then patterned to form a patterned additional oxide layer and a patterned polysilicon gate layer, all of which are subsequently covered by a conformal silicon nitride layer. Next, the conformal silicon nitride layer is anisotropically etched to form spacers on the sidewalls of the patterned structure.

Abstract: An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. The memory cell has a source and a drain. The method and system include providing a source implant in the semiconductor, providing a pocket implant in the semiconductor, and providing a drain implant in the semiconductor after the pocket implant is provided. Thus, short channel effects are reduced.

Abstract: A method is provided for forming a triple well of a semiconductor memory device, where a second well of a second conductive type encloses a second well of a first conductive type. A single mask is used for ion implanting the base of the enclosing well and also the entire enclosed well, which inherently avoids misalignment. Additional doping is provided to the location where the sidewalls of the enclosing well join its base. This is accomplished either by a second, deeper ion implant of the sidewalls, or by ion implanting the base at an angle and rotating it, or both. Alternately, the single mask pattern is processed between the ion implantation steps to alter its width.

Abstract: There is provided a MOS device with self-compensating threshold implant regions and a method of manufacturing the same which includes a semiconductor substrate, a partial first threshold implant forming a higher concentration layer, a gate oxide formed on the surface of the higher concentration layer, and a gate formed on a surface of the gate oxide. The MOS device further includes a second threshold implant for forming self-compensating implant regions in the substrate which is subsequently heated to define pockets. A third implant is performed to create lightly-doped source/drain regions. A sidewall spacer is formed on each side of the gate. A fourth implant is performed to create highly-doped source/drain regions between the lightly-doped source/drain regions and the pockets.

Abstract: The method of manufacturing a CMOS transistor according to the present invention comprises the steps of forming a field oxide at a selected region on a semiconductor substrate to isolate a first region for a NMOS transistor from a second region for a PMOS transistors; forming a P-well region and a N-well region in the first and second regions, respectively; forming a gate oxide film and a gate electrode on selected regions of the first and second regions; implanting low concentration N-type impurities ions to form low concentration impurity implantation regions within the first and second regions; forming spacers at said side walls of the gate electrode and the gate oxide film; forming a high concentration implantation region in the first and second regions; and implanting N-type impurity ions into the second region to form a punch stop doping layer below said low concentration impurity implantation region of the second region.

Abstract: A thick oxide layer is formed over a drain region of an MOS transistor while a thin oxide layer is provided over the source and channel regions. As a result both improved current driving ability and reduced gate induced drain leakage current are achieved.

Abstract: A method of producing an asymmetrical semiconductor device with ion implantation techniques and semiconductor devices constructed according to this method in which a barrier of ion absorbing material of height h is positioned beside a structure on a semiconductor surface. The barrier is located at a maximum distance d from one side of the structure, and an angled ion implant is directed at the side of the structure. The maximum distance d of the barrier from the side of the structure is equal to the height of the barrier h divided by the tangent of the angle of the ion implant so that the side of the structure is shadowed from the ion implant. A second ion implant is directed to the opposite side of the structure on the semiconductor surface, thereby forming a desired implant and producing the asymmetrical semiconductor device.

Abstract: The present invention provides a method of manufacturing MOS device having threshold voltage adjustment region 28 ormed using a large angled implant. The invention's angled implant serves as both (a) a Vt adjustment I/I and (b) a Channel stop I/I by (1) increasing the threshold voltage (Vt) and (2) reducing the leakage current. The method comprises forming spaced field oxide regions having bird's beaks on a semiconductor substrate. A field implant is performed using the spaced field oxide regions as an implant mask formed a deep channel stop region 24. Next, a sacrificial oxide layer 20 is formed over the resultant surface. In a critical step, a threshold voltage adjustment region 28 is formed by performing a large angled implant of a p-type ions. The p-type ions into are implanted into the channel region 19 and under the bird's beak 18 such that the threshold voltage is higher under the bird's beak than in the channel region 19. A MOS transistor is then formed over the channel region.

Abstract: In producing a top gate type or a bottom gate type thin film transistor (TFT), after a metal film for forming silicide is formed on a semiconductor active layer provided on an insulating surface, an N-type or P-type impurity ion is introduced into the semiconductor active layer using an anodizable gate electrode and an anodic oxide formed on the surface of the gate electrode as masks. The exposing portion of the semiconductor active layer is reacted with the metal film, so that a silicide layer is formed in the portion. Then, non-reacted portion of the metal film is removed.

Abstract: A process for the manufacturing of integrated circuits provides for forming contacts between a conductive material layer and first doped regions of a semiconductor substrate in a self-aligned manner to edges of an insulating material layer which defines active areas of the integrated circuit wherein the doped regions are formed, and second doped regions of the same conductivity type as the first doped regions under the first doped regions, the second doped regions extending partially under the edges of the insulating material layer to prevent short-circuits between the conductive material layer and the semiconductor substrate. The second doped regions are formed by means of implantation of dopants along directions slanted with respect to an orthogonal direction to a surface of the semiconductor substrate at angles and with an energy sufficiently high to make the dopants penetrate in the semiconductor material deeper than the first doped regions and under the edges of the insulating material layer.

Abstract: A method of implanting dopants within an exposed first active region on a semiconductor substrate of a semiconductor wafer without doping an exposed second active region of the semiconductor substrate. A barrier wall is formed adjacent to the second active region and projects from the semiconductor substrate to a height above the second active region. A minimal angle relative to an axis perpendicular to the semiconductor substrate is determined at which doping ions directed at the semiconductor substrate must travel so that the barrier wall blocks the doping ions from contacting the second active region. The doping ions are used to bombard the semiconductor substrate at an angle at least as large as the minimal angle previously determined. As a result, the doping ions contact the first active region but do not substantially contact the second active region. The width of the second active region can be formed as greater than that of the first active.

Abstract: A MOS device is provided with a reduced source and drain area. This is accomplished by first providing a MOS device with a buried gate region. The buried gate region is located on top of a channel region, which runs horizontally along the bottom of the gate trench. The source and drain regions are aligned vertically an parallel to the outside sidewalls of the buried gate region. Sidewall protectors are provided between the gate and lateral source and drain regions on the inside sidewalls of the gate trench. Additionally, a process for manufacturing the above described device is also disclosed.

Abstract: A semiconductor device having a nitrogen-rich active region-channel interface and process for fabrication thereof is provided. The nitrogen-rich interface can, for example, can reduce the electric field potential in this region and reduce hot carrier injection effects. Consistent with one embodiment of the invention, a semiconductor device is provided having a substrate, at least one gate electrode disposed over the substrate and an active region disposed adjacent to gate electrode. The semiconductor device further includes a channel region extending from the active region beneath the gate electrode and a nitrogen-rich region disposed at an interface between the channel region and the active region. The nitrogen-rich region may, for example, be disposed at least in part in the channel region. The nitrogen-rich region may, for example, also be disposed at least part of the active region. Further, the active region may be disposed, for example, within the nitrogen-rich region.

Abstract: A method for manufacturing shallow trench isolation structure in a substrate, in which by forming a doped region at the upper corners of a trench, the degree of oxidation in that region increases when the liner layer is formed over the exposed surface of the trench. Therefore, thickness of the liner layer at the upper corner regions of the trench is almost the same as in other regions. Consequently, a kink effect is prevented when a gate is subsequently formed over the active region of the substrate.

Abstract: A dual bit read only memory cell has two bits separately stored in two different areas of the channel, such as the left and right bit line junctions of the channel. A programmed bit has a threshold pocket implant self-aligned to its bit line junction and an unprogrammed bit has no such implant. An array of such cells is manufactured by laying down a bit line mask and separately programming the two bit line junctions. For each bit line junction, the bit line junctions which are to remain unprogrammed are first covered, with a junction mask, after which the array is exposed to a threshold pocket implant at a 15-45.degree. angle, to the right or to the left. The junction mask is removed and the process repeated for the other bit line junction. Finally, the bit line mask is removed. In an alternative embodiment, the threshold pocket implant is two implants, of two different materials.

Abstract: A method of forming electrical elements on the sidewalls of deformable micromechanical structures such as flexible, high aspect ratio beams. The micromechanical structure is made of a semiconductor material such as silicon. The method includes angled ion implantation at an angle nonnormal to the substrate surface. The angle ensures that ions are implanted into appropriately oriented sidewalls. Multiple ion implantations can be performed to form electrical elements into different sidewalls. Masking techniques can be used to restrict the locations where ions are implanted. Alternatively, several different types of ion diffusion can be used to expose the sidewall in selected regions. The present invention can form conductive pathways which are continuous between perpendicular surfaces. This enables electrical elements on vertical surfaces to communicate with electronics on horizontal surfaces, for example. The dopant ion concentration and ion species can be controlled to form many different electrical elements.

Abstract: A novel structure of TFT is described. In the structure of TFT, an anodic oxidation film, which is a material composing a gate electrode, is laid at the side of gate electrode. An electrode, which is connected to a source, drain region, is in contact with the upper surface and the side of the source, drain region, and extended on the upper surface of an insulation film which is laid on the gate electrode. In the preparation process of TFT, it can be completed by using only two sheets of mask.

Abstract: A semiconductor device and a method for fabricating the same suitable for increasing its tolerance and packing density are disclosed, the semiconductor device including a semiconductor substrate having a field region placed lower than surface of an active region; an isolation layer formed at the field region; a gate insulating layer and a gate electrode successively formed over the active region; and impurity regions formed in the exposed active region at both sides of the gate electrode.

Abstract: An integrated semiconductor logic gate apparatus having optimized asymmetric channel regions and method for fabricating the apparatus is disclosed. The fabrication process includes ion-implanting the drain side of the channel to produce asymmetric channels on the gate transistors by using a criss-cross form of ion implantation. The criss-cross ion-implantation is performed after formation of the multiple gate stacks and is facilitated by a patterned photoresist mask that leaves an open, unprotected region above adjacent gate stacks through which the ion-implantation is performed. The criss-cross ion-implantation includes two tilt angles that are determined by tangent expressions that factor the height of the photoresist mask, the width of the unprotected opening over pairs of gate stacks and the width of the channel regions, including a distance relating to the point where the source/drain potential barrier is a minimum beneath the overlying gate stack.

Abstract: The present invention proves a method and apparatus for manufacturing a polysilicon TFT without a defective activated area in a channel region below a gate. According to the instant invention, a dopant is implanted into a polysilicon thin film formed on an substrate with a gate having a tapered edge which is used as a mask to form a source and a drain. An energy beam then slantingly irradiates from the side of the edge of the gate to the surface of the substrate. Thus, the source and drain are activated and, at the same time, the energy beam streams into the polysilicon thin film below the edge of the gate to activate the channel region implanted the dopant.