Abstract: A method is provided for improving silicide formation, and the electrical ntact provided thereby, on non-planar silicon structures. In this method, a semiconductor device structure is initially formed having non-planar surface regions. A metal layer is deposited on the non-planar surfaces. The metal deposition process step is followed by an off-axis implantation of non-dopant ions, causing a mixing of the metal and silicon atoms at the metal and non-planar silicon structure interface. The off-axes implantation also serves to disrupt the native silicon dioxide layer between the silicon and metal layers regions. Thermal processing is then used to form silicide on the non-planar surfaces of the semiconductor silicon structure.

Abstract: A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.

Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

Abstract: A semiconductor memory device and a fabrication method thereof include formation of surplus gates connected to a cell node of a gate edge region, located at a cell node side of a SRAM access transistor, and to the gate of a driving transistor located at the opposite side thereof. The present invention prevents silicon loss of the substrate caused by the formation of a buried contact in the conventional device, secures an operational stability of the memory cell by controlling differently the current flow of an access transistor in accordance with the condition of the cell node (for example, low level or high level), and facilitates an interconnection in the cell since the gate of a side transistor is used as a substitute for another interconnection (for example, a wiring) when realizing a SRAM.

Abstract: The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.

Abstract: Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130). A second gate electrode (140) may be formed substantially perpendicular to the first gate electrode (124) and separated from a second active area (142) of the semiconductor layer by a second gate insulator (146). A masking layer (160) may be formed over the semiconductor layer (112) and expose a source and a drain section (162 and 164) of the first active area (126) and a source and a drain section (166 and 168) of the second active area (142). Dopants may be implanted from a first direction substantially parallel to the first gate electrode (124) into the source and drain sections (166 and 168) of the first active area (126).

Abstract: A method of forming a self-aligned halo-isolated well with a single mask is disclosed. First, a layer of resist is disposed over at least a portion of a substrate's surface. Then, an impurity of a first polarity type is implanted at an angle into the substrate through a gap in the layer of resist, thus forming a well having the impurity of the first polarity, which extends beneath the layer of resist. An impurity of a second polarity type is also implanted, using the same mask as previously used. The second implantation forms a well of the impurity of the second polarity disposed within the well of to impurity of the first polarity.

Abstract: An element isolator is formed in a silicon substrate. A gate oxide film and a gate electrode are formed overlying the silicon substrate. Subsequently, a four-step large-tilted-angle ion implant is performed in which ions of nitrogen are implanted at an angle of tilt of 25 degrees, to form an oxynitride layer at each edge of the gate oxide film and to form a nitrogen diffusion layer in the silicon substrate. This is followed by formation of a lightly-doped source/drain region by means of impurity doping. A sidewall is formed on each side surface of the gate electrode, which is followed by formation of a heavily-doped source/drain region by impurity doping. The present invention provides an improved semiconductor device having high-performance, highly-reliable MOS field effect transistors and a method for fabricating the same.

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56).

Abstract: The present invention relates to a method of manufacturing MOS components having lightly doped drains wherein the implanting type ion used is different than that used in the formation of the source/drain regions. The present invention also includes the use of a tilt implantation angle accompanied by substrate rotation during the implantation process to form lightly doped drain structures on two sides of the source/drain regions. The mask is the same for the formation of the source/drain regions as that for the formation of the lightly doped drain regions. The method of manufacturing MOS components having lightly doped drains according to this invention has fewer manufacturing processes for the formation of spacers than the conventional methods. Moreover, the reduction in spacer production results in an increased contact surface area for subsequent contact window formation, thereby lowering contact resistance.

Abstract: A method to form, in a NMOS area, a shallow trench isolation (STI) having B doped sidewalls regions 44 to reduce the NMOS reverse narrow width effect in narrow active areas 12N (e.g., narrow channel regions <0.1 .mu.m wide). A substrate is provided having a NMOS area 13 and a PMOS area 15. A pad oxide layer 20 and a barrier layer 22 are formed on the substrate. Trenches 24 are etched in the substrate 10 in the NMOS and PMOS areas. The etching forms narrow active areas 12N and wide active areas 12W. The narrow active areas 12N have a width between 0.4 and 1.0 .mu.m. A liner layer 30 is grown on the sidewalls and bottom of the trench on the substrate. A first photoresist layer is formed covering the PMOS areas and having first opening over the NMOS areas. In a critical step, a large angle Boron implantation is performed into the sidewalls and the bottom of the trenches forming Boron doped regions 44 in the substrate. The first photoresist layer is removed.

Abstract: A method is described which forms an MOS transistor having a narrow diffusion region that is smaller than the diffusion region defined using photoresist in a conventional CMOS processing. In one embodiment, LOCOS can be used to form isolation (e.g., shallow trench) between active devices. A polysilicon layer is then deposited and doped either n+ or p+ selectively. The polysilicon layer is then patterned. Next, a dielectric layer and a refractory layer are deposited over the patterned polysilicon layer. Next, a contact hole with a high aspect ratio is defined in the oxide where the transistor will be formed. Angled implant of lightly-doped drain (LDD) regions or graft source/drain regions are formed on two opposite sides of the contact hole. The refractory metal layer is then removed. Spacers are then formed on opposite sidewall of the contact hole. A gate oxide layer is either thermally grown or deposited in the contact, before or after spacer formation.

Abstract: Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

Abstract: Generation of parasitic transistor in active layer edge is prevented. In an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.

Abstract: A zero thermal budget manufacturing process for a MOS-technology power device.

Abstract: On a semiconductor substrate, a floating gate electrode composed of a first layer of polysilicon is disposed through a gate dielectric film, and the drain diffusion layer contacts with the floating gate electrode by self-alignment. The source diffusion layer is disposed to have an offset. The control gate electrode is formed through the ON film and second gate dielectric film on the floating gate electrode. The control gate electrode is formed to cover the offset region. The first gate dielectric film is formed entirely of the tunneling dielectric film at least in the region beneath the floating gate electrode. In such constitution, an electrically erasable and programmable semiconductor memory device small in cell area and excellent in matching with other process may be obtained.

Abstract: A method is achieved for forming buried contacts with diffused contact regions on semiconductor integrated circuits having low sheet resistance between the buried contacts and the field effect transistors. The method also allows for greater misalignment tolerances that prevent trenching or electrical opens from occurring in the diffused contact regions when etching the polycide interconnecting lines over the contacts. The method utilizes the etch back of an opening in the photoresist contact mask and a subsequent angular implant to extend the diffused contact regions to reduce the sheet resistance between the buried contacts and the FETs. The method is especially useful for electrically connecting the drain of the pass transistor to the gate of the pull-down transistor on static RAM devices.

Abstract: The method includes the following steps: delimiting active areas on a substrate, forming gate electrodes insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation to a reference line on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length, the widths of the gate electrode strips are determined at the design stage in relation to the orientation of the strips to the reference line and on the orientation of the directions of the implant beams.

Abstract: A semiconductor fabrication process comprising forming a dielectric on an upper surface of a single crystal silicon substrate. A trench mask is then patterned on an upper surface of the dielectric. The trench mask exposes portions of the dielectric situated over portions of the isolation region. Exposed portions of the dielectric are then removed and portions of the silicon within the isolation region are also removed to form an isolation trench within the silicon substrate. This formation results in the formation of corners in the silicon substrate where the upper surface of the silicon substrate intersects with sidewalls of the isolation trench. Localized damage is then created in regions proximal to these corners of the silicon substrate preferably through the use of one or more ion implantation processes performed at implant angles in excess of approximately 30.degree. C.

Abstract: An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpendicular to the main surface of a semiconductor substrate in the sidewall oxide film has a peak at the interface between the semiconductor substrate and the sidewall oxide film. As a result, an interface state at the interface between the sidewall oxide film and the main surface of the semiconductor substrate is suppressed, resulting in decrease of the probability at which hot carriers are trapped in the interface state. Accordingly, the hot carrier resistance is improved.

Abstract: A semiconductor device having a shallow trench isolation structure, where the upper part of the trench is broader than the lower part of it, comprises an insulating layer on the sidewalls of the upper part of the trench, another insulating layer buried in the trench for isolating semiconductor devices and low-concentration doped regions near the upper part of the trench and high-concentration doped regions near the lower part of the trench. Therefore, the leakage current is prevented due to the sufficient amount of the ions in the high-concentration doped regions near the lower part of the trench and the narrow width effect is minimized owing to the insulating layer on the sidewalls of the upper part of the trench.

Abstract: In fabricating a bipolar transistor, semiconductor dopant is introduced into a semiconductor body during a base doping operation to define a doped region, that forms a PN junction with adjoining semiconductor material and abuts a slanted sidewall of a field insulating region. The doped region constitutes a base region for the transistor. The base doping operation entails ion implanting the dopant into the body at a tilt angle of at least 15.degree. relative to the vertical. The minimum lateral base thickness and, the minimum sidewall base thickness increase relative to the minimum vertical base thickness. As a result, the magnitude of the collector-to-emitter breakdown voltage typically increases. The minimum lateral, sidewall, and vertical base thicknesses vary with the tilt angle and base-implant energy in such a manner that the minimum lateral base thickness and the minimum sidewall base thickness are separately controllable from the minimum vertical base thickness.

Abstract: A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to form an opening. The buffer oxide layer within the opening is removed and another oxide layer is formed at the same place as a gate oxide layer. A poly-gate is formed at the opening with a wider width than the opening. Thus, a part of the poly-gate at both ends covers a part of the silicon nitride layer. The silicon nitride layer is then removed and leaves the poly-gate as a T-shape with two ends suspended over the substrate. With a large angle, a light dopant is implanted into the substrate under the suspended part of the poly-gate to form a lightly doped region. With another smaller angle, a heavy dopant is implanted into the substrate beside the poly-gate. Therefore, a source/drain is formed.

Abstract: A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger I.sub.d currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.

Abstract: Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-germanium (poly-SiGe) of a non-uniform Ge concentration on the substrate structure. The method further includes forming source and drain regions within the substrate structure, the drain region having a different threshold voltage than the source region. In a further aspect, a Flash EPROM cell with an adjustable threshold voltage includes a substrate structure as a foundation for the cell. The cell further includes a gate structure on the substrate structure, the gate structure comprising a floating gate layer of polysilicon-germanium (poly-SiGe) of non-uniform Ge concentration.

Abstract: A method of forming a buried contact junction without forming a buried contact trench and without a disconnection gap in the current path by using a tapered polysilicon profile and a large angle tilt buried contact implant is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate wherein the first polysilicon layer is tapered such that the bottom of the opening has a width the size of the planned buried contact and wherein the top of the opening has a width larger than the size of the planned buried contact. Ions are implanted at a tilt angle into the substrate within the opening whereby the ions penetrate the substrate laterally underlying with said first polysilicon layer to form the buried contact.

Abstract: A semiconductor device (20) is fabricated by doping a dielectric layer (29) located over the surface of a semiconductor substrate (21). The dielectric layer (29) contains nitrogen and is doped with silicon ions by using an ion implantation process (15) such that a peak concentration (32) of the silicon ions remains in the dielectric layer (29) during the ion implantation process (15). Doping the dielectric layer (29) reduces charge trapping in the dielectric layer (29) and reduces power slump in the semiconductor device (20) during high frequency operation.

Abstract: In a semiconductor employing shall trench isolation, a subtrench conductive layer formed before the isolation dielectric is present by implanting dopants into the floor and sidewalls of the shallow trench using a large tilt angle (LTA) implant. The subtrench conductive layer is advantageously used to interconnect what would normally be isolated devices. In lieu of metal or polysilicon interconnects which reside over the isolation dielectric, the subtrench conductive layer is formed entirely within the silicon substrate, and resides beneath and laterally adjacent the isolation dielectric. The conductive layer is formed by implanting ions into the floor and sidewalls of a shallow trench prior to filling the trench with the isolation dielectric. The implantation at specified dosages presents a layer of dopant within the exterior surfaces of the trench sidewalls and floor. Implantation or diffusion of source/drain regions occur after the conductive layer is formed and the isolation dielectric is formed.

Abstract: The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.

Abstract: In a charge coupled device (CCD) comprising a semiconductor substrate having a channel layer therein and a gate insulator thereon, a plurality first electrodes arranged in charge transfer direction on the gate insulator with inter-electrode spaces defined by opposite sidewalls of the first electrodes, an interlayer insulators covering the outer surfaces including the sidewalls of the first electrodes, a plurality of second electrodes formed at the inter-electrodes spaces, and a potential barrier region formed in the channel layer under the inter-electrode spaces, each of the sidewalls are tapered to diverge the inter-electrode space upwardly from the gate insulator so that each of the first electrodes has a thin portion at the tapered sidewall. In boron injection to form the potential barrier region using the first electrodes as a mask.

Abstract: A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type; a first MOS transistor provided on the second region; and a second MOS transistor provided on the first region. In such a complementary semiconductor device, at least one of the first MOS transistor and the second MOS transistor is an asymmetric MOS transistor of the same conductivity type as the conductivity type of the corresponding region which is either the first region or the second region.

Abstract: A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.

Abstract: An ion implantation method is provided, which is able to improve the controllability of implanted dopant ions and the uniformity in concentration and profile of implanted dopant ions. A semiconductor substrate with a (100)-oriented crystal surface is prepared. An elongated mask with a specific pattern is formed on the surface of the substrate. A beam of dopant ions is irradiated to the surface of the substrate along a first direction, thereby selectively implanting the dopant ions into the substrate using the mask. The first direction has a first angle with a normal of the surface of the substrate in a plane perpendicular to a longitudinal axis of the mask, where the first angle is in the range from 7.degree. C. to 60.degree. C. The first direction has a second angle with a lateral axis of the mask in a plane parallel to the surface of the substrate, where the second angle is in the range from 5.degree. C. to 20.degree. C.

Abstract: A trench is formed in a substrate, the trench defining an active region surface on the substrate, the trench having a trench sidewall. A trench insulation region is then formed in the trench. The substrate underlying the trench sidewall is doped with impurities, and after the first doping, the substrate underlying the active region surface is doped with impurities to form a well having an impurity concentration which increases towards the trench sidewall in a predetermined manner. To form the trench, an insulation layer preferably is formed on the substrate, a barrier layer is formed on the insulation layer, and the barrier layer and the insulation layer are patterned to form an insulation region on the substrate and a barrier region on the insulation region. The substrate is then etched using the barrier region and the insulation region as a mask to thereby form a trench in the substrate.

Abstract: An N-Channel Metal Oxide Semiconductor Field Effect Transistor (N-MOSFET) with minimum susceptibility to the Hot Carrier Effect (HCE) and a method by which the N-MOSFET is fabricated. Formed upon a semiconductor substrate is a N-MOSFET structure including a gate oxide upon a semiconductor substrate, a gate electrode upon the gate oxide and a pair of N+ source/drain regions adjoining the gate electrode and the gate oxide. Implanted into the gate oxide regions beneath the gate electrode edges is a dose of a hardening ion. The hardening ion may be either nitrogen ion or fluorine ion. The hardening ion is implanted at an angle non-orthogonal to the plane of the semiconductor substrate through means of a large tilt angle ion implant process. Optionally, a Lightly Doped Drain (LDD) source/drain electrode structure or Double Doped Drain (DDD) source/drain electrode structure may be incorporated into the N-MOSFET structure.

Abstract: A semiconductor fabrication method is provided for forming transistors upon a semiconductor substrate wherein the semiconductor substrate has first, second and third substrate regions. A single mask layer is formed over the semiconductor substrate. The single mask layer has a first mask portion covering the first substrate region, a second mask portion exposing the second substrate region, and a third mask portion partially covering the third substrate region. A first type impurity dopant is differentially introduced into the first, second and third substrate regions according to the single mask layer. First, second and third transistors are formed in the first, second and third substrate regions, respectively. The first and second transistors have differing conductivity types and the first and third transistors have the same conductivity type. The first and third transistors also have differing threshold voltages according to the differential introducing of the dopant.

Abstract: An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpendicular to the main surface of a semiconductor substrate in the sidewall oxide film has a peak at the interface between the semiconductor substrate and the sidewall oxide film. As a result, an interface state at the interface between the sidewall oxide film and the main surface of the semiconductor substrate is suppressed, resulting in decrease of the probability at which hot carriers are trapped in the interface state. Accordingly, the hot carrier resistance is improved.

Abstract: A new method of forming an integrated circuit MNOS/MONOS device with suppressed off-cell leakage current is described. A silicon oxide layer is formed on the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon oxide layer and patterned. A first ion implantation is performed at a tilt angle to form channel stop regions in the semiconductor substrate not covered by the patterned silicon nitride layer wherein the channel stop regions partially extend underneath the patterned silicon nitride layer. The silicon substrate not covered by the patterned silicon nitride layer is oxidized to form field oxide regions within the silicon substrate wherein the channel stop regions extend under the full length of the field oxide regions. The patterned silicon nitride layer is removed. An insulating layer of silicon nitride/silicon oxide (NO) or silicon oxide/silicon nitride/silicon oxide (ONO) is deposited over the surface of the semiconductor substrate.

Abstract: The invention provides a vertical-to-surface transmission electro-photonic semiconductor device with a mesa structure of light reflective multiple layers in which the device includes a high resistive region for a carrier confinement. The high resistive region is formed by an ion-implantation of proton in a downward oblique direction during a rotation of a semiconductor substrate with use of a photo-resist mask whose horizontal width is larger than that of the mesa structure. The high resistive region defines a light emitting area of an active layer, an inverse circular truncated cone like definition of a top cladding region and a circular truncated cone like definition of a bottom cladding region. The oblique angle ion-implantation permits the top cladding region to be free from any exposure of the ion-implantation thereby an electrical resistance of the device is reduced.

Abstract: A method and system for providing a semiconductor device with device isolation and leakage current control which entails processing a semiconductor substrate to form a semiconductor circuit, and providing at least one high energy implant on the semiconductor circuit is disclosed. The high energy implant is provided at an angle to source and drain regions of the semiconductor circuit so as to allow a dosage from the at least one high energy implant below and away from the surface of the active device region. In so doing, a profile is provided in which dopant distribution is substantially uniform. Therefore, the breakdown characteristics are increased and the junction capacitance of the device is reduced. Accordingly, a device manufactured in accordance with the present invention has significant advantages over devices manufactured in accordance with conventional processes.