Providing Nondopant Ion (e.g., Proton, Etc.) Patents (Class 438/528)
  • Patent number: 10043934
    Abstract: A photovoltaic device is provided in which the tunneling barrier for hole collection at either the front contact or the back contact of a silicon heterojunction cell is reduced, without compromising the surface passivation either the front contact or at the back contact. This is achieved in the present disclosure by replacing the intrinsic and/or doped hydrogenated amorphous silicon (a-Si:H) layer(s) at the back contact or at the front contact with an intrinsic and/or doped layer(s) of a semiconductor material having a lower valence band-offset than that of a:Si—H with c-Si, and/or a higher activated doping concentration compared to that of doped hydrogenated amorphous Si. The higher level of activated doping is due to the higher doping efficiency of the back contact or front contact semiconductor material compared to that of amorphous Si, and/or modulation doping of the back or front contact semiconducting material.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9595522
    Abstract: A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having a gate stack. The method further includes performing a first pre-amorphous implantation process on the substrate and forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate and performing a second annealing process on the substrate and the second stress film.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Tsan-Chun Wang
  • Patent number: 9377682
    Abstract: According to one embodiment, a template substrate includes a substrate and a mask. The substrate includes a mesa region formed in a central portion of an upper surface of the substrate. The mesa region is configured to protrude more than a region of the substrate around the mesa region. An impurity is introduced into an upper layer portion of a partial region of a peripheral portion of the mesa region. The mask film is provided on the upper surface of the substrate.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: June 28, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shingo Kanamitsu, Masamitsu Itoh
  • Patent number: 9299281
    Abstract: A display device and manufacturing method thereof are disclosed. In one aspect, the display device includes a substrate including a display area and a peripheral area surrounding the display area, wherein the display area includes a plurality of pixels configured to display images and a plurality of inspection pads formed in the peripheral area and configured to transmit a plurality of inspection signals to the pixels. Each of the inspection pads includes a poly resistor formed over the substrate, at least one insulating layer formed over the poly resistor, first and second conductive wires formed over the insulating layer and respectively connected to opposing ends of the poly resistor, and a protective layer formed over the insulating layer and substantially overlapping the poly resistor.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: March 29, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yun-Kyeong In
  • Patent number: 9299607
    Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed on a substrate, and a contact hole is formed from the dielectric layer to the substrate. A dielectric spacer liner is formed to cover a sidewall and a bottom of the contact hole. A portion of the dielectric spacer liner is removed to expose a portion of the substrate. A metal silicide layer is formed into the substrate through the contact hole.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tain-Shang Chang, Chia-Han Lai, Ren-Hau Yu, Ching-Yao Sun, Yu-Sheng Wang
  • Patent number: 9268228
    Abstract: Various techniques for patterning a substrate are disclosed. Specifically, implantation of the first species into an anti-reflective coating layer is contemplated to reduce stress in the layer that may be generated during the exposure stage or development stage. During these steps, the resist layer or the resist structure may under mechanical changes (e.g. shrinkage) while it is in contact with the anti-reflective layer. Such changes may introduce stress in the anti-reflective layer, which may contribute to excessive line edge roughness (LER) or line width roughness (LWR). By implanting the first species before, during, or after these steps, the stress in the anti-reflective layer may be avoided or compensated, and excessive LER or LWR may be avoided or reduced.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: February 23, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Tristan Ma
  • Patent number: 9177831
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Patent number: 9029243
    Abstract: A method for producing a semiconductor device is provided. The method includes providing a wafer including a main surface and a silicon layer arranged at the main surface and having a nitrogen concentration of at least about 3*1014 cm?3, and partially out-diffusing nitrogen to reduce the nitrogen concentration at least close to the main surface. Further, a semiconductor device is provided.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Peter Irsigler
  • Patent number: 9006060
    Abstract: An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region there-between. At least one of the source/drain regions is conductively doped n-type with at least one of As and P. A conductivity-neutral dopant is in the silicon-comprising semiconductor material in at least one of the channel region and the at least one source/drain region. A gate construction is operatively proximate the channel region. Methods are disclosed.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Allen McTeer
  • Patent number: 8993425
    Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ying Zhang
  • Publication number: 20150069462
    Abstract: First and second n-type field stop layers in an n? drift region come into contact with a p+ collector layer. The first n-type field stop layer has an impurity concentration reduced toward an n+ emitter region at a steep gradient. The second n-type field stop layer has an impurity concentration distribution in which impurity concentration is reduced toward the n+ emitter region at a gentler gradient than that in the first n-type field stop layer and the impurity concentration of a peak position is less than that in the impurity concentration distribution of the first n-type field stop layer. The impurity concentration distributions of the first and second n-type field stop layers have the same peak position. The first and second n-type field stop layers are formed using annealing and first and second proton irradiation processes which have the same projected range and different acceleration energy levels.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 12, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Tomonori Mizushima
  • Publication number: 20150064890
    Abstract: A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Ingo Muri, Fritz Kroener, Werner Schustereder
  • Patent number: 8890291
    Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: November 18, 2014
    Assignee: Sumco Corporation
    Inventors: Toshiaki Ono, Wataru Ito, Jun Fujise
  • Patent number: 8889529
    Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8835282
    Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: September 16, 2014
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan Cheung
  • Patent number: 8835289
    Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
  • Patent number: 8772878
    Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: July 8, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Vassilios Papageorgiou, Belinda Hannon
  • Patent number: 8765560
    Abstract: A method of manufacturing a semiconductor device, the semiconductor device including a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: July 1, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8741720
    Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
  • Patent number: 8710378
    Abstract: A molded portable single-member housing assembly for securing and protecting elongated elements having an aesthetically pleasing design is provided. The molded portable single-member housing assembly having a lid and a depressed housing portion connected via a live hinge. The lid is engaged by a user via an aperture which permits the user to physically manipulate the lid rotatably about a hinge axis. The elongated element is store or housed within the base portion and permitted access out of the housing via at least two indentions. Further, the molded portable single-member housing assembly has at least four legs.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 29, 2014
    Assignee: Martin House Group LLC
    Inventors: Pepa A. Iliev, Vall A. Iliev
  • Patent number: 8704229
    Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: April 22, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Peter Javorka, Glyn Braithwaite
  • Patent number: 8703596
    Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8697513
    Abstract: In a second direction, in a plan view, an n-channel MOS transistor and an expanding film are adjacent. Therefore, the n-channel MOS transistor receives a positive stress in the direction in which a channel length is extended from the expanding film. As a result, a positive tensile strain in an electron moving direction is generated in a channel of the n-channel MOS transistor. On the other hand, in the second direction, in a plan view, a p-channel MOS transistor and the expanding film are shifted from each other. Therefore, the p-channel MOS transistor receives a positive stress in the direction in which a channel length is narrowed from the expanding film. As a result, a positive compressive strain in a hole moving direction is generated in a channel of the p-channel MOS transistor. Thus, both on-currents of the n-channel MOS transistor and the p-channel MOS transistor can be improved.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: April 15, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ryo Tanabe
  • Patent number: 8679961
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device which includes a MISFET, includes: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film; implanting nitrogen equal to or more than 5.0e14 atoms/cm2 and equal to or less than 1.5e15 atoms/cm2 in the semiconductor substrate by tilted ion implantation in a direction from an outside to an inside with respect to side surfaces of the gate electrode; depositing a metal film including nickel on areas in which nitrogen atoms are implanted, the areas are in a semiconductor substrate on both sides of the gate electrode; and performing first heat processing of reacting the metal film and the semiconductor substrate and forming metal semiconductor compound layers, the shapes of the layers are controlled by the nitrogen profiles of the areas.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiji Ikeda
  • Patent number: 8673754
    Abstract: A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: March 18, 2014
    Assignee: SK hynix Inc.
    Inventors: Seung-Mi Lee, Yun Hyuck Ji, Beom-Yong Kim, Bong-Seok Jeon
  • Patent number: 8664056
    Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Wirbeleit, Andy Wei
  • Patent number: 8664073
    Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
  • Patent number: 8658522
    Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya Sato, Patricia M. Liu, Fanos Christodoulou
  • Patent number: 8654537
    Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: February 18, 2014
    Assignee: Apple Inc.
    Inventors: Joseph Fisher, Jr., Sean Mayo, Dennis R. Pyper, Paul Nangeroni, Jose Mantovani
  • Patent number: 8598024
    Abstract: A method of fabricating a metal silicide layer includes forming a metal layer on a substrate, and forming a pre-metal silicide layer by reacting the substrate with the metal layer by performing a first annealing process on the substrate. The method also includes implanting silicon into the substrate using a gas cluster ion beam (GCIB) process, and changing the pre-metal silicide layer into a metal silicide layer by performing a second annealing process on the substrate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Chul-Sung Kim, Sang-Woo Lee, Yu-Gyun Shin
  • Patent number: 8551845
    Abstract: A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Abhishek Dube, Viorel C. Ontalus
  • Patent number: 8541275
    Abstract: A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sivananda Kanakasabapathy, Hemanth Jagannathan, Matthew Copel
  • Patent number: 8530343
    Abstract: A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach: (1) diffusion control for USJ formation; and (2) high dose carbon implantation for stress engineering. Diffusion control for USJ formation is demonstrated in conjunction with a boron or shallow boron cluster implant of the source/drain structures in PMOS. More particularly, first, a cluster carbon ion, such as C16Hx+, is implanted into the source/drain region at approximately the same dose as the subsequent boron implant; followed by a shallow boron, boron cluster, phosphorous or phosphorous cluster ion implant to form the source/drain extensions, preferably using a borohydride cluster, such as B18Hx+ or B10Hx+.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: September 10, 2013
    Assignee: SemEquip, Inc.
    Inventors: Wade A. Krull, Thomas N. Horsky
  • Patent number: 8501570
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ziwei Fang, Jeff J. Xu, Ming-Jie Huang, Yimin Huang, Zhiqiang Wu, Min Cao
  • Patent number: 8502284
    Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8486814
    Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
  • Patent number: 8470700
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: June 25, 2013
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Shiang Yang Ong, Elgin Quek
  • Patent number: 8471307
    Abstract: An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5×1019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Rajesh B. Khamankar, Haowen Bu, Douglas Tad Grider
  • Patent number: 8470687
    Abstract: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Joseph E. Geusic, Salman Akram
  • Patent number: 8404546
    Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yen Woon, Chun-Feng Nieh, Ching-Yi Chen, Hsun Chang, Chung-Ru Yang, Li-Te S. Lin
  • Patent number: 8389385
    Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: March 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Gurtej S. Sandhu, John Smythe
  • Patent number: 8389370
    Abstract: An enhanced shallow trench isolation method for fabricating radiation tolerant integrated circuit devices is disclosed. A layer of pad oxide is first deposited on a semiconductor substrate. A layer of pad nitride is then deposited on the pad oxide layer. A trench is defined within the semiconductor substrate by selectively etching the pad nitride layer, the pad oxide layer, and the semiconductor substrate. Boron ions are then implanted into both the bottom and along the sidewalls of the trench. Subsequently, a trench plug is formed within the trench by depositing an insulating material into the trench and by removing an excess portion of the insulating material. A p-well is implanted to a depth just below the depth of the bottom of the trench. This helps to keep the threshold voltage of the IC device below the trench at a high level, and thereby keep post-radiation leakage low. Then, an electrically neutral species is implanted into the wafer.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: March 5, 2013
    Assignee: Schilmass Co. L.L.C.
    Inventors: Nadim Haddad, Frederick Brady, Jonathon Maimon
  • Patent number: 8349732
    Abstract: A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Hung-Chih Tsai, Keh-Chiang Ku, Kong-Beng Thei, Mong Song Liang
  • Patent number: 8343862
    Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: January 1, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Frank Pfirsch, Stephan Voss, Franz-Josef Niedernostheide
  • Patent number: 8329557
    Abstract: Embodiments of the present invention relate to the use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. Then, a thin film of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. To improve uniformity of depth of implantation, channeling effects are reduced by one or more techniques. In one technique, a miscut bulk substrate is subjected to the implantation, such that the lattice of the substrate is offset at an angle relative to the impinging particle beam. According to another technique, the substrate is tilted at an angle relative to the impinging particle beam. In still another technique, the substrate is subjected to a dithering motion during the implantation. These techniques may be employed alone or in combination.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: December 11, 2012
    Assignee: Silicon Genesis Corporation
    Inventors: Adam Brailove, Zuqin Liu, Francois J. Henley, Albert J. Lamm
  • Patent number: 8293619
    Abstract: A film of material may be formed by providing a semiconductor substrate having a surface region and a cleave region located at a predetermined depth beneath the surface region. During a process of cleaving the film from the substrate, shear in the cleave region is carefully controlled to achieve controlled propagation by either KII or energy propagation control. According to certain embodiments, an in-plane shear component (KII) is maintained near zero by adiabatic heating of silicon through exposure to E-beam radiation. According to other embodiments, a surface heating source in combination with an implanted layer serves to guide fracture propagation through the cleave sequence.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: October 23, 2012
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 8288257
    Abstract: Methods for implanting material into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting material into a substrate includes providing a substrate into a processing chamber, the substrate comprising a substrate surface having a material layer formed thereon, generating a first plasma of a non-dopant processing gas, exposing the material layer to the plasma of the non-dopant processing gas, generating a second plasma of a dopant processing gas including a reacting gas adapted to produce dopant ions, and implanting dopant ions from the plasma into the material layer. The method may further include a cleaning or etch process.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: October 16, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Matthew D. Scotney-Castle, Majeed A. Foad, Peter I. Porshnev
  • Patent number: 8288250
    Abstract: A method for making a stack of at least two stages of circuits, each stage including a substrate and at least one component and metallic connections formed in or on this substrate, the assembly of a stage to be transferred onto a previous stage including: a) ionic implantation in the substrate of the stage to be transferred through at least part of the components, so as to form a weakened zone, b) formation of metallic connections of the components, c) transfer and assembly of some of this substrate onto the previous stage, and d) a step to thin the transferred part of the substrate by fracture along the weakened zone.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: October 16, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Laurent Clavelier, Chrystel Deguet, Patrick Leduc, Hubert Moriceau
  • Patent number: 8263483
    Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: September 11, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans-Joachim Schulze
  • Patent number: 8258546
    Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Hung, Yong-Tian Hou, Keh-Chiang Ku, Chien-Hao Huang