Abstract: A method for forming a MOS device with an ultra shallow lightly doped diffusion region includes providing a gate dielectric layer overlying a substrate surface region, forming a gate structure overlying the gate dielectric layer, performing a first implant process using a germanium species to form an amorphous region within an LDD region using the gate structure as a mask, and performing a second implant process in the LDD region using a P-type impurity and a carbon species. A first thermal process activates the P-type impurity in the LDD region, forming side wall spacers overlying the gate structure, and performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region adjacent to the gate structure using the gate structure and the spacers as a mask. A second thermal process then activates the first impurity in the active source/drain regions.

Abstract: A technique for conformal processing of a substrate having a non-planar surface is disclosed. The technique includes several stages. In a first stage, some surfaces of the substrate are effectively processed. During a second stage, these surfaces are treated to limit or eliminate further processing of these surfaces. During a third stage, other surfaces of the substrate are processed. In some applications, the surfaces that are perpendicular, or substantially perpendicular to the flow of particles are processed in the first and second stages, while other surfaces are processed in the third stage. In some embodiments, the second stage includes the deposition of a film on the substrate.

Abstract: A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation.

Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.

Abstract: The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.

Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.

Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.

Abstract: Methods for implanting material into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting material into a substrate includes providing a substrate into a processing chamber, the substrate comprising a substrate surface having a material layer formed thereon, generating a first plasma of a non-dopant processing gas, exposing the material layer to the plasma of the non-dopant processing gas, generating a second plasma of a dopant processing gas including a reacting gas adapted to produce dopant ions, and implanting dopant ions from the plasma into the material layer. The method may further include a cleaning or etch process.

Abstract: By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

Abstract: ZnTe is implanted with a first species selected from Group III and a second species selected from Group VII. This may be preformed using sequential implants, implants of the first species and second species that are at least partially simultaneous, or a molecular species comprising an atom selected from Group III and an atom selected from Group VII. The implants may be performed at an elevated temperature in one instance between 70° C. and 800° C.

Abstract: The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.

Abstract: A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks.

Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

Abstract: Electrostatic discharge (ESD) protection clamps (61, 95) for I/O terminals (22, 23) of integrated circuit (IC) cores (24) comprise a bipolar transistor (25) with an integrated Zener diode (30) coupled between the base (28) and collector (27) of the transistor (25). Prior art variations (311, 312, 313, 314) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants (781, 782) and forming the base (28, 68) coupled anode (301, 75) and collector (27, 70, 64) coupled cathode (302, 72) of the Zener (30) using opposed edges (713, 714) of a single relatively thin mask (71, 71?). The anode (301, 75) and cathode (302, 72) are self-aligned and the width (691) of the Zener space charge region (69) therebetween is defined by the opposed edges (713, 714) substantially independent of location and orientation of the ESD clamps (61, 95) on the die or wafer.

Abstract: One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.

Abstract: A method for fabricating a semiconductor device includes: forming an impurity junction area within an area of the semiconductor substrate; forming a contact hole which partially exposes a surface the impurity junction area; and performing an additional ion implant process to implant impurity ions into the impurity junction area exposed through the contact hole, thereby increasing an impurity concentration of a surface portion of the impurity junction area.

Abstract: A first species is directed through a first mask with a first aperture and a second mask with a second aperture. The first aperture and second aperture may be different shapes or have different spacing. The first species may be implanted in pattern defining non-implanted regions surrounded by implanted regions. These implanted regions are a sum of said first ion species implanted through said first aperture and said second aperture. Thus, the non-implanted regions are surrounded by the implanted regions formed using the first mask and second mask. The first species also may deposit on or etch the workpiece.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: A method of manufacturing a semiconductor device that includes a semiconductor substrate is provided. The method includes: exposing a photoresist coated on the semiconductor substrate using a photomask including a plurality of regions having different light transmittances; developing the photoresist to form a resist pattern including a plurality of regions having different thicknesses that depend on an exposure amount of the photoresist; and implanting impurity ions into the semiconductor substrate through the plurality of regions of the resist pattern having different thicknesses to form a plurality of impurity regions whose depths from a surface of the semiconductor substrate to peak positions are different from each other. The depths to the peak positions depend on the thickness of the resist pattern through which the implanted impurity ions pass.

Abstract: An improved method of moving a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. After the substrate is exposed to the ion beam, the mask is indexed to a new position relative to the substrate and a subsequent implant step is performed. Through the selection of the aperture size and shape, the index distance and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions. In other embodiments, the implant pattern is suitable for use with a bus-bar structure.

Abstract: In an ion implantation method, ion implantation into a substrate is performed while changing a relative positional relation between an ion beam and the substrate. A first ion implantation process in which a uniform dose amount distribution is formed within the substrate and a second ion implantation process in which a non-uniform dose amount distribution is formed within the substrate are performed in a predetermined order. Moreover, a cross-sectional size of an ion beam irradiated on the substrate during the second ion implantation process is set smaller than a cross-sectional size of an ion beam irradiated on the substrate during the first ion implantation process.

Abstract: A first species is directed through a first mask with a first aperture and a second mask with a second aperture. The first aperture and second aperture may be different shapes or have different spacing. The first species may be implanted in pattern defining non-implanted regions surrounded by implanted regions. These implanted regions are a sum of said first ion species implanted through said first aperture and said second aperture. Thus, the non-implanted regions are surrounded by the implanted regions formed using the first mask and second mask. The first species also may deposit on or etch the workpiece.

Abstract: A method for manufacturing a semiconductor device includes steps of preparing a semiconductor substrate having a first conductive type; implanting a first impurity having the first conductive type in the semiconductor substrate to form a well region having a bottom portion; and implanting a second impurity having a second conductive type in the semiconductor substrate to form an impurity region having a top portion, the top of the impurity region being in contact with the bottom portion of the well region. Implantation of the second impurity includes a first step of implanting the second impurity and a second step of implanting the second impurity, wherein a first implantation area of the first step of implanting the second impurity being broader or narrower than a second implantation area of the second step of implanting the second impurity.

Abstract: An improved, lower cost method of processing substrates, such as to create solar cells is disclosed. In addition, a modified substrate carrier is disclosed. The carriers typically used to carry the substrates are modified so as to serve as shadow masks for a patterned implant. In some embodiments, various patterns can be created using the carriers such that different process steps can be performed on the substrate by changing the carrier or the position with the carrier. In addition, since the alignment of the substrate to the carrier is critical, the carrier may contain alignment features to insure that the substrate is positioned properly on the carrier. In some embodiments, gravity is used to hold the substrate on the carrier, and therefore, the ions are directed so that the ion beam travels upward toward the bottom side of the carrier.

Abstract: A semiconductor device has at least two main carbon-rich regions and two additional carbon-rich regions. The main carbon-rich regions are separately located in a substrate so that a channel region is located between them. The additional carbon-rich regions are respectively located underneath the main carbon-rich regions. The carbon concentrations is higher in the main carbon-rich regions and lower in the additional carbon-rich regions, and optionally, the absolute value of a gradient of the carbon concentration of the bottom portion of the main carbon-rich regions is higher than the absolute value of a gradient of the carbon concentration of the additional carbon-rich regions. Therefore, the leakage current induced by a lattice mismatch effect at the carbon-rich and the carbon-free interface can be minimized.

Abstract: A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.

Abstract: A technique for conformal processing of a substrate having a non-planar surface is disclosed. The technique includes several stages. In a first stage, some surfaces of the substrate are effectively processed. During a second stage, these surfaces are treated to limit or eliminate further processing of these surfaces. During a third stage, other surfaces of the substrate are processed. In some applications, the surfaces that are perpendicular, or substantially perpendicular to the flow of particles are processed in the first and second stages, while other surfaces are processed in the third stage. In some embodiments, the second stage includes the deposition of a film on the substrate.

Abstract: Various masks for use with ion implantation equipment are disclosed. In one embodiment, the masks are formed by assembling a collection of segments and spacers to create a mask having the desired configuration. This collection of parts is held together with a carrier or frame. In another embodiment, a panel is formed by machining open-ended slots into a substrate, so as to form a comb-shaped device. Two such panels may be connected together to form a mask. In other embodiments, the panels may be used sequentially in an ion implantation process to create interdigitated back contacts. In another embodiment, multiple masks are overlaid so as to create implant patterns that cannot be created effectively using a single mask.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a first hard mask layer over the substrate; patterning the first hard mask layer to form one or more first openings having a first critical dimension; performing a first implantation process on the substrate; forming a second hard mask layer over the first hard mask layer to form one or more second openings having a second critical dimension; and performing a second implantation process.

Abstract: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making a first amorphous layer in a top layer of the semiconductor substrate by a suitable implant, the first amorphous layer having a first depth, c) implanting a first dopant into the semiconductor substrate to provide the first amorphous layer with a first doping profile, d) applying a first solid phase epitaxial regrowth action to partially regrow the first amorphous layer and form a second amorphous layer having a second depth that is less than the first depth and activate the first dopant, e) implanting a second dopant into the semiconductor substrate to provide the second amorphous layer with a second doping profile with a higher doping concentration than the first doping profile, f) applying a second solid phase epitaxial regrowth action to regrow the second amorphous layer and activate the second dopant.

Abstract: A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage.

Abstract: A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.

Abstract: According to the present invention, an ion implantation system capable of implanting ions into a large substrate and reducing a manufacturing cost, and an ion implantation method using the same may be provided. The ion implantation system includes a plurality of ion implantation assemblies arranged in a line, each ion implantation assembly to implant ions into a partial region of the substrate. This allows for a compact ion implantation system to implant ions into a very large substrate. The substrate moves through the ion implantation system in a first direction, turns around, and then moves back through the ion implantation system in a second and opposite direction, where ions are implanted into the substrate while the substrate is moving to in both directions. The path in the first direction can be spaced-apart from the path in the second direction to allow for two substrates to be processed simultaneously.

Abstract: A backside illuminated image sensor includes a photodiode, formed below the top surface of a semiconductor substrate, for receiving light illuminated from the backside of the semiconductor substrate to generate photoelectric charges, a reflecting gate, formed on the photodiode over the front upper surface of the semiconductor substrate, for reflecting light illuminated from the backside of the substrate and receiving a bias to control a depletion region of the photodiode, and a transfer gate for transferring photoelectric charges from the photodiode to a sensing node of a pixel.

Abstract: Method of preparing p-type doped ZnO or p-type doped ZnMgO, in which the following successive steps are carried out: a) implantation of O+ oxygen ions in an n-type doped ZnO or an n-type doped ZnMgO; b) first annealing at a temperature less than or equal to 1200° C. under oxygen for a time greater than or equal to 5 minutes; c) implantation of at least one ion of an element chosen among the elements of group I or the elements of group V of the periodic table; d) second annealing. The p-type doped ZnO or ZnMgO obtained by this method may be used in an optoelectronic device such as a light emitting diode.

Abstract: A method includes: forming a transfer gate on a semiconductor substrate; forming a first ion implantation region on a first side of the transfer gate; forming a second ion implantation region on the first side of the transfer gate such that the second ion implantation region encloses the first ion implantation region; forming a third ion implantation region along a surface of the semiconductor substrate; and forming a floating diffusion region at a second side of the transfer gate.

Abstract: An improved, lower cost method of processing substrates, such as to create solar cells is disclosed. In addition, a modified substrate carrier is disclosed. The carriers typically used to carry the substrates are modified so as to serve as shadow masks for a patterned implant. In some embodiments, various patterns can be created using the carriers such that different process steps can be performed on the substrate by changing the carrier or the position with the carrier. In addition, since the alignment of the substrate to the carrier is critical, the carrier may contain alignment features to insure that the substrate is positioned properly on the carrier. In some embodiments, gravity is used to hold the substrate on the carrier, and therefore, the ions are directed so that the ion beam travels upward toward the bottom side of the carrier.

Abstract: A method for manufacturing a semiconductor device includes steps of preparing a semiconductor substrate having a first conductive type; implanting a first impurity having the first conductive type in the semiconductor substrate to form a well region having a bottom portion; and implanting a second impurity having a second conductive type in the semiconductor substrate to form an impurity region having a top portion, the top of the impurity region being in contact with the bottom portion of the well region. Implantation of the second impurity includes a first step of implanting the second impurity and a second step of implanting the second impurity, wherein a first implantation area of the first step of implanting the second impurity being broader or narrower than a second implantation area of the second step of implanting the second impurity.

Abstract: According to an embodiment, a semiconductor memory device includes a plurality of multi-level memory cells provided on a major surface of a semiconductor substrate of a first conductivity type. A first semiconductor region of a second conductivity type is selectively provided in the surface of the semiconductor substrate between the multi-level memory cells. A second semiconductor region is provided deeper than the first semiconductor region and includes a first conductivity type impurity. A plurality of binary memory cells are provided on the major surface of the semiconductor substrate, and a third semiconductor region of the second conductivity type is selectively provided in the surface of the semiconductor substrate between the binary memory cells. Amount of the first conductivity type impurity compensating a second conductivity type impurity of the first semiconductor region is larger than that of the third semiconductor region.

Abstract: A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.

Abstract: A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality of ion exposure cycles are performed, wherein each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall, and providing ions at a tilt angle of about five degrees or larger upon the second sidewall. Upon the performing of the plurality of ion exposure cycles the mid frequency and low frequency linewidth roughness are reduced.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.

Abstract: A device for protecting a semiconductor device from electrostatic discharge may include a high voltage first conductivity type well formed in a semiconductor substrate. A first stack region may have a first conductivity type drift region, and a first conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A second stack region may have a second conductivity type drift region, and a second conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A device isolating film formed between the first stack region and the second stack region for isolating the first stack region from the second stack region.

Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Abstract: The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enters a snapback region and begins to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.

Abstract: An object of the present invention is to provide a MOS type semiconductor device allowing production at a low cost without lowering a breakdown voltage and avoiding increase of an ON resistance.

Abstract: A bipolar semiconductor component, in particular a diode, comprising an anode structure which controls its emitter efficiency in a manner dependent on the current density in such a way that the emitter efficiency is low at small current densities and sufficiently high at large current densities, and an optional cathode structure, which can inject additional holes during commutation, and production methods therefor.

Abstract: A method for manufacturing a semiconductor device includes implanting indium into a first region of a semiconductor substrate; forming a first gate insulation film having a first film thickness in the first region and a second region different from the first region after the implanting; removing the first gate insulation film from the first region; applying heat treatment to the semiconductor substrate after the forming; and forming a second gate insulation film having a second film thickness on the first region after the applying. In the method, a temperature falling rate of the heat treatment in the applying is 20° C. per second or higher.