Abstract: The disclosed subject matter generally relates a method of irradiating a large area thin film with a pulsed light source. In some embodiments, the disclosed subject matter particularly relates to utilizing flash lamp annealing in combination with patterning techniques for making thin film devices. The flash lamp annealing can trigger lateral growth crystallization or explosive crystallization in large area thin films. In some embodiments, capping layers or proximity masks can be used in conjunction with the flash lamp annealing.

Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.

Abstract: A method includes positioning at least one dual sided workpiece on an assembly in a process chamber to expose a first side of the at least one dual sided workpiece, treating the first side of the at least one dual sided workpiece, reorienting a portion of the assembly in the process chamber to expose a second side of the at least one dual sided workpiece, the second side opposing the first side, and treating the second side. A processing apparatus including a process chamber defining an enclosed volume and a dual sided workpiece assembly disposed in the enclosed volume is also provided.

Abstract: According to one embodiment, a producing method for a semiconductor device includes first impurities containing phosphorus or boron in the form of molecular ion and second impurities containing carbon, fluorine or nitrogen with less implantation amount than this phosphorus or boron in the form of molecular ion are implanted into a semiconductor layer to form an impurity implantation layer.

Abstract: Techniques for processing a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method for processing a substrate, the method comprising: ionizing first material and second material in an ion source chamber of an ion source, the first material being boron (B) containing material, the second material being one of phosphorous (P) containing material and arsenic (As) containing material; generating first ions containing B and second ions containing one of P and As; and extracting the first and second ions from the ion source chamber and directing the first and second ions toward the substrate.

Abstract: An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.

Abstract: When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.

Abstract: The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.

Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

Abstract: A bipolar diode is provided having a drift layer of a first conductivity type on a cathode side and an anode layer of a second conductivity type on an anode side. The anode layer includes a diffused anode contact layer and a double diffused anode buffer layer. The anode contact layer is arranged up to a depth of at most 5 ?m, and the anode buffer layer is arranged up to a depth of 18 to 25 ?m. The anode buffer layer has a doping concentration between 8.0*1015 and 2.0*1016 cm?3 in a depth of 5 ?m and between 1.0*1014 up to 5.0*1014 cm?3 in a depth of 15 ?m (Split C and D), resulting in good softness of the device and low leakage current. Split A and B show anode layer doping concentrations of known diodes, which have either over all depths lower doping concentrations resulting in high leakage current or enhanced doping concentration resulting in bad softness.

Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

Abstract: Methods of forming a passivation layer on a workpiece are disclosed. These methods utilize a SiC forming polymer to form the passivation layer. In addition, while the polymer is being heated to form SiC, a second result, such as annealing of the underlying workpiece, or firing of the metal contacts is achieved. For example, the workpiece may be implanted prior to coating it with the polymer. When the workpiece is heated, SiC is formed and the workpiece is annealed. In another embodiment, a workpiece is coating with the SiC forming polymer and metal pattern is applied to the polymer. The firing of workpiece causes the metal contacts to form and also forms SiC on the workpiece.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.

Abstract: One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities.

Abstract: A technique for conformal processing of a substrate having a non-planar surface is disclosed. The technique includes several stages. In a first stage, some surfaces of the substrate are effectively processed. During a second stage, these surfaces are treated to limit or eliminate further processing of these surfaces. During a third stage, other surfaces of the substrate are processed. In some applications, the surfaces that are perpendicular, or substantially perpendicular to the flow of particles are processed in the first and second stages, while other surfaces are processed in the third stage. In some embodiments, the second stage includes the deposition of a film on the substrate.

Abstract: A method for forming an image sensing device is disclosed. An epitaxy layer having the first conductivity type is formed on a substrate, wherein the epitaxy layer comprises a first pixel area corresponding to a first incident light, a second pixel area corresponding to a second incident light, and a third pixel area corresponding to a third incident light. A first deep well is formed in a lower portion of the epitaxy layer for reducing pixel-to-pixel talk of the image sensing device. A second deep well is formed in a lower portion of the epitaxy layer.

Abstract: On a plane of a semiconductor wafer, two types of in-plane regions comprising full-width non-ion-implantation regions and partial ion implantation regions, which are alternately arranged one or more times in a direction orthogonal to a scanning direction of an ion beam are created. During the creation of the partial ion implantation regions, reciprocating scanning using the ion beam can be repeated until the target dose can be satisfied while performing or stopping ion beam radiation onto the semiconductor wafer in a state in which the semiconductor wafer can be fixed. During the creation of the full-width non-ion-implantation regions, the semiconductor wafer can be moved without performing the ion beam radiation onto the semiconductor wafer. Then, by repeating fixing and movement of the semiconductor wafer plural times, ion implantation regions and non-ion-implantation regions are created in desired regions of the semiconductor wafer.

Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.

Abstract: A first species is implanted into an entire surface of a workpiece and helium is implanted into this entire surface with a non-uniform dose. The first species may be, for example, hydrogen, helium, or nitrogen. The helium has a higher dose at a portion of a periphery of the workpiece. When the workpiece is split, this split is initiated at the periphery with the higher dose. The non-uniform dose may be formed by altering a scan speed of the workpiece or an ion beam current of the helium. In one instance, the non-uniform dose of the helium is larger than a uniform dose of the hydrogen.

Abstract: A method of introducing dopants into a semiconductor wafer includes implanting the dopants into a region below a surface of the semiconductor wafer using an ion beam to form a first implanted layer. The dopants when activated causing a conductivity of the implanted layer to be either of N-type or P-type. The first implanted layer is characterized by a peak dopant concentration at a first depth below the surface of the semiconductor wafer. The method also includes removing a layer from the semiconductor wafer surface, wherein said layer includes a portion of said dopants.

Abstract: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.?doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.?doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.?doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.

Abstract: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.

Abstract: A method of manufacturing a super-junction semiconductor device facilitates suppressing the shape change caused in the alignment mark in the upper epitaxial layer transferred from the alignment mark in the lower epitaxial layer to be small enough to detect the transferred alignment mark with a few additional steps, even if the epitaxial layer growth rate is high. Alignment mark groups, each formed of trenches including parallel linear planar patterns and used in any of the multiple epitaxial layer growth cycles, are formed collectively on a scribe line between semiconductor chip sections; and the mesa region width between the trenches in each alignment mark group indicated by the distance between the single-headed arrows, facing opposite to each other and drawn in alignment mark groups is set to be one fourth of the designed total epitaxial layer thickness at the end of each epitaxial layer growth cycle or longer.

Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two dopants are present in a spatially varying region of the active region prior to device actuation. The at least two dopants have opposite conductivity types and different mobilities.

Abstract: This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process.

Abstract: A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask.

Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.

Abstract: An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.

Abstract: In one example, a method disclosed herein includes reducing a temperature of at least an implant surface of a semiconducting substrate to a temperature less than ?50° C. and after reducing the temperature of the implant surface, performing at least one ion implantation process to implant ions into the substrate with the implant surface at a temperature less than ?50° C.

Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

Abstract: A method of manufacturing a semiconductor device includes forming select lines extending in a second direction crossing a first direction on a semiconductor substrate, wherein the semiconductor substrate has active regions separated by an isolation layer and extending in the first direction, forming junctions by implanting first impurities into the active regions, respectively, between the select lines and forming a plurality of oxide layers filled between the select lines, forming contact holes exposing the junctions by etching at least one of the plurality of oxide layers, forming junction extensions by implanting second impurities into the active regions of the semiconductor substrate exposed due to loss of the isolation layer while the contact holes are formed, and forming contact plugs for filling the contact holes.

Abstract: Provided is a method and structure for utilizing advance channel substrate materials in semiconductor manufacturing. Advanced channel substrate materials such as germanium and Group III-V channel substrate materials, are advantageously utilized. One or more capping films including at least a nitride layer are formed over the channel substrate prior to patterning, ion implantation and the subsequent stripping and wet cleaning operations. With the capping layers intact during these operations, attack of the channel substrate material is prevented and the protective films are easily removed subsequently. The films are dimensioned in conjunction with the ion implantation operation to enable the desired dopant profile and concentration to be formed in the channel substrate material.

Abstract: To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage. The threshold voltage of a second nMIS transistor is greater than the threshold voltage of a first nMIS transistor and the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a second nMIS high-k film included in the second nMIS transistor is lower than the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a first nMIS high-k film included in the first nMIS transistor.

Abstract: A method for manufacturing a sensor having pixels on a substrate, each pixel including a photoelectric converter, a charge-voltage converter, and a gate for forming a channel for transferring charges in the photoelectric converter to the charge-voltage converter, comprises a step of implanting ions into target regions of the substrate, where the photoelectric converters are to be formed, wherein the step is performed N times, and in each of the steps, the ions are implanted along a direction with an inclined angle with respect to a normal to the substrate surface, the target regions where the ions are implanted are different in each step, and for each step, a mask is formed on the substrate, having an opening for every N pixels, a plurality of the openings periodically arranged in a direction along an intersection line between the surface and a plane determined by the normal and the direction.

Abstract: An improved method of implanting a solar cell is disclosed. A substrate is coated with a soft mask material. A shadow mask is used to perform a pattern ion implant and to set the soft mask material. After the soft mask material is set, the mask is removed and a blanket implant is performed.

Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.

Abstract: A method for manufacturing a gate-last high-K CMOS structure comprising a first transistor and a second transistor, which is formed in a Si substrate includes: implanting acceptor impurity into a gate recess of the first transistor to form a first buried-layer heavily doping region under a channel of the first transistor; and implanting donor impurity into a gate recess of the second transistor to form a second buried-layer heavily doping region under a channel of the second transistor.

Abstract: A through portion is formed on a semiconductor substrate. Into the semiconductor substrate, a first ion implantation is performed via the through portion. The through portion is at least partially removed in the thickness direction from a region of at least a portion of the through portion when viewed in a plan view. A second ion implantation is performed into the semiconductor substrate at the region of at least the portion thereof. An implantation energy for the first ion implantation is equal to an implantation energy for the second ion implantation.

Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

Abstract: An ion implantation method includes performing ion implantation a plurality of times using a plurality of ion implantation masks each including main mask portions, bridge portions connecting between the main mask portions, and openings corresponding to parts of annular regions where ions are to be implanted, whereby a plurality of annular ion-implanted regions are formed by combining the plurality of ion implantation masks.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes: forming a photoresist pattern having a first opening over a substrate; forming a first impurity region inside the substrate exposed to the first opening; partially etching the photoresist pattern by a plasma ashing process using oxygen (O2) gas to form a second opening having a width broader than that of the first opening; and forming a second impurity region inside the substrate exposed through the second opening, wherein the width of the second opening varies according to a plasma ashing time.

Abstract: A bipolar diode is provided having a drift layer of a first conductivity type on a cathode side and an anode layer of a second conductivity type on an anode side. The anode layer includes a diffused anode contact layer and a double diffused anode buffer layer. The anode contact layer is arranged up to a depth of at most 5 ?m, and the anode buffer layer is arranged up to a depth of 18 to 25 ?m. The anode buffer layer has a doping concentration between 8.0*1015 and 2.0*1016 cm?3 in a depth of 5 ?m and between 1.0*1014 up to 5.0*1014 cm?3 in a depth of 15 ?m (Split C and D), resulting in good softness of the device and low leakage current. Split A and B show anode layer doping concentrations of known diodes, which have either over all depths lower doping concentrations resulting in high leakage current or enhanced doping concentration resulting in bad softness.

Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.

Abstract: A method of forming a retrograde material profile in a substrate includes forming a surface peak profile on the substrate. Ions are then implanted into the substrate to form a retrograde profile from the surface peak profile, at least one of an ion implantation dose and an ion implantation energy of the implanted ions being chosen so that the retrograde profile has a peak concentration that is positioned at a desired distance from the surface of the substrate.