Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.

Abstract: An enhanced shallow trench isolation method for fabricating radiation tolerant integrated circuit devices is disclosed. A layer of pad oxide is first deposited on a semiconductor substrate. A layer of pad nitride is then deposited on the pad oxide layer. A trench is defined within the semiconductor substrate by selectively etching the pad nitride layer, the pad oxide layer, and the semiconductor substrate. Boron ions are then implanted into both the bottom and along the sidewalls of the trench. Subsequently, a trench plug is formed within the trench by depositing an insulating material into the trench and by removing an excess portion of the insulating material. A p-well is implanted to a depth just below the depth of the bottom of the trench. This helps to keep the threshold voltage of the IC device below the trench at a high level, and thereby keep post-radiation leakage low. Then, an electrically neutral species is implanted into the wafer.

Abstract: A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.

Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

Abstract: Embodiments of the present invention relate to the use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. Then, a thin film of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. To improve uniformity of depth of implantation, channeling effects are reduced by one or more techniques. In one technique, a miscut bulk substrate is subjected to the implantation, such that the lattice of the substrate is offset at an angle relative to the impinging particle beam. According to another technique, the substrate is tilted at an angle relative to the impinging particle beam. In still another technique, the substrate is subjected to a dithering motion during the implantation. These techniques may be employed alone or in combination.

Abstract: A film of material may be formed by providing a semiconductor substrate having a surface region and a cleave region located at a predetermined depth beneath the surface region. During a process of cleaving the film from the substrate, shear in the cleave region is carefully controlled to achieve controlled propagation by either KII or energy propagation control. According to certain embodiments, an in-plane shear component (KII) is maintained near zero by adiabatic heating of silicon through exposure to E-beam radiation. According to other embodiments, a surface heating source in combination with an implanted layer serves to guide fracture propagation through the cleave sequence.

Abstract: Methods for implanting material into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting material into a substrate includes providing a substrate into a processing chamber, the substrate comprising a substrate surface having a material layer formed thereon, generating a first plasma of a non-dopant processing gas, exposing the material layer to the plasma of the non-dopant processing gas, generating a second plasma of a dopant processing gas including a reacting gas adapted to produce dopant ions, and implanting dopant ions from the plasma into the material layer. The method may further include a cleaning or etch process.

Abstract: A method for making a stack of at least two stages of circuits, each stage including a substrate and at least one component and metallic connections formed in or on this substrate, the assembly of a stage to be transferred onto a previous stage including: a) ionic implantation in the substrate of the stage to be transferred through at least part of the components, so as to form a weakened zone, b) formation of metallic connections of the components, c) transfer and assembly of some of this substrate onto the previous stage, and d) a step to thin the transferred part of the substrate by fracture along the weakened zone.

Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.

Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.

Abstract: Provided is a method for performing etching process or film forming process to a substrate W whereupon a prescribed pattern is formed with an opening. The method is provided with a step of mixing a liquid and a gas, at least one of which contains a component that contributes to the etching process or the film forming process, and generating charged nano-bubbles 85 having a diameter smaller than that of the opening formed on the semiconductor substrate W; a step of forming an electric field to attract the nano-bubbles onto the surface of the substrate W; and a step of performing the process by supplying the substrate with the liquid containing the nano-bubbles 85 while forming the electric field.

Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device.

Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate through an ion implanting surface thereof; closely contacting the single crystal silicon substrate and a transparent insulator substrate with each other via a transparent adhesive while using the ion implanting surface as a bonding surface; curing the transparent adhesive; applying an impact to the ion implanted layer to mechanically delaminate the single crystal silicon substrate; forming a plurality of diffusion regions having a second conductivity type at the delaminated surface side of the single crystal silicon layer, such that a plurality of first conductivity-type regions and second conductivity-type regions are present at the delaminated surface of the single crystal silicon layer; forming pluralities of individual electrodes on the pluralities of first and second conductivity-type regions, respectively; and forming collector electrodes for the individual electrode

Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate; conducting a surface activating treatment for at least one of: the ion implanting surface of the single crystal silicon substrate, and a surface of the transparent insulator substrate; bonding the ion implanting surface of the single crystal silicon substrate and the transparent insulator substrate to each other, such that the surface(s) subjected to the surface activating treatment is/are used as a bonding surface(s); applying an impact to the ion implanted layer; and forming a plurality of diffusion regions having a second conductivity type at the delaminated surface side of the single crystal silicon layer, such that a plurality of first conductivity-type regions and second conductivity-type regions are present at the delaminated surface of the single crystal silicon layer.

Abstract: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous layer is a step for irradiating plasma to the surface of the semiconductor substrate, and the step for forming the shallow impurity-introducing layer is a step for introducing impurities into the surface which has been made amorphous.

Abstract: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.

Abstract: A method of fabricating a semiconductor device including forming a plurality of gate structures on a semiconductor substrate, forming a plurality of impurity regions in the semiconductor substrate at sides of the gate structures, forming a dielectric layer on the semiconductor substrate having the gate structures, forming contact holes by etching the dielectric layer to expose parts of the impurity regions at sides of the gate structures, directly implanting impurity ions into the exposed parts of the impurity regions via the contact holes by using the gate structures as ion implanting masks, wherein the impurity ions prevent impurities doped in the impurity regions from diffusing to channel regions of the gate structures, and forming conductive plugs in the contact holes.

Abstract: A method for manufacturing doped substrates using a continuous large area scanning implantation process is disclosed. In one embodiment, the method includes providing a movable track member. The movable track member is provided in a chamber. The chamber includes an inlet and an outlet. In a specific embodiment, the movable track member can include one or more rollers, air bearings, belt member, and/or movable beam member to provide one or more substrates for a scanning process. The method may also include providing a first substrate. The first substrate includes a first plurality of tiles. The method maintains the first substrate including the first plurality of tiles in a vacuum. The method includes transferring the first substrate including the first plurality of tiles from the inlet port onto the movable track member. The first plurality of tiles are subjected to a scanning implant process. The method also includes maintaining a second substrate including a second plurality of tiles in the vacuum.

Abstract: A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality of ion exposure cycles are performed, wherein each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall, and providing ions at a tilt angle of about five degrees or larger upon the second sidewall. Upon the performing of the plurality of ion exposure cycles the mid frequency and low frequency linewidth roughness are reduced.

Abstract: The porosity of a diamond film may be increased and its dielectric constant lowered by exposing a film containing sp3 hybridization to ion implantation. The implantation produces a greater concentration of sp2 hybridizations. The sp2 hybridizations may then be selectively etched, for example, using atomic hydrogen plasma to increase the porosity of the film. A series of layers may be deposited and successively treated in the same fashion to build up a composite, porous diamond film.

Abstract: One aspect provides a method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder. In one aspect, this improvement is achieved by forming gate electrodes over a semiconductor substrate, amorphizing the semiconductor substrate that creates amorphous regions adjacent the gate electrodes to a depth in the semiconductor substrate. Source/drains are formed adjacent the gate electrodes by placing conductive dopants in the semiconductor substrate, wherein displaced substrate atoms and the conductive dopants are contained within the depth of the amorphous regions. The semiconductor substrate is annealed to re-crystallize the amorphous regions subsequent to forming the source/drains.

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.

Abstract: A semiconductor structure includes a thin semiconductor layer fixed on an applicator or flexible support, the thin layer having an exposed surface characterized by fractured solid bridges spaced apart by cavities. A method of producing the thin layer of semiconductor material includes implanting ions into the semiconductor wafer to define a reference plane, where the ion dose is above a minimum dose, but below a critical dose so as to avoid degrading the wafer surface. The method further includes applying a thermal treatment to define a layer of microcavities and applying stress to free the thin layer from the wafer.

Abstract: A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach: (1) diffusion control for USJ formation; and (2) high dose carbon implantation for stress engineering. Diffusion control for USJ formation is demonstrated in conjunction with a boron or shallow boron cluster implant of the source/drain structures in PMOS. More particularly, first, a cluster carbon ion, such as C16Hx+, is implanted into the source/drain region at approximately the same dose as the subsequent boron implant; followed by a shallow boron, boron cluster, phosphorous or phosphorous cluster ion implant to form the source/drain extensions, preferably using a borohydride cluster, such as B18Hx+ or B10Hx+.

Abstract: A method of fabricating a CMOS transistor includes forming strained channels by re-crystallized amorphous polysilicon with the tensile film or the compressive film during annealing. C or Ge ions are optionally used to form solid-phase epitaxy to amplify the stress in the strained channel. Therefore, the charge carrier mobility in a CMOS transistor is improved.

Abstract: A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different than the first stress in a second region located further from the semiconductor fin. The semiconductor fin may also be aligned over a pedestal within the substrate. The semiconductor structure is annealed under desirable stress conditions to obtain an enhancement of semiconductor device performance.

Abstract: The invention is directed to a method for manufacturing a semiconductor. The method comprises steps of providing a substrate having a gate structure formed thereon and forming a source/drain extension region in the substrate adjacent to the gate structure. A spacer is formed on the sidewall of the gate structure and a source/drain region is formed in the substrate adjacent to the spacer but away from the gate structure. A bevel carbon implantation process is performed to implant a plurality carbon atoms into the substrate and a metal silicide layer is formed on the gate structure and the source/drain region.

Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate through an ion implanting surface thereof; closely contacting the single crystal silicon substrate and a transparent insulator substrate with each other via a transparent electroconductive adhesive while using the ion implanting surface as a bonding surface; curing and maturing the transparent electroconductive adhesive into a transparent electroconductive film; applying an impact to the ion implanted layer to mechanically delaminate the single crystal silicon substrate to leave a single crystal silicon layer; and forming a p-n junction in the single crystal silicon layer.

Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate through an ion implanting surface thereof to form an ion implanted layer in the single crystal silicon substrate; forming a transparent electroconductive film on a surface of a transparent insulator substrate; conducting a surface activating treatment for the ion implanting surface of the single crystal silicon substrate and/or a surface of the transparent electroconductive film on the transparent insulator substrate; bonding the ion implanting surface of the single crystal silicon substrate and the surface of the transparent electroconductive film on the transparent insulator substrate to each other; applying an impact to the ion implanted layer; and forming a p-n junction in the single crystal silicon layer.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to increased seasoning layer thickness. This is accomplished by first plasma-discharging residual electrostatic charge from the thick seasoning layer. The number of wafers which can be processed using the same seasoning layer is further increased by fractionally supplementing the seasoning layer after each wafer is processed, which may be followed by a brief plasma discharging of the supplemented seasoning before processing the next wafer.

Abstract: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

Abstract: The method of the invention consists of implanting ions into the surface of multilayer optical waveguides, in the highly doped layer, in a defined pattern so as to modify the refractive index of this layer.

Abstract: In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.

Abstract: In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.

Abstract: A fast recovery diode includes a base layer of a first conductivity type. The base layer has a cathode side and an anode side opposite the cathode side. An anode buffer layer of a second conductivity type having a first depth and a first maximum doping concentration is arranged on the anode side. An anode contact layer of the second conductivity type having a second depth, which is lower than the first depth, and a second maximum doping concentration, which is higher than the first maximum doping concentration, is also arranged on the anode side. A space charge region of the anode junction at a breakdown voltage is located in a third depth between the first and second depths. A defect layer with a defect peak is arranged between the second and third depths.

Abstract: A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.

Abstract: A method of forming dielectric films including a metal silicate on a silicon substrate comprises a first step of oxidizing a surface layer portion of the silicon substrate and forming a silicon dioxide film; a second step of irradiating ion on the surface of the silicon dioxide film and making the surface layer portion of the silicon dioxide film into a reaction-accelerating layer with Si—O cohesion cut; a third step of laminating a metal film on the reaction-accelerating layer in a non-oxidizing atmosphere; and a fourth step of oxidizing the metal film and forming a metal silicate film that diffuses a metal from the metal film to the silicon dioxide film.

Abstract: A method of semiconductor manufacturing is disclosed in which doping is accomplished by the implantation of ion beams formed from ionized molecules, and more particularly to a method in which molecular and cluster dopant ions are implanted into a substrate with and without a co-implant of non-dopant cluster ion, such as a carbon cluster ion, wherein the dopant ion is implanted into the amorphous layer created by the co-implant in order to reduce defects in the crystalline structure, thus reducing the leakage current and improving performance of the semiconductor junctions. These compounds include co-implants of carbon clusters with implants of monomer or cluster dopants or simply implanting cluster dopants. In particular, the invention described herein consists of a method of implanting semiconductor wafers implanting semiconductor wafers with carbon clusters followed by implants of boron, phosphorus, or arsenic, or followed with implants of dopant clusters of boron, phosphorus, or arsenic.

Abstract: In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical source lines.

Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.

Abstract: Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage.

Abstract: According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a first depth to the semiconductor substrate, the impurity diffusion region containing impurity, an inert substance containing region formed in the area of the semiconductor substrate to a second depth deeper than the first depth, the inert substance containing region containing an inert substance, and a diffusion suppressing region formed in the area of the semiconductor substrate to a third depth deeper than the second depth, the diffusion suppressing region containing a diffusion suppressing substance suppressing diffusion of the impurity.

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.

Abstract: A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

Abstract: A method for manufacturing SIMOX wafer, wherein roughness (Rms) of an SOI layer and roughness (Rms) of an interface between the SOI layer and a BOX layer can be reduced. The method includes forming a first ion-implanted layer containing highly concentrated oxygen within a wafer; forming a second ion-implanted amorphous layer; and a high temperature heat treatment, transforming the first and second ion-implanted layers into a BOX layer by holding the wafer at a temperature between 1300° C. or more and a temperature less than a silicon melting point in an atmosphere containing oxygen, wherein when a first dose amount in forming the first ion-implanted layer is set to 2×1017 to 3×1017 atoms/cm2, the first implantation energy set to 165 to 240 keV and a second dose amount in forming the second ion-implanted layer is set to 1x1014 to 1x1016 atoms/cm2.