Abstract: Disclosed herein are various methods of forming a replacement gate structure with a gate electrode comprised of a deposited intermetallic compound material. In one example, the method includes removing at least a sacrificial gate electrode structure to define a gate cavity, forming a gate insulation layer in the gate cavity, performing a deposition process to deposit an intermetallic compound material in the gate cavity above the gate insulation layer, and performing at least one process operation to remove portions of intermetallic compound material positioned outside of the gate cavity.

Abstract: A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.

Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.

Abstract: An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.

Abstract: Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes one or more of a substrate and insulator including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

Abstract: One embodiment of the present invention comprises a transistor having a source/drain region within a substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region. A silicide intermix layer is formed over both the source/drain region and a portion of the extension region. A silicide contact is formed through the silicide intermix layer over the source/drain region.

Abstract: An embodiment of this invention provides a method to produce a conductive thin film, which comprises: providing a substrate; forming a first metal oxide layer on the substrate; forming an indium-free metal layer on the first metal oxide layer; and forming a second metal oxide layer on the indium-free layer, wherein the first metal oxide layer, the indium-free metal layer, and the second oxide layer are all solution processed.

Abstract: A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.

Abstract: Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a feature formed in a high k dielectric layer may include depositing a first layer within the feature atop the dielectric layer; depositing a second layer comprising cobalt or nickel within the feature atop the first layer; and depositing a third layer comprising a metal within the feature atop the second layer to fill the feature, wherein at least one of the first or second layers forms a wetting layer to form a nucleation layer for a subsequently deposited layer, wherein one of the first, second, or third layers forms a work function layer, and wherein the third layer forms a gate electrode.

Abstract: An integrated circuit device includes a semiconductor substrate and a gate electrode on the semiconductor substrate. The gate electrode structure includes an insulating layer of a dielectric material on the semiconductor substrate, an oxygen barrier layer on the insulating layer, and a tungsten (W) metal layer on the oxygen barrier layer. Also disclosed are methods for fabricating the device.

Abstract: A method of actuating a semiconductor device includes providing a transistor including a substrate and a first electrically conductive material layer stack positioned on the substrate. The first electrically conductive material layer stack includes a reentrant profile. A second electrically conductive material layer includes first and second discrete portions in contact with first and second portions of a semiconductor material layer that conforms to the reentrant profile and is in contact with an electrically insulating material layer that conforms to the reentrant profile. A voltage is applied between the first discrete portion and the second discrete portion of the second electrically conductive material layer. A voltage is applied to the first electrically conductive material layer stack to modulate a resistance between the first discrete portion and the second discrete portion of the second electrically conductive material layer.

Abstract: In sophisticated semiconductor devices, the integrity of the device level may be enhanced after applying a replacement gate approach by providing an additional diffusion barrier layer, such as a silicon nitride layer, thereby obtaining a similar degree of diffusion blocking capabilities as in semiconductor devices without performing a replacement gate approach.

Abstract: A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

Abstract: A method for manufacturing a metal gate stack structure in gate-first process comprises the following steps after making conventional LOCOS and STI isolations: growing an untra-thin interface layer of oxide or oxynitride on a semiconductor substrate by rapid thermal oxidation or chemical process; depositing a high dielectric constant (K) gate dielectric on the untra-thin interface oxide layer and then performing rapid thermal annealing; depositing a TiN metal gate; depositing a barrier layer of AlN or TaN; depositing a poly-silicon film and a hard mask, and performing photo-lithography and the etching of the hard mask; after photo-resist removing, etching the poly-silicon film/metal gate/high-K gate dielectric sequentially to form the metal gate stack structure. The manufacturing method of the present invention is suitable for integration of high-K dielectric/metal gate in nano-scale CMOS devices, and removes obstacles of implementing high-K/metal gate integration.

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

Abstract: In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

Abstract: A method and device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.

Abstract: Improved formation of replacement metal gate transistors is obtained by utilizing a silicon to metal substitution reaction. After removing the dummy gate, a gate dielectric and work function metal are deposited. The work function metal is deposited to a different thickness for the P-channel transistors than for the N-channel transistors. A sacrificial polysilicon gate is then formed, which is caused to undergo substitution with a metal such as aluminum.

Abstract: A slurry composition for chemical mechanical polishing (CMP) of a phase-change memory device is provided. The slurry composition comprises deionized water and iron or an iron compound. The slurry composition can achieve high polishing rate on a phase-change memory device and improved polishing selectivity between a phase-change memory material and a polish stop layer (e.g., a silicon oxide film), can minimize the occurrence of processing imperfections (e.g., dishing and erosion), and can lower the etch rate on a phase-change memory material to provide a high-quality polished surface. Further provided is a method for polishing a phase-change memory device using the slurry composition.

Abstract: A semiconductor memory device and a method for fabricating the sane are disclosed. In the semiconductor device, an insulation film of a drain region is formed to have a thick thickness in a local region such that it improves Hot Carrier Degradation (HCD) characteristics. The semiconductor device includes a first insulation film formed over a semiconductor substrate, a gate formed over the first insulation film, and a second insulation film located at a specific region between the first insulation film and the gate.

Abstract: An integrated circuit includes a first replacement gate structure. The first replacement gate structure includes a layer of a first barrier material that is less than 20 ? in thickness and a layer of a p-type workfunction material. The replacement gate structure is less than about 50 nm in width.

Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.

Abstract: A semiconductor device with reduced defect density is fabricated by forming localized metal silicides instead of full area silicidation. Embodiments include forming a transistor having a gate electrode and source/drain regions on a substrate, forming a masking layer with openings exposing portions of both the gate electrode and source/drain regions over the substrate, depositing metal in the openings on the exposed portions, forming silicides in the openings, and removing unreacted metal and the masking layer.

Abstract: A method for fabricating a semiconductor device is disclosed. One embodiment of the method includes forming a dummy gate pattern on a substrate, forming an interlayer dielectric film that covers the dummy gate pattern, exposing a top surface of the dummy gate pattern, selectively removing the dummy gate pattern to form a first gate trench, forming a sacrificial layer pattern over a top surface of the substrate in the first gate trench, the sacrificial layer pattern leaving a top portion of the first gate trench exposed, increasing an upper width of the exposed top portion of the first gate trench to form a second gate trench, and removing the sacrificial layer pattern in the second gate trench, and forming a non-dummy gate pattern in the second gate trench.

Abstract: A method of fabricating a gate stack for a transistor includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. After depositing the metal gate electrode material, a layer of oxygen molecule catalyzing layer having a catalyzing function to the oxygen molecules is deposited, and afterwards, a low-temperature PMA annealing process is used to decompose the oxygen molecules in the annealing atmosphere into more active oxygen atoms. These oxygen atoms are diffused into the high-k gate dielectric film through the metal gate to supplement the oxygen vacancies in the high-k film, in order to alleviate oxygen vacancies in the high-k film and improve the quality of the high-k film. According to the present invention, the oxygen vacancies and defects of high-k gate dielectric film will be alleviated, and further, growth of SiOx interface layer having a low dielectric constant caused by the traditional PDA high temperature process may be prevented.

Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.

Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.

Abstract: A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.

Abstract: Generally, the present disclosure is directed to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same. One illustrative method disclosed herein includes removing at least a dummy gate electrode to define a gate cavity, forming a work-function material in said gate cavity, forming a semiconductor material above said work-function material, and performing a material substitution process on said semiconductor material to substitute a replacement material for at least a portion of said semiconductor material.

Abstract: It is an object of an embodiment of the present invention to reduce leakage current between a source and a drain in a transistor including an oxide semiconductor. As a first gate film in contact with a gate insulating film, a compound conductor which includes indium and nitrogen and whose band gap is less than 2.8 eV is used. Since this compound conductor has a work function of greater than or equal to 5 eV, preferably greater than or equal to 5.5 eV, the electron concentration in an oxide semiconductor film can be maintained extremely low. As a result, the leakage current between the source and the drain is reduced.

Abstract: A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes generating a logic zero at a source of the transistor by electrically connecting the source of the transistor to a ground line with the first conductor. Further, the method includes, programming the read only memory cell to logic zero. A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes, connecting electrically a source of the transistor to the drain with the first conductor. Further, the method includes programming the read only memory cell to logic one.

Abstract: A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.

Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.

Abstract: The present invention improves the performance of a semiconductor device wherein a metal silicide layer is formed through a salicide process. A metal silicide layer is formed over the surfaces of first and second gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions through a salicide process of a partial reaction type without the use of a salicide process of a whole reaction type. In a heat treatment for forming the metal silicide layer, by heat-treating a semiconductor wafer not with an annealing apparatus using lamps or lasers but with a thermal conductive annealing apparatus using carbon heaters, a thin metal silicide layer is formed with a small thermal budget and a high degree of accuracy and microcrystals of NiSi are formed in the metal silicide layer through a first heat treatment.

Abstract: A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.

Abstract: Generally, the present disclosure is directed to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same. One illustrative method disclosed herein includes removing at least a dummy gate electrode to define a gate cavity, forming a work-function material in said gate cavity, forming a semiconductor material above said work-function material, and performing a material substitution process on said semiconductor material to substitute a replacement material for at least a portion of said semiconductor material.

Abstract: Various methods are proposed for forming a gate insulation film, a metal gate layer, and others separately in an N-channel region and a P-channel region of an integrated circuit device having a CMIS or CMOS structure using a metal gate. One of the problems of the methods however has been that the process becomes complex. The present invention is that, in a manufacturing method of a CMOS integrated circuit device, a titanium-based nitride film for adjusting the electrical properties of a high-permittivity gate insulation film before a gate electrode film is formed includes a lower film containing a comparatively large quantity of titanium and an upper film containing a comparatively large quantity of nitrogen in an N-channel region and a P-channel region.

Abstract: A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Abstract: A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.

Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function.

Abstract: Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

Abstract: Provided are devices and methods utilizing TiN and/or TaN films doped with Si, Al, Ga, Ge, In and/or Hf. Such films may be used as a high-k dielectric cap layer, PMOS work function layer, aluminum barrier layer, and/or fluorine barrier. These TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TiInN, TaInN, TiHfN or TaHfN films can be used where TiN and/or TaN films are traditionally used, or they may be used in conjunction with TiN and/or TaN.

Abstract: A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate.

Abstract: A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate.

Abstract: A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.

Abstract: A chemical solution including an aqueous solution, an oxidizing agent, and a pH stabilizer selected from quaternary ammonium salts and quaternary ammonium alkali can be employed to remove metallic materials in cavities for forming a semiconductor device. For example, metallic materials in gate cavities for forming a replacement gate structure can be removed by the chemical solution of the present disclosure with, or without, selectivity among multiple metallic materials such as work function materials. The chemical solution of the present disclosure provides different selectivity among metallic materials than known etchants in the art.