Abstract: The present invention provides methods of forming fuse box guard rings for integrated circuits and integrated circuit devices having the same. A fuse line is formed at a fuse portion of an integrated circuit device and a first insulating layer is formed on the fuse line. A guard ring pattern that encloses the fuse line is formed on the first insulating layer. A second insulating layer is formed on the guard ring pattern and the first insulating layer. The second insulating layer is partially etched to remove a portion of the second insulting layer in the fuse portion of the integrated circuit device enclosed by the guard ring pattern exposing a portion of the first insulating layer and to form a via hole in a peripheral circuit region of the integrated circuit device.

Abstract: The present invention relates to a method of forming a metal feature on an intermediate structure of a semiconductor device that comprises a first exposed metal structure and a second exposed metal structure. The metal feature is selectively formed on the first exposed metal structure without forming on the second exposed metal structure. By adjusting a concentration of stabilizer in an electroless plating solution, the metal feature is electrolessly plated on the first exposed metal structure without plating metal on the second exposed metal structure.

Abstract: A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2exposing at least a portion of the exposed adjacent metal structures. A metal fuse portion is formed between at least two of the adjacent metal structures without additional photolithography, etch or deposition processes. The metal fuse portion including a portion having a nominal mass and a sub-portion of the portion having a mass less than the nominal mass so that the metal fuse portion is more easily disconnected at the less massive sub-portion during programming of the metal fuse portion.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising: a metallization-line; a liner separating the metallization line and a combination Cu-alloy seed layer and a pure Cu layer; a dielectric surrounding the liner; and a dielectric cap disposed over the surrounding dielectric, the liner and the combination Cu-alloy seed layer and pure Cu layer; the laser fuse being characterized after Laser energizing by passivation areas: a) on the open Cu-fuse surface; and b) in the interfaces between: (i) the Cu-alloy seed layer and the liners and dielectric; and (ii) between the pure Cu layer and the dielectric cap.

Abstract: A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

Abstract: A method for forming a fuse pattern for repairing a bad cell includes forming a metal wiring pattern on a substrate and successively forming an insulating layer on the metal wiring pattern and the substrate. The insulating layer of a region for defining the fuse pattern is etched by using an etching gas including a fluorocarbon-type compound and a fluorosilicate-type compound, which substantially suppresses a generation of by-products. A partially exposed metal layer of the metal wiring pattern is removed to form a fuse. Accordingly, a structure such as a fence is not formed on the residue of insulating layer. Therefore, the removal process for the fence is unnecessary. As a result, the process for forming the fuse is simplified.

Abstract: A semiconductor device includes a substrate, a fuse that can be blown by the radiation of light formed above the substrate, and insulating films formed on the fuse and on the substrate. One of the insulating films includes a flat portion formed on the substrate and the surface thereof is higher than the surface of the fuse, and a protruded portion formed on the fuse continuously from the flat portion, and protruded from the surface of the flat portion.

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.

Abstract: In one embodiment, a first dielectric layer (32) that overlies a fuse (16) and a bonding pad (30) is etched with a first etch process. This first etch process exposes a portion (40) of a second dielectric layer (20) that underlies the first dielectric layer (32) and overlies the fuse (16). In addition, the first etch process also forms a bond pad opening (38) that exposes a portion (42) of an anti-reflective layer (28) that forms a portion of the bonding pad (30). A second etch process is then used to etch the exposed portion (42) of the anti-reflective layer (28) and the exposed portion (40) of the second dielectric layer (20) at substantially the same rate to form a fuse window (45) overlying the fuse (16). The second etch process prevents over etching of the second dielectric layer (20), and thus exposure of the underlying fuse (16).

Abstract: A system and methodology for fabricating integrated circuits (ICs) on wafer die monitors at a subset of die one or more parameters that can affect the performance capabilities of associated ICs. One or more respective parameters for unmeasured die are derived based on one or more of the measured parameter. Fuses are selectively set for ICs at each die location based on parameters associated with each respective die location, thereby configuring the respective ICs accordingly.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: A method for forming a junction electrode of a semiconductor device where a gate is formed on a semiconductor substrate by using a predetermined device structure, a contact hole is formed by stacking an interlayer insulation film on the gate, and n-type and p-type junction electrodes are formed in the contact hole according to an epitaxial growth method, thereby preventing a defect due to the implantation and improving yields of the semiconductor devices. Moreover, a selective silicon growth method may be employed in a narrow junction portion, thereby reducing the number of processes, prime cost, and time. In addition, performance of the electrode is exemplary and homogeneous, a result which has not been achieved using conventional implantation methods.

Abstract: The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to at least two contacts in the metal layer. A conductive metal layer is deposited and patterned to form a fuse between the fuse contacts. A second dielectric layer is deposited on the conductive metal layer.

Abstract: The semiconductor device includes a blocking layer 12 formed on a substrate 10, an insulation film 14 formed on the blocking layer 12, and a fuse 22 formed on the insulation film 14. The blocking layer 12 is formed below the fuse 22, whereby the fuse is disconnected by laser ablation, and the laser ablation can be stopped by the blocking layer 12 with good controllability without damaging the substrate. The fuses to be disconnected can be arranged at a very small pitch, which can improve integration of the fuse circuit.

Abstract: A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.

Abstract: Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.

Abstract: A fabrication method for forming a semiconductor device having a fuse is provided. A substrate includes a cell array area, a peripheral circuit area and a global step difference between the cell array area and the peripheral circuit area. The substrate comprises a fuse formed in the peripheral circuit of the substrate. An interlayer insulating layer is formed on the global step difference. The global step difference is reduced by a cell open process. A multilevel metal interconnection including an intermetal insulating layer is formed on the resultant structure. During the cell open process and/or the process for forming the multilevel metal interconnection, the interlayer insulating layer and/or the intermetal insulating layer is partially removed to form a recess. A passivation layer is formed on the multilevel metal interconnection. A fuse opening is formed through the recess to expose the fuse.

Abstract: A semiconductor device comprises fuse elements formed on an insulating interlayer over a semiconductor substrate. A groove is formed in the insulating interlayer at each space between the fuse elements. A silicon nitride film of a predetermined thickness covers the side and upper surfaces of each fuse element. Since the side and upper surfaces of each fuse element are covered with the silicon nitride film of the same thickness, the film covering the fuse elements has no local weak point. Consequently, when a fuse element is blown out by applying laser beams, it is prevented that the silicon nitride film breaks before the temperature of the fuse element fully rises, and melted fuse element flows out.

Abstract: A method of forming metal fuses and bonding pads. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.

Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.

Abstract: The semiconductor device includes a semiconductor substrate, an insulating layer on the semiconductor substrate wherein a groove is patterned to a predetermined depth in an upper surface of the insulating layer, a fuse layer at sidewalls and on a bottom of the groove, and a wire connected electrically to the fuse layer.

Abstract: A cross point memory array is fabricated on a substrate with a plurality of memory cells, each memory cell including a diode and an anti-fuse in series. First and second conducting materials are disposed in separate strips on the substrate to form a plurality of first and second orthogonal electrodes with cross points. A plurality of semiconductor layers are disposed between the first and second electrodes to form a plurality of diodes between the cross points of the first and second electrodes. A passivation layer is disposed between the first electrodes and the diodes to form a plurality of anti-fuses adjacent to the diodes at the cross points of first and second electrodes. Portions of the diode layers are removed between the electrode cross points to form the plurality of memory cells with rows of trenches between adjacent memory cells to provide a barrier against crosstalk between adjacent memory cells. The trenches extend substantially to the depth of the n-doped layer in each diode.

Abstract: A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so that the fuse wires are between the integrated circuit substrate and the insulating layer. A plurality of fuse cutting holes can be formed in the insulating layer wherein each of the fuse cutting holes exposes a target spot on a respective one of the fuse wires, and a cross-sectional area of the fuse wires can be reduced at the exposed target spots. Related structures are also discussed.

Abstract: A semiconductor device having an array of dummy interconnections in a fuse window are proposed. The each dummy interconnection comprised of a fuse body scheduled to be blown away by laser beam, a fuse wiring extended up to the bottom of the fuse body from one side of the fuse window, and another fuse wiring extended up to the bottom of the fuse body form the another side of the fuse window. Contact plugs are disposed on terminal portions of the fuse wirings respectively, the terminal portions facing to each other having a predetermined gap between them. The bottom surfaces of both terminal portions of the fuse body are electrically connected with the facing terminal portions of the fuse wirings through the contact plugs, respectively. The length of the fuse body is set so as to have a length not shorter than the predetermined gap and not exceeding a diameter of laser beam to blow off the fuse body.

Abstract: A method of manufacturing a semiconductor device comprises forming a thin film over a semiconductor substrate, patterning the thin film to define a portion of a laser trimming registration position pattern while simultaneously forming a fuse element formed from the same thin film and separate from the portion of the laser trimming position registration pattern, and forming a metallic film on the portion of the laser trimming position pattern but not on the fuse element.

Abstract: A method for forming a fuse in a semiconductor device comprising: forming a second insulating layer on a first insulating layer; etching the second insulating layer to form a trench; depositing a first metal layer on the trench and the second insulating layer; performing a chemical-mechanical polishing (CMP) process on the first metal layer to form the first metal wiring; forming a third insulating layer on the first metal wiring and the second insulating layer; etching the third insulating layer to form a second trench; depositing a barrier layer and a second metal layer on the second trench and the third insulating layer, and performing a CMP process on the barrier layer and the third insulating layer to form the second metal wiring; depositing a buffer layer on the second metal wiring and the third insulating layer; forming a passivation layer on the buffer layer; and etching the passivation layer.

Abstract: A tungsten layer formation method for a semiconductor device reduces resistivity of the tungsten layer without requiring modification of the conventional manufacturing system. The method includes treating the surface of a barrier metal layer formed over a semiconductor substrate in a pressure environment of over 40 Torr using SiH4 gas; forming a tungsten seed layer on the treated barrier metal layer using WF6 and SiH4 gases, a mixing ratio {WF6}/{SiH4} of the gases being less than or equal to one; and forming a tungsten layer on the treated barrier metal layer using WF6 gas, the treated barrier metal layer having the tungsten seed layer formed thereon.

Abstract: A one-time programmable memory cell includes a fuse and an anti-fuse in series. The memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite, typically dominated by the relatively high resistance of the anti-fuse. In the written state, the resistance is infinite because the breakdown of the fuse resulting in an open circuit. The cell may be programmed by applying a critical voltage across the cell generating a critical current to cause the fuse to become open. When critical voltage is applied, this generally causes the anti-fuse to break down, which in turn causes a pulse of high current to be applied to the fuse. The states are detected by applying a read voltage across the memory cell. If the memory has not been programmed, then a measurable amount flows. Otherwise, no current flows.

Abstract: A fuse structure in a semiconductor device and a manufacturing method thereof. The fuse structure includes a insulation layer, a metal layer on a top surface of the first insulation layer, the metal layer having a middle portion narrower than a first and a second outer portions of the metal layer, a second insulation layer over the metal layer, a first top metal layer and a second top metal layer on a top surface of the second insulation layer and a plurality of vias connecting the first and second top metal layers with the metal layer respectively. The first top metal layer is connected to the first outer portion of the metal layer and the second top metal layer is connected to the second outer portion of the metal layer. The middle portion is disposed between the first and second outer portions of the metal layer.

Abstract: A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

Abstract: Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.

Abstract: A semiconductor device of the present invention is provided with a first metal wire formed above a semiconductor substrate with an interlayer insulating film intervened, a fuse formed on interlayer insulating film so as to be spaced at a distance away from first metal wire, an insulating film which covers first metal wire and which has an opening above fuse, a second metal wire formed on insulating film, a first passivation film which covers second metal wire and fuse, and a second passivation film formed on first passivation film, made of a material different from that of first passivation film and having an opening above fuse.

Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.

Abstract: A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

Abstract: A method for forming an electrical metal fuse for use with a semiconductor integrated circuit device. At least two varying trench metal depths may be formed on a substrate to configure the electrical metal fuse thereon. Additionally, at least two different widths of single metal lines, may be configured on the substrate. As a result of the two different trench depths and two different widths of metal formed thereon to create the electrical metal fuse, increases in current density gradients and thermal gradients thereof can be generated. The trench metal depths and width of metal are formed from copper. The electrical metal fuse generally comprises a current density ratio greater than 10 to 1.

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlying the first dielectric layer, a capacitor dielectric section overlying the first capacitor plate, and a fuse barrier section overlying and between the first and second fuse electrodes are formed simultaneously. In a conductive layer overlying the second dielectric layer, a second capacitor plate overlying the capacitor dielectric section, and a fuse overlying the fuse barrier section and contacting the first and second fuse electrodes are formed simultaneously. The capacitor dielectric section and the fuse barrier section may be defined simultaneously by selectively removing portions of the first dielectric layer during a single etching step.

Abstract: The present invention provides a method for reducing plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) transistor positioned on a substrate of a MOS semiconductor wafer. The method begins with the formation of a dielectric layer covering the MOS transistor on the substrate. An etching process is then performed to form a first contact hole through the dielectric layer to a gate on the surface of the MOS transistor, as well as to form a second contact hole through the dielectric layer to an n-well in the substrate. A bypass circuit, positioned on the dielectric layer and the first and second contact holes, and a fusion area are then formed. The fusion area, electrically connecting with the bypass circuit, also electrically connects with the MOS transistor and the n-well thereafter. Ions produced during the process are thus transferred to the n-well via the conductive wire so as to reduce plasma damage to the gate oxide.

Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.

Abstract: A semiconductor wiring structure positioned between plurality conductors, comprisies spacers positioned on adjacent ones of the conductors and at least one wiring element positioned between the spacers.

Abstract: The method for manufacturing a semiconductor device includes the steps of: removing an oxide film in a region including a fuse region at the formation of an opening for the formation of a vertical interconnection in an oxide film serving as an upper insulating layer; and forming the vertical interconnection for electrically connecting interconnection layers below and above the oxide film and the interconnection layer placed on an upper side of the oxide film as one upper conductive layer at the same time.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers-an overlying and underlying layer-on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: An integrated circuit including a die having a circuit area and a plurality of guard rings. The circuit area includes active devices, passive devices, and interconnects connected to form an integrated circuit. The plurality of guard rings includes a plurality of stacked guard rings having substantially equal widths and encircling the circuit area. Alternatively, the plurality of guard rings includes metallization level guard rings interleaved with one or more via level guard rings. Each of the one or more via level guard rings includes one or more guard rings encircling the circuit area. Alternatively, the plurality of guard rings includes a plurality of concentric guard rings encircling the circuit area. Each of the plurality of guard rings is fabricated from a metal, such as aluminum, copper, or silver, or an alloy of aluminum, copper, or silver.

Abstract: A fuse area structure in a semiconductor device and a method of forming the same are provided. A ring-shaped guard ring which surrounds a fuse opening, for preventing moisture from seeping into the side surface of the exposed fuse opening, is included. The guard ring is integrally formed with a passivation film. In order to form the guard ring, a guard ring opening etching stop film is formed on a fuse line. A guard ring opening is formed using the etching stop film, and a contact hole is formed in a peripheral circuit. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the guard ring opening are formed. The conductive material layer formed on the guard ring opening is removed. The exposed etching stop film is removed. Finally, a passivation film is deposited on the entire surface of the resulting structure.

Abstract: A method for forming a fuse pattern for repairing a bad cell includes forming a metal wiring pattern on a substrate and successively forming an insulating layer on the metal wiring pattern and the substrate. The insulating layer of a region for defining the fuse pattern is etched by using an etching gas including a fluorocarbon-type compound and a fluorosilicate-type compound, which substantially suppresses a generation of by-products. A partially exposed metal layer of the metal wiring pattern is removed to form a fuse. Accordingly, a structure such as a fence is not formed on the residue of insulating layer. Therefore, the removal process for the fence is unnecessary. As a result, the process for forming the fuse is simplified.

Abstract: A fusible link device and a method of making same. The fusible link device comprising a poly layer having a center undoped portion and two doped end portions. The center undoped portion having a first resistance and the two doped end portions each having a second resistance that is lower than the first resistance. A silicide layer is formed over the poly layer with the silicide layer having a third resistance lower than the second resistance. The silicide layer agglomerating to form an electrical discontinuity within a discontinuity area in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. The agglomeration of the silicide layer occurring over the center undoped portion of the poly layer. Contacts are electrically coupled to the two doped poly layer end portions for receiving the programming potential.

Abstract: A fuse area structure in a semiconductor device and a method of forming the same are provided. A ring-shaped guard ring which surrounds a fuse opening, for preventing moisture from seeping into the side surface of the exposed fuse opening, is included. The guard ring is integrally formed with a passivation film. In order to form the guard ring, a guard ring opening etching stop film is formed on a fuse line. A guard ring opening is formed using the etching stop film, and a contact hole is formed in a peripheral circuit. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the guard ring opening are formed. The conductive material layer formed on the guard ring opening is removed. The exposed etching stop film is removed. Finally, a passivation film is deposited on the entire surface of the resulting structure.