Abstract: The method is disclosed as applied to roughening the light-emitting surface of an LED wafer for reduction of the internal total reflection of the light generated. A masking film of silver is first deposited on the surface of a wafer to be diced into LED chips. Then the masking film is heated to cause its coagulation into discrete particles. Then, using the silver particles as a mask, the wafer surface is dry etched to create pits therein. The deposition of silver on the wafer surface and its thermal coagulation into particles may be either successive or concurrent.

Abstract: A method for manufacturing a semiconductor optical device includes: forming a p-type cladding layer; forming a capping layer on the p-type cladding layer, the capping layer being selectively etchable relative to the p-type cladding layer; forming a through film on the capping layer; forming a window structure by ion implantation; removing the through film after the ion implantation; and selectively removing the capping layer using a chemical solution.

Abstract: According to an exemplary embodiment, a PHEMT (pseudomorphic high electron mobility transistor) structure includes a conductive channel layer. The PHEMT structure further includes at least one doped layer situated over the conductive channel layer. The at least one doped layer can include a heavily doped layer situated over a lightly doped layer. The PHEMT structure further includes a recessed ohmic contact situated on the conductive channel layer, where the recessed ohmic contact is situated in a source/drain region of the PHEMT structure, and where the recessed ohmic contact extends below the at least one doped layer. According to this exemplary embodiment, the recessed ohmic contact is bonded to the conductive channel layer. The recessed ohmic contact is situated adjacent to the at least one doped layer. The PHEMT structure further includes a spacer layer situated between the at least one doped layer and the conductive channel layer.

Abstract: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

Abstract: A transparent conductive oxide (TCO) based film is formed on a substrate. The film may be formed by sputter-depositing, so as to include both a primary dopant (e.g., Al) and a co-dopant (e.g., Ag). The benefit of using the co-dopant in depositing the TCO inclusive film may be two-fold: (a) it may prevent or reduce self-compensation of the primary dopant by a more proper positioning of the Fermi level, and/or (b) it may promote declustering of the primary dopant, thereby freeing up space in the metal sublattice and permitting more primary dopant to create electrically active centers so as to improve conductivity of the film. Accordingly, the use of the co-dopant permits the primary dopant to be more effective in enhancing conductivity of the TCO inclusive film, without significantly sacrificing visible transmission characteristics. An example TCO in certain embodiments is ZnAlOx:Ag.

Abstract: A method of forming an electronic device can include forming a metallic layer over a side of a workpiece including a substrate, a differential etch layer, and a semiconductor layer. The differential etch layer may lie between the substrate and the semiconductor layer, and the semiconductor layer may lie along the side of the workpiece. The process can further include selectively removing at least a majority of the differential etch layer from between the substrate and the semiconductor layer, and separating the semiconductor layer and the metallic layer from the substrate. The selective removal can be performed using a wet etching, dry etching, or electrochemical technique. In a particular embodiment, the same plating bath may be used for plating the metallic layer and selectively removing the differential etch layer.

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract: A GaN-based semiconductor device includes a silicon substrate; an active layer of a GaN-based semiconductor formed on the silicon substrate; a trench formed in the active layer and extending from a top surface of the active layer to the silicon substrate; a first electrode formed on an internal wall surface of the trench so that the first electrode extends from the top surface of the active layer to the silicon substrate; a second electrode formed on the active layer so that a current flows between the first electrode and the second electrode via the active layer; and a bottom electrode formed on a bottom surface of the silicon substrate. The first electrode is formed of a metal capable of being in ohmic contact with the silicon substrate and the active layer.

Abstract: A semiconductor saturable absorber and the fabrication method thereof are provided. The semiconductor saturable absorber includes a Fe-doped InP substrate, a periodic unit comprising an AlGaInAs QW formed on the Fe-doped InP substrate and an InAlAs barrier layer formed on one side of the AlGaInAs QW, and another InAlAs barrier layer formed on the other side of the AlGaInAs QW. Each of the InAlAs barrier layers has a width being a half-wavelength of a light emitted by the AlGaInAs QW.

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

Abstract: A semiconductor component, particularly a pHEMT, having a T-shaped gate electrode deposited in a double-recess structure, is produced with a method with self-adjusting alignment of the recesses and of the T-shaped gate electrode.

Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.

Abstract: High-speed silicon CMOS circuits and high-power AlGaN/GaN amplifiers are integrated on the same wafer. A thin layer of high resistivity silicon is bonded on a substrate. Following the bonding, an AlGaN/GaN structure is grown over the bonded silicon layer. A silicon nitride or a silicon oxide layer is then deposited over the AlGaN/GaN structure. Following this, a thin layer of silicon is bonded to the silicon nitride/silicon oxide layer. An area for the fabrication of AlGaN/GaN devices is defined, and the silicon is etched away from those areas. Following this, CMOS devices are fabricated on the silicon layer and AlGaN/GaN devices fabricated on the AlGaN/GaN surface.

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: Spacer structures of field effect transistor structures are enhanced at least in sections with immobile charge carriers. The charge accumulated in the spacer structures induces an enhancement zone of mobile charge carriers in the underlying semiconductor substrate. The enhancement zone reduces the resistance of a channel coupling between the respective source/drain region and a channel region of the respective field effect transistor structure, wherein the channel region being controlled by a potential of a gate electrode. Source/drain regions drawn back from the gate electrode of the field effect transistor structure reduce an overlap capacitance between the gate electrode and the respective source/drain regions. A method for fabricating transistor arrangements having n-FETs and p-FETs with enhanced spacer structures.

Abstract: A method for fabricating an HBT is disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locations for contact metals and emitter, base and contact metals are deposited on the emitter, base and sub-collector epitaxial layers, respectively. A self-alignment material is deposited on the surface of the substrate around the epitaxial layers and a planarization material is deposited on and covers the top surface of the HBT. The planarization material is then etched so it has a planar surface about the same level as the surface of the self-alignment material and the contact metals protrude from the planar surface. The planar metals are then deposited over the protruding portions of the contact metals.

Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.

Abstract: This invention provides a process for growing Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaxial layers by using metal organic chemical vapor deposition (MOCVD). The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaxial layer, such as Si0.1Ge0.9 in a thickness of 0.8 ?m on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si01.Ge0.9 due to the large mismatch between this layer and Si substrate. Furthermore, a subsequent 0.8 ?m Si0.05Ge0.95 layer, and/or optionally a further 0.8 ?m Si0.02Ge0.98 layer, are grown.

Abstract: The present invention relates to a process for producing an epitaxial layer of gallium nitride (GaN) as well as to the epitaxial layers of gallium nitride (GaN) which can be obtained by said process. Such a process makes it possible to obtain gallium nitride layers of excellent quality by (i) forming on a surface of a substrate, a film of a silicon nitride of between 5 to 20 monolayers, functioning as a micro-mask, (ii) depositing a continuous gallium nitride layer on the silicon nitride film at a temperature ranging from 400 to 600° C., (iii) after depositing the gallium nitride layer, annealing the gallium nitride layer at a temperature ranging from 950 to 1120° C. and (iv) performing an epitaxial regrowth with gallium nitride at the end of a spontaneous in situ formation of islands of gallium nitride.

Abstract: A method for manufacturing a group III nitride compound semiconductor device includes irradiating a surface of a wafer with ultraviolet rays to thereby clean a resist residue from the surface of the wafer, the surface including a group III nitride compound semiconductor. The ultraviolet rays cause a reaction of oxygen molecules to form stimulated oxygen atoms having a strong oxidative power at the surface.

Abstract: Disclosed are methods of preparing monoalkyl Group VA metal dihalide compounds in high yield and high purity by the reaction of a Group VA metal trihalide with an organo lithium reagent or a compound of the formula RnM1X3?n, where R is an alkyl, M1 is a Group IIIA metal, X is a halogen and n is an integer fro 1 to 3. Such monoalkyl Group VA metal dihalide compounds are substantially free of oxygenated impurities, ethereal solvents and metallic impurities. Monoalkyl Group VA metal dihydride compounds can be easily produced in high yield and high purity by reducing such monoalkyl Group VA metal dihalide compounds.

Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

Abstract: A thyristor for switching microwave signals includes semiconductor layers disposed on a substrate. A first surface of the thyristor defines an anode, and a second surface of the thyristor defines a cathode. The semiconductor layers include at least one semi-insulating layer. The thyristor transmits a microwave signal between the anode and the cathode in an ON state and blocks the microwave signal between the anode and the cathode in an OFF state.

Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.

Abstract: A semiconductor laser device has on a compound semiconductor substrate at least a lower cladding layer, an active layer, an upper cladding layer and a contact layer. An upper part of the upper cladding layer and the contact layer are formed as a mesa-structured portion having a ridge stripe pattern, and the both sides of the mesa structured portion are buried with a current blocking layer. The laser device includes the current blocking layer having a pit-like recess penetrating thereof and extending towards the compound semiconductor substrate, and a portion of the recess other than that penetrating the current blocking layer being covered or buried with an insulating film or a compound semiconductor layer with a high resistivity. The compound semiconductor substrate and the electrode layer thus can be kept insulated in an area other than a current injection area, thereby non-emissive failure due to short-circuit is prevented.

Abstract: A titanium layer and a titanium nitride layer are successively laminated on a substrate and a group III nitride compound semiconductor layer is further formed thereon. When the titanium layer is removed in the condition that a sufficient film thickness is given to the titanium nitride layer, a device having the titanium nitride layer as a substrate is obtained.

Abstract: An electrode structure on a p-type III group nitride semiconductor layer includes first, second and third electrode layers successively stacked on the semiconductor layer. The first electrode layer includes at least one selected from a first metal group of Ti, Hf, Zr, V, Nb, Ta, Cr, W and Sc. The second electrode layer includes at least one selected from a second metal group of Ni, Pd and Co. The third electrode layer includes Au.

Abstract: A layer comprising silicon oxide (SiO2) is formed on (111) plane of a silicon (Si) substrate in a striped pattern which is longer in the [1-10] axis direction perpendicular to the [110] axis direction. Then a group III nitride compound semiconductor represented by a general formula AlxGayIn1?x?yN (0?x?1, 0?y?1, 0?x+y?1) is laminated thereon. The group III nitride compound semiconductor represented by a general formula AlxGayIn1?x?yN (0?x?1, 0?y?1, 0?x+y?1) grows epitaxially on the substrate-exposed regions B which are not covered by the SiO2 layer, and grows epitaxially on the SiO2 layer in lateral direction from the regions B. Consequently, a group III nitride compound semiconductor having no dislocations can be obtained.

Abstract: A separator layer of Ti is formed on an auxiliary substrate of sapphire or the like. An undercoat layer of TiN is formed on the separator layer. The undercoat layer is provided so that a Group III nitride compound semiconductor layer can be grown with good crystallinity on the undercoat layer. TiN is sprayed on the undercoat layer to form a thermal spray depositing layer. Then, the separator layer is chemically etched to reveal the undercoat layer. Then, a Group III nitride compound semiconductor layer is grown on a surface of the undercoat layer.

Abstract: A semiconductor device includes a semiconductor structure having a p-type nitride semiconductor defining a top surface (17), a buffer layer (20) composed predominantly of a p-type metal oxide semiconductor overlying the top surface (17), and an electrode (26) including one or more metals overlying the buffer layer (20).

Abstract: A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.

Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: A method of fabricating a gate structure of a field effect transistor comprising processes of forming an &agr;-carbon mask and plasma etching a gate electrode and a gate dielectric using the &agr;-carbon mask. In one embodiment, the gate dielectric comprises hafnium dioxide.

Abstract: Non-alloyed, low resistivity contacts for semiconductors using Group III-V and Group II-VI compounds and methods of making are disclosed. Co-implantation techniques are disclosed.

Abstract: An n-type buffer layer composed of n-type GaN, an n-type cladding layer composed of n-type AlGaN, an n-type optical confinement layer composed of n-type GaN, a single quantum well active layer composed of undoped GaInN, a p-type optical confinement layer composed of p-type GaN, a p-type cladding layer composed of p-type AlGaN, and a p-type contact layer composed of p-type GaN are formed on a substrate composed of sapphire. A current blocking layer formed in an upper portion of the p-type cladding layer and on both sides of the p-type contact layer to define a ridge portion is composed of a dielectric material obtained by replacing some of nitrogen atoms composing a Group III-V nitride semiconductor with oxygen atoms.

Abstract: A light emitting diode is disclosed. The diode includes a silicon carbide substrate having a first conductivity type, a first gallium nitride layer above the SiC substrate having the same conductivity type as the substrate, a superlattice on the GaN layer formed of a plurality of repeating sets of alternating layers selected from among GaN, InGaN, and AlInGaN, a second GaN layer on the superlattice having the same conductivity type as the first GaN layer, a multiple quantum well on the second GaN layer, a third GaN layer on the multiple quantum well, a contact structure on the third GaN layer having the opposite conductivity type from the substrate and the first GaN layer, an ohmic contact to the SiC substrate, and an ohmic contact to the contact structure.

Abstract: A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer.

Abstract: A method of making a transparent electrode for a light-emitting diode includes depositing metal on a top surface of a semiconductor structure, and defining a first region of the semiconductor structure for a first electrode by forming a mask over the metal, the mask having at least one opening so that the first region is covered by the mask and a second region is aligned with the at least one opening in the mask. The method also includes removing metal aligned with the at least one opening in the mask in the second region to form the first electrode overlying the first region of the semiconductor structure and so as to reveal the top surface of the semiconductor structure in the second region.

Abstract: A process for forming/configuring a device to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is implemented by incorporating a dynamic threshold voltage in such device. An onset point for the NDR characteristic is also adjustable during a manufacturing process to enhance the performance of an NDR device.

Abstract: A process for forming a dual mode FET and a logic circuit to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is selectively enabled/disabled by forming a body contact bias, thus permitting a dual behavior of the device. Larger collections of such FETs can be synthesized to form dual mode logic circuits as well, so that a single circuit can perform more than one logic operation depending on whether an NDR mode is enabled or not.

Abstract: A semiconductor manufacturing process is disclosed that is suitable for making both negative differential resistance (NDR) and non-NDR devices at the same time. An NDR process is thus integrated within a conventional CMOS process so that compatibility with existing fabrication procedures is maintained. In addition, many of the NDR process steps and non-NDR process steps are shared in common to form features of such devices at the same time.

Abstract: A contact for n-type III-V semiconductor such as GaN and related nitride-based semiconductors is formed by depositing Al,Ti,Pt and Au in that order on the n-type semiconductor and annealing the resulting stack, desirably at about 400-600° C. for about 1-10 minutes. The resulting contact provides a low-resistance, ohmic contact to the semiconductor and excellent bonding to gold leads.

Abstract: A ZnO based oxide semiconductor layer is grown on a sapphire substrate 1 by supplying, for example, raw materials made of Zn and O constituting ZnO and a p-type dopant material made of N without supplying an n-type dopant material (a-step). By stopping the supply of the material of O and further supplying an n-type dopant material made of Ga, the semiconductor layer is doped with the p-type dopant and the n-type dopant, thereby forming a p-type ZnO layer (2a) (b-step). By repeating the steps (a) and (b) plural times, a p-type ZnO based oxide semiconductor layer is grown. As a result, N to be the p-type dopant can be doped in a stable carrier concentration also during high temperature growth in which a residual carrier concentration can be reduced, and the carrier concentration of the p-type layer made of the ZnO based oxide semiconductor can be increased sufficiently.

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: A high electron mobility transitor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.

Abstract: A method of making an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. By implanting ions into a substrate that is later thermally oxidized, a number of temporary charge trapping sites can be established above a channel region of a transistor. The channel is also heavily doped, so that a strong electrical field can be generated to accelerate hot carriers into the temporary charge trapping sites. The insulating layer formed during the oxidation step is made sufficiently thick to prevent quantum tunnelingo of the hot carriers into a gate electrode. Other suitable and conventional processing steps are used to finalize completion of the fabrication of the NDR device so that the entire process is compatible and achieved with CMOS processing techniques.

Abstract: The semiconductor device according to the present invention comprises a V-groove having V-shaped cross-section formed on a semiconductor substrate or on an epitaxial growth layer grown on a semiconductor substrate, and an active layer is provided only at the bottom of said V-groove. The method for manufacturing a semiconductor device according to the present invention comprises the steps of forming a stripe-like etching protective film in <011> direction of a semiconductor substrate or an epitaxial growth layer grown on it, performing gas etching using hydrogen chloride as etching gas on a semiconductor substrate or on an epitaxial growth layer grown on a semiconductor substrate to form a V-groove, and forming an active layer at the bottom of said V-groove.

Abstract: By using electron beam lithography, chemically assisted ion beam etching, and electroplating, high aspect ratio magnetic columns, 60 nm-170 nm in diameter, which are embedded in an aluminum-gallium-oxide/gallium-arsenide (Al0.9Ga0.1)203/GaAs heterostructured substrate, are fabricated. Storage of data in electroplated Ni columns is realized in the form of tracks 0.5 &mgr;m and 0.25 &mgr;m in the down-track direction, and 1 &mgr;m in the cross-track direction, corresponding to areal densities of 1.3 and 2.6 Gbits/in2 respectively. The fabrication of patterned media samples, using dry etching and oxidation of AlGaAs, and electrodeposition of Ni into GaAs substrate is realized.

Abstract: A novel contact structure and method for a multilayer gettering contact metallization is provided utilizing a thin layer of a pure metal as the initial layer formed on a semiconductor cap layer. During formation of the contact structure, this thin metal layer reacts with the cap layer and the resulting reacted layer traps mobile impurities and self-interstitials diffusing within the cap layer and in nearby metal layers, preventing further migration into active areas of the semiconductor device. The contact metallization is formed of pure metal layers compatible with each other and with the underlying semiconductor cap layer such that depth of reaction is minimized and controllable by the thickness of the metal layers applied. Thin semiconductor cap layers, such as InGaAs cap layers less than 200 nm thick, may be used in the present invention with extremely thin pure metal layers of thickness 10 nm or less, thus enabling an increased level of integration for semiconductor optoelectronic devices.

Abstract: A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers each have a separate electrical connection and a common ground, thereby forming a three terminal device. The thermionic cooler is comprised of a superlattice barrier surrounded by cathode and anode layers grown onto an appropriate substrate, one or more metal contacts with a finite surface area deposited on top of the cathode layer, and one or more mesas of different areas formed by etching around the contacts to the anode layer. The thermoelectric cooler is defined by metal contacts deposited on the anode layer or the substrate itself. A backside metal is deposited on the substrate for connecting to the common ground.