Abstract: The invention relates to a method for producing a semiconductor component comprising performing a plasma treatment of an exposed surface of a semiconductor material with halogens, and carrying out a diffusion method with dopants on the exposed surface.

Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

Abstract: A method of forming a light emitting device includes forming a semiconductor light emitting diode, forming a metal layer stack including a first metal layer and a second metal layer on the light emitting diode, and oxidizing the metal layer stack to form transparent conductive layer including at least one conductive metal oxide.

Abstract: A light emitting diode includes a first conductivity type semiconductor material region, an active region located over the first conductivity type semiconductor material region, a second conductivity type semiconductor material layer located over the active region, a first layer containing at least one of nickel or gold located over the second conductivity type semiconductor material layer, a reflective top contact electrode located over the first layer, a dielectric material layer located over the top contact electrode and containing an opening, and a reflector located over the dielectric material layer and contacting the top contact electrode through the opening in the dielectric material layer.

Abstract: Embodiments of the invention pertain to the use of alloyed semiconductor nanocrystals for use in solar cells. The use of alloyed semiconductor nanocrystals offers materials that have a flexible stoichiometry. The alloyed semiconductor may be a ternary semiconductor alloy, such as AxB1-xC or AB1-yCy, or a quaternary semiconductor alloy, such as AxByC1-x-yD, AxB1-xCyD1-y or ABxCyD1-x-y (where A, B, C, and D are different elements). In general, alloys with more than four elements can be used as well, although it can be much harder to control the synthesis and quality of such materials. Embodiments of the invention pertain to solar cells having a layer incorporating two or more organic materials such that percolated paths for one or both molecular species are created. Specific embodiments of the invention pertain to a method for fabricating nanostructured bulk heterojunction that facilitates both efficient exciton diffusion and charge transport.

Abstract: According to one or more embodiments of the present invention, a method for fusing metal nanowire junctions in a conductive film includes applying a constant current through the conductive film including a plurality of metal nanowires and a plurality of metal nanowire junctions, or conducting an ultrasonic welding of the metal nanowire junctions.

Abstract: Structures and methods for producing active layer stacks of lattice matched, lattice mismatched and thermally mismatched semiconductor materials, with low threading dislocation densities, no layer cracking and minimized wafer bowing, by using epitaxial growth onto elevated substrate regions in a mask-less process.

Abstract: Methods for improving the performance and lifetime of irradiated photovoltaic cells are disclosed, whereby Group-V elements, and preferably nitrogen, are used to dope semiconductor GaAs-based subcell alloys.

Abstract: A method of manufacturing a photo-semiconductor device that has a photoconductive semiconductor film provided with electrodes and formed on a second substrate, the semiconductor film being formed by epitaxial growth on a first semiconductor substrate different from the second substrate, the second substrate being also provided with electrodes, and the electrodes of the second substrate and the electrodes of the photoconductive semiconductor film being held in contact with each other.

Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Abstract: The invention relates to a method for equipping a process chamber in an apparatus for depositing at least one layer on a substrate held by a susceptor in the process chamber, process gases being introduced into the process chamber through a gas inlet element, in particular by means of a carrier gas, the process gases decomposing into decomposition products in the chamber, in particular on hot surfaces, the decomposition products comprising the components that form the layer. In order to improve the apparatus so that thick multi-layer structures can be deposited reproducibly in process steps that follow one another directly, it is proposed that a material is selected for the surface facing the process chamber at least of the wall of the process chamber that is opposite the susceptor, the optical reflectivity, optical absorptivity and optical transmissivity of which respectively correspond to those of the layer to be deposited during the layer growth.

Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.

Abstract: A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are separately disposed on the epitaxial layer structure, and the epitaxial layer structure has a root-means-square (RMS) roughness less than about 3 at a surface whereon the first electrode is formed.

Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

Abstract: A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract: A method of forming electronic device precursors and devices with reduced cracking in relevant layers is disclosed along with resulting structures. The method includes the steps of growing a transition layer of undoped Group III nitride on a substrate that is other than a Group III nitride, growing an active structure of Group III nitride on the undoped layer, and removing the substrate from the undoped layer.

Abstract: A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. The nanoparticle can be formed with a barrier separating it from another nanoparticle on the substrate; for example, nanoparticle can be located in a pit etched in the substrate. The size and location of the nanoparticle can be stable at elevated temperatures.

Abstract: This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.

Abstract: Accordingly, the present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A substrate which has a conductive layer disposed thereon is provided and the conductive layer has an oxide layer with an exposed surface. The exposed surface of the oxide layer contacts a solution of an organic surface active compound in an organic solvent to form a protective layer of the organic surface active compound over the oxide layer. The protective layer has a thickness of from about 0.5 nm to about 5 nm and ranges therebetween depending on a chemical structure of the surface active compound.

Abstract: Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum.

Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Abstract: A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer.

Abstract: Methods for plating metal over features of a semiconductor wafer and devices that can be formed by these methods are disclosed. One such method includes forming a barrier layer over the substrate using electroless plating and forming a copper layer over the barrier layer. In some implementations, the semiconductor wafer is a GaAs wafer. Alternatively or additionally, the feature over which metal is plated can be a through-wafer via. In some implementations, a seed layer over the barrier layer can be formed using electroless plating.

Abstract: Etched wafers and methods of forming the same are disclosed. In one embodiment, a method of etching a wafer is provided. The method includes forming a metal hard mask on the wafer using electroless plating, patterning the metal hard mask, and etching a plurality of features on the wafer using an etcher. The plurality of featured are defined by the metal hard mask.

Abstract: A relaxed InGaN template is formed by growing a GaN or InGaN nucleation layer at low temperatures on a conventional base layer (e.g., sapphire). The nucleation layer is typically very rough and multi-crystalline. A single-crystal InGaN buffer layer is then grown at normal temperatures on the nucleation layer. Although not necessary, the buffer layer is typically undoped, and is usually grown at high pressures to encourage planarization and to improve surface smoothness. A subsequent n-doped cap layer can then be grown at low pressures to form the n-contact of a photonic or electronic device. In some cases, a wetting layer—typically low temperature AlN—is grown prior to the nucleation layer. Other templates, such as AlGaN on Si or SiC, are also produced using the method of the present invention.

Abstract: A relaxed InGaN template employs a GaN or InGaN nucleation layer grown at low temperatures on a conventional base layer (e.g., sapphire). The nucleation layer is typically very rough and multi-crystalline. A single-crystal InGaN buffer layer is then grown at normal temperatures. Although not necessary, the buffer layer is typically undoped, and is usually grown at high pressures to encourage planarization and to improve surface smoothness. A subsequent n-doped cap layer can then be grown at low pressures to form the n-contact of a photonic or electronic device. In some cases, a wetting layer—typically low temperature AlN—is grown prior to the nucleation layer. Other templates, such as AlGaN on Si or SiC, are also produced using the method of the present invention.

Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.

Abstract: A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.

Abstract: Accordingly, the present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A substrate which has a conductive layer disposed thereon is provided and the conductive layer has an oxide layer with an exposed surface. The exposed surface of the oxide layer contacts a solution of an organic surface active compound in an organic solvent to form a protective layer of the organic surface active compound over the oxide layer. The protective layer has a thickness of from about 0.5 nm to about 5 nm and ranges therebetween depending on a chemical structure of the surface active compound.

Abstract: A method of forming a buried oxide/crystalline III-V semiconductor dielectric stack is presented. The method includes providing a substrate and forming a layered structure on the substrate comprising of layers of different materials, one of the different materials is selected to be an oxidizable material to form one or more buried low index oxide layers. A first sequence of oxidizing steps are performed on the layered structure by exposing the edges of the layered structure to a succession of temperature increases in the presence of steam from an initial temperature to the desired oxidation temperature for a time interval equal to the sum of the time intervals of the succession of temperature increases. Also, the method includes performing a second sequential oxidizing step with steam on the layered structure at the specific oxidation temperature for a specific time interval.

Abstract: A method of processing copper backside metal layer for semiconductor chips is disclosed. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by either electroless plating or sputtering. Then, the copper backside metal layer is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the copper backside metal layer through backside via holes, but also prevents metal peeling from semiconductor's substrate after subsequent fabrication processes, which is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes. The use of Pd as seed layer is particularly useful for the copper backside metal layer, because the Pd layer also acts as a diffusion barrier to prevent Cu atoms entering the semiconductor wafer.

Abstract: This invention describes a method of making solar cells wherein the efficiency of the solar cell is enhanced by defining a diffraction grating either on top of the cell or at the bottom of the cell. The diffraction grating spacing is defined such that it bends one or more wavelengths of the incident radiation thereby making those wavelengths traverse in the direction of the plane of the device. The addition of a diffraction grating is done in conjunction with thinning down the cell such that the minority carriers generated (holes and electrons) have a higher probability of being collected. The combined effect of the diffraction grating and the reduced thickness in the solar cell increases the efficiency of the solar cell.

Abstract: A light emitting diode having high light extraction efficiency and a method of manufacturing the same are provided. The LED includes a semiconductor multiple layer including an active layer; a transparent electrode layer formed on the semiconductor multiple layer; and refraction field unit embedded in the transparent electrode layer and formed of a material having a different refractive index than the transparent electrode layer.

Abstract: A method for producing an optoelectronic semiconductor chip based on a nitride semiconductor system is specified. The method comprises the steps of: forming a semiconductor section with at least one p-doped region; and forming a covering layer disposed downstream of the semiconductor section in a growth direction of the semiconductor chip, said covering layer having at least one n-doped semiconductor layer. An activation step suitable for electrically activating the p-doped region is effected before or during the formation of the covering layer. An optoelectronic semiconductor chip which can be produced by the method is additionally specified.

Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.

Abstract: An integrated circuit device includes a semiconductor die, the semiconductor die including a semiconductor substrate, driving/control circuitry disposed along a peripheral region of the semiconductor die, a MEMS device disposed within a central region of the semiconductor die, and a barrier disposed between the driving/control circuitry and the MEMS device.

Abstract: A Si(1-x)MxC material for heterostructures on SiC can be grown by CVD, PVD and MOCVD. SIC doped with a metal such as Al modifies the bandgap and hence the heterostructure. Growth of SiC Si(1-x)MxC heterojunctions using SiC and metal sources permits the fabrication of improved HFMTs (high frequency mobility transistors), HBTs (heterojunction bipolar transistors), and HEMTs (high electron mobility transistors).

Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.

Abstract: A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.

Abstract: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.

Abstract: The invention provides a semiconductor device and a method for fabricating the same capable of preventing a field plate portion from being delaminated from an insulating film by stress inherent in a semiconductor layer even if the stress is released in forming a trench in part of the semiconductor layer where the semiconductor device is to be separated and capable of having a higher breakdown property of the semiconductor device. The semiconductor device has source, drain and gate electrodes, insulating films that insulate the electrodes on an electron supplying layer and a mesa-structure formed at part where the semiconductor device is to be separated. The gate electrode has a first electrode layer having a function of the electrode and a second electrode layer having a field plate portion whose part that contacts with the insulating film is made of a metallic material that adheres well to the insulating film.

Abstract: Provided is a method for preparing a substrate for growing gallium nitride and a gallium nitride substrate. The method includes performing thermal cleaning on a surface of a silicon substrate, forming a silicon nitride (Si3N4) micro-mask on the surface of the silicon substrate in an in situ manner, and growing a gallium nitride layer through epitaxial lateral overgrowth (ELO) using an opening in the micro-mask. According to the method, by improving the typical ELO, it is possible to simplify the method for preparing the substrate for growing gallium nitride and the gallium nitride substrate and reduce process cost.

Abstract: Fabrication method of GaN power LED with electrodes formed by composite optical coatings, comprising epitaxially growing N—GaN, active, and P—GaN layers successively on a substrate; depositing a mask layer thereon; coating the mask layer with photoresist; etching the mask layer into an N—GaN electrode pattern; etching through that electrode pattern to form an N—GaN electrode region; removing the mask layer and cleaning; forming a transparent, electrically conductive film simultaneously on the P—GaN and N—GaN layers; forming P—GaN and N—GaN transparent, electrically conductive electrodes by lift-off; forming bonding pad pattern for the P—GaN and N—GaN electrodes by photolithography process; simultaneously forming thereon bonding pad regions for the P—GaN and N—GaN electrodes by stepped electron beam evaporation; forming an antireflection film pattern by photolithography process; forming an antireflection film; thinning and polishing the backside of the substrate, then forming a reflector thereon; and completin

Abstract: The method is disclosed as applied to roughening the light-emitting surface of an LED wafer for reduction of the internal total reflection of the light generated. A masking film of silver is first deposited on the surface of a wafer to be diced into LED chips. Then the masking film is heated to cause its coagulation into discrete particles. Then, using the silver particles as a mask, the wafer surface is dry etched to create pits therein. The deposition of silver on the wafer surface and its thermal coagulation into particles may be either successive or concurrent.

Abstract: A light emitting diode is disclosed. The diode includes a silicon carbide substrate having a first conductivity type, a first gallium nitride layer above the SiC substrate having the same conductivity type as the substrate, a superlattice on the GaN layer formed of a plurality of repeating sets of alternating layers selected from among GaN, InGaN, and AlInGaN, a second GaN layer on the superlattice having the same conductivity type as the first GaN layer, a multiple quantum well on the second GaN layer, a third GaN layer on the multiple quantum well, a contact structure on the third GaN layer having the opposite conductivity type from the substrate and the first GaN layer, an ohmic contact to the SiC substrate, and an ohmic contact to the contact structure.