Abstract: The present invention provides an optoelectronic device and a method of manufacture therefor, that prevents dopant diffusion and controls the dopant concentration therein. The optoelectronic device includes an active region formed over a substrate, and an interface barrier layer and barrier layer located over the active region. The optoelectronic device further includes an upper cladding layer located over the interface barrier layer and the barrier layer. In an exemplary embodiment of the invention, the interface barrier layer is an indium phosphide interface barrier layer and the barrier layer is an indium gallium arsenide phosphide barrier layer.

Abstract: On an insulating substrate, there are formed a first gate electrode, a gate insulating film, a semiconductor film, and an interlayer insulating film. Above the interlayer insulating film, a TFT is formed having a second gate electrode connected to the first gate electrode. Then, a photosensitive resin is formed over the entire surface of the extant layers. Subsequently, first exposure is applied using a first mask, and second exposure is then applied using a second mask with a larger amount of light than used for the first exposure. The second mask has an opening at a position corresponding to a source. Thereafter, the photosensitive resin film is developed thereby forming a contact hole and a concave.

Abstract: A method for manufacturing III-nitride semiconductor devices is disclosed. The method employs oxidation and sulfurated treatment to reduce the specific contact resistance between metal and p-type III-nitride semiconductors. The method includes surface treatment of p-type III-nitride semiconductors using (NH4)2Sx solution to remove the native oxide from their surface; evaporating metal layer onto the surface-treated p-type III-nitride semiconductors; and then alloy processing the metals and the p-type III-nitride semiconductor with thermal alloy treatment. The method may further include a pre-oxidation step prior to the sulfurated treatment. In this way, ohmic contact can be formed between the metal layer and the p-type III-nitride semiconductors.

Abstract: A system for coating the surface of compound semiconductor wafers includes providing a single-wafer epitaxial production system in a cluster-tool architecture with a loading, storage, and transfer modules, a III-V deposition chamber, and an insulator deposition chamber. The compound semiconductor wafer is placed in the loading and transfer module and the pressure is reduced to less than 5×10−10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The single wafer is then moved through the transfer module to the insulator chamber and an insulating cap layer is formed by thermally evaporating molecules, consisting essentially of gallium and oxygen, from an effusion cell using a thermal evaporation source that utilizes a metallic iridium crucible that is manufactured using the electroforming process.

Abstract: The electrode structure of the invention includes a p-type AlxGayIn1−x−yN (0≦x≦1, 0≦y≦1, x+y≦1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.

Abstract: Methods are provided for producing a compound semiconductor substrate including: a mica substrate; and a III-V group compound semiconductor layer containing nitrogen as its main component grown on the mica substrate.

Abstract: A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

Abstract: A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer.

Abstract: A method of fabricating on ohmic metal electrode. The p-type ohmic metal electrode according to the present invention employs Ru and RuOx as the cover layer in lieu of conventional Au, in order to effectively prevent penetration by contaminants in the air, such as oxygen, carbon, and H2O, and to form a stable metal-Ga intermetallic phase at the junction between the contact layer and the nitride compound semiconductor. The n-type ohmic metal electrode according to the present invention employs Ru as the diffusion barrier in lieu of conventional Ni or Pt, in order to effectively form a metal-nitride phase such as titanium nitride that contributes to superior ohmic characteristics during the heating process, without destruction of the junction. According to the present invention, it is possible to fabricate devices having superior electrical, optical, and thermal characteristics compared with conventional devices.

Abstract: Disclosed is a method for manufacturing a metal oxide semiconductor FET (MOSFET), which utilizes a low-temperature liquid phase oxidation for III-V group. The method includes the steps of (a) providing a substrate, (b) forming an epitaxial layer on the substrate, (c) defining and forming a drain and a source on a portion of the epitaxial layer, (d) forming a recess in an another portion of the epitaxial layer, (e) forming an oxide layer on a surface of the recess by relatively low-temperature oxidation, and (f) forming a gate on a portion of the oxide layer between the drain and source. In addition, the method further includes two selective procedures, that is, a synchronic sulfurated passivation process which can be performed with the growth of the oxide film simultaneously, and a rapid thermal annealing (RTA) process.

Abstract: An ohmic contact of semiconductor and its manufacturing method are disclosed. The present invention provides a low resistivity ohmic contact so as to improve the performance and reliability of the semiconductor device. This ohmic contact is formed by first coating a transition metal and a noble metal on a semiconductor material; then heat-treating the transition metal and the noble metal in an oxidizing environment to oxidize the transition metal. In other words, this ohmic contact primarily includes a transition metal oxide and a noble metal. The oxide in the film can be a single oxide, or a mixture of various oxides, or a solid solution of various oxides. The metal of the film can be a single metal, or various metals or an alloy thereof. The structure of the film can be a mixture or a laminate or multilayered including oxide and metal. The layer structure includes at least one oxide layer and one metal layer, in which at least one oxide layer is contacting to semiconductor.

Abstract: A process for producing a semiconductor device includes the following sequential steps: producing a semiconductor body having an AlxGa1−xAs layer with an upper surface, where x≦0.40; applying a contact metallization made of a non-noble metallic material to the AlxGa1−xAs layer; precleaning a semiconductor surface to produce a hydrophilic semiconductor surface; roughening the upper surface of the AlxGa1−xAs layer by etching with an etching mixture of hydrogen peroxide ≧30% and hydrofluoric acid ≧40% (1000:6) for a period of from 1 to 2.5 minutes; and re-etching with a dilute mineral acid. According to another embodiment, 0≦x≦1 and the upper surface of the AlxGa1−xAs layer is roughened by etching with nitric acid 65% at temperatures of between 0° C. and 30° C.

Abstract: A semiconductor device for generating spin-polarized conduction electrons including a ferromagnetic semiconductor layer and a non-magnetic semiconductor layer having a band alignment of Type II with respect to the ferromagnetic semiconductor, said ferromagnetic semiconductor layer and non-magnetic semiconductor layer being connected together directly or with interposing therebetween another non-magnetic semiconductor layer or energy barrier layer such that a spin splitting of a conduction band of the non-magnetic semiconductor layer is induced by a spontaneous spin splitting of a valence band of the ferromagnetic semiconductor layer, and spin-polarized conduction electrons are generated in the non-magnetic semiconductor layer by the spin splitting of the conduction band of the non-magnetic semiconductor layer.

Abstract: A high electron mobility transistor comprises a GaN-based electron accumulation layer formed on a substrate, an electron supply layer formed on the electron accumulation layer, a source electrode and a drain electrode formed on the electron supply layer and spaced from each other, a gate electrode formed on the electron supply layer between the source and drain electrodes, and a hole absorption electrode formed on the electron accumulation layer so as to be substantially spaced from the electron supply layer. Since the hole absorption electrode is formed on the electron absorption layer in order to prevent holes generated by impact ionization from being accumulated on the electron accumulation layer, a kink phenomenon is prevented. Good drain-current/voltage characteristics are therefore obtained. A high power/high electron mobility transistor is provided with a high power-added efficiency and good linearity.

Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.

Abstract: A high electron mobility transistor includes a channel layer for developing therein an electron gas layer having a substantially uniform electron gas density, and upper and lower high-resistance wide-band gap layers disposed respective over and beneath the channel layer, each of the upper and lower high-resistance wide-band gap layers having a silicon-doped planar layer disposed therein. A contact layer is disposed on the upper wide-band gap layer for contact with source and drain electrodes, the contact layer having a recess defined therein which divides the contact tact layer. A gate electrode of substantially T-shaped cross section is disposed in the recess, and a passivation film is disposed on an inner wall surface of the recess and a lower leg portion of the gate electrode, exposing an upper head portion of the gate electrode.

Abstract: A semiconductor device has a first region, a second region and a border region between the first region and the second region. The semiconductor device has an interlayer dielectric layer, covering at least the first region and the second region. A first wiring layer is located in the first region and defines a relatively small pattern. A second wiring layer is located in the second region and defines a relatively large pattern that is wider than the small pattern. A first dummy pattern is formed in the first region and a second dummy pattern is formed in the border region. The interlayer dielectric layer includes a planarization silicon oxide film. The planarization silicon oxide film is one of a silicon oxide film formed by a polycondensation reaction between a silicon compound and hydrogen peroxide, an organic SOG (Spin On Glass) film an inorganic SOG film and a silicon oxide film formed by reacting an organic silane with ozone or water.

Abstract: A method of forming a light-transmissive contact on a p-type Gallium nitride (GaN) layer of an optoelectronic device includes in one embodiment, introducing a selected metal in an oxidized condition, rather than oxidizing the metal only after it has been deposited on the surface of the p-type GaN layer. In some applications, the oxidized metal provides sufficient lateral conductivity to eliminate the conventional requirement of a second highly conductive contact metal, such as gold. If the second contact metal is desired, an anneal in an oxygen-free environment is performed after deposition of the second layer. The anneal causes the second metal to penetrate the oxidized metal and to fuse to the surface of the p-type GaN layer. In a second embodiment, the oxidation occurs only after at least one of the two metals is deposited on the surface of the p-type GaN layer.

Abstract: A p-contact that comprises a contact layer of a p-type Group III-nitride semiconductor having an exposed surface and an electrode layer of palladium (Pd) located on the exposed surface of the contact layer. The p-contact is made by providing a p-type Group III-nitride semiconductor contact layer having an exposed surface, and depositing an electrode layer of palladium on the exposed surface of the contact layer. Preferably, the p-contact is annealed for a prolonged annealing time after the electrode layer is deposited, and the exposed surface of the contact layer is etched using hydrofluoric acid (HF) before depositing the electrode layer.

Abstract: A first surface layer made of compound semiconductor material is defined in a surface area of a substrate. A first intermediate layer is formed on the surface layer, the first intermediate layer being made of compound material having Ga as a III group element and S as a VI element and having a thickness of at least two monolayers or thicker. A first electrode is formed on the first intermediate layer, being electrically connected to the first surface layer with an ohmic contact.

Abstract: The present invention provides a structure of a metal-insulator-semiconductor (MIS)-like multiple-negative-differential-resistance (MNDR) device and the fabrication method thereof. The device of the present invention has the characteristics of dual-route and MNDR at low temperatures. These characteristics result from the successive barrier-lowering and potential-redistribution effect when conducting carriers fall into a quantum well. MNDR devices have excellent potential in multiple-value logic circuitry applications and are capable of reducing circuitry complexity.

Abstract: A memory device consists of an array of resonant tunnel diodes in the form of pillars which are formed by selective etching. Each pillar includes first and second barriers (B1, B2) disposed between terminal regions (T1, T2) and a conductive region (CR1) between the barriers. The diameter of the pillars is typically of the order of 20-50 nm and is sufficiently small that the device exhibits first and second relatively high and low stable resistive states in the absence of an applied voltage between the terminal regions. The device can be used as a non-volatile memory at room temperature.

Abstract: Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.

Abstract: A process for producing a semiconductor device includes the following sequential steps: producing a semiconductor body having an Al.sub.x Ga.sub.1-x As layer with an upper surface, where x.ltoreq.0.40; applying a contact metallization made of a non-noble metallic material to the Al.sub.x Ga.sub.1-x As layer; precleaning a semiconductor surface to produce a hydrophilic semiconductor surface; roughening the upper surface of the Al.sub.x Ga.sub.1-x As layer by etching with an etching mixture of hydrogen peroxide.gtoreq.30% and hydrofluoric acid.gtoreq.40% (1000:6) for a period of from 1 to 2.5 minutes; and re-etching with a dilute mineral acid. According to another embodiment, 0.ltoreq.x.ltoreq.1 and the upper surface of the Al.sub.x Ga.sub.1-x As layer is roughened by etching with nitric acid 65% at temperatures of between 0.degree. C. and 30.degree. C.

Abstract: Methods are disclosed for forming Group III--arsenide-nitride semiconductor materials. Group III elements are combined with group V elements, including at least nitrogen and arsenic, in concentrations chosen to lattice match commercially available crystalline substrates. Epitaxial growth of these III-V crystals results in direct bandgap materials, which can be used in applications such as light emitting diodes and lasers. Varying the concentrations of the elements in the III-V crystals varies the bandgaps, such that materials emitting light spanning the visible spectra, as well as mid-IR and near-UV emitters, can be created. Conversely, such material can be used to create devices that acquire light and convert the light to electricity, for applications such as full color photodetectors and solar energy collectors. The growth of the III-V crystals can be accomplished by growing thin layers of elements or compounds in sequences that result in the overall lattice match and bandgap desired.

Abstract: The invention uses hydrogen ambient atmosphere to directly form PdGe contacts on Group III-V materials. Specific GaAs HBT's have been formed in a 100% H.sub.2 ambient, and demonstrate low etch reactivity attributable to the significant incorporation of hydrogen. The LP-MOCVD method used to demonstrate the invention produced a specific contact resistivity of less than 1.times.10.sup.-7 .OMEGA.-cm-.sup.-2, at preferred conditions of a 100% hydrogen ambient, 300.degree. C., and 15 minute reaction time. This is believed to be the lowest known resistance of any alloy method employed for PdGe on GaAs. Equally significant, the contacts demonstrate increased durability during etching.

Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated by dry etching a silicon nitride layer overlying the III-V semiconductor material with a chemical comprised of a group VI element. An ohmic metal layer is formed on the III-V semiconductor material after the silicon nitride layer is etched and before any exposure of the III-V semiconductor material to a chemical which etches the III-V semiconductor material or removes the group VI element.

Abstract: A method of improving contact resistance in a multi-layer heterostructure comprising the steps of providing a substrate, growing a crystalline material on the substrate, and doping close to an interface of the substrate and the crystalline material with n-silicon to provide continuity at the interface.

Abstract: It is intended to realize an ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics. Provided on an n.sup.+ -type GaAs substrate is an ohmic electrode in which an n.sup.++ -type regrown GaAs layer regrown from the n.sup.+ -type GaAs substrate and a NiGe film containing precipitates composed of .alpha.'-AuGa are sequentially stacked. The ohmic electrode may be fabricated by sequentially stacking a Ni film, Au film and Ge film on the n.sup.+ -type GaAs substrate, then patterning these films by, for example, lift-off, and thereafter annealing the structure at a temperature of 400.about.750.degree. C. for several seconds to several minutes.

Abstract: A method of selective metallization/deposition including patterning a mask on the surface of a substrate structure to define contact areas, and utilizing a compound, including a metal, which dissociates under predetermined conditions. The dissociation and application of the predetermined conditions occurring either during deposition or after deposition to selectively form a layer of the metal on the contact areas.

Abstract: A liquid phase deposition method involves the use of a supersaturated hydrofluosilicic acid aqueous solution for growing a silicon dioxide film at low temperature (30.degree. C.-50.degree. C.) on a III-V semiconductor, such as a gallium arsenide substrate. The silicon dioxide film may be used in a bipolar transistor or as a field oxide of MOS (metal oxide semiconductor). The III-V semiconductor substrate is chemically treated with an alkaline aqueous solution such as ammonium hydroxide so that the surface of the III-V semiconductor substrate is modified to facilitate the growth of the silicon dioxide film by liquid phase deposition. The growth rate of the silicon dioxide film is as fast as 1265 .ANG./hr. The silicon dioxide film has a refractive index ranging between 1.372 and 1.41.

Abstract: The electrode structure of the invention includes a p-type Al.sub.x Ga.sub.y In.sub.1-x-y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.

Abstract: A partially ionized beam (PIB) deposition technique is used to heteroepitally deposit a thin film of CoGe.sub.2 (001) on GaAs (100) substrates 14. The resulting epitaxial arrangement is CoGe.sub.2 (001) GaAs (100). The best epitaxial layer is obtained with an ion energy 1100 eV to 1200 eV and with a substrate temperature of approximately 280.degree. Centigrade. The substrate wafers are treated only by immersion in HF:H.sub.2 O 1:10 immediately prior to deposition of the epitaxial layer. Contacts grown at these optimal conditions display ohmic behavior, while contacts grown at higher or lower substrate temperatures exhibit rectifying behavior. Epitaxial formation of a high melting point, low resistivity cobalt germanide phase results in the formation of a stable contact to n-GaAs.

Abstract: A complementary heterojunction field effect transistor (CHFET) in which the channels for the p-FET device and the n-FET device forming the complementary FET are formed from gallium antimonide (GaSb) or indium antimonide (InSb). An n-type HFET structure is grown, for example, by molecular beam epitaxy (MBE) in order to obtain the highest electron or hole mobility. The complementary p-type HFET is formed by p-type doping of a cap layer thereby eliminating the need for two implants for channel doping. In order to reduce the complexity of the process for making the CHFET, a common gold germanium alloy contact is used for both the p and n-type channel devices, thereby eliminating the need for separate ohmic contacts, resulting in a substantial reduction in the number of mask levels and, thus, complexity in fabricating the device.

Abstract: An ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics is disclosed. A non-single crystal InAs layer, Ni film, WSi film and W film are sequentially deposited on an n.sup.+ -type GaAs substrate by sputtering, etc. and subsequently patterned by lift-off, etc. to make a multi-layered structure for fabricating ohmic electrodes. The structure is then annealed first at, e.g. 300.degree. C. for 30 minutes and next at, e.g. 650.degree. C. for one second to fabricate an ohmic electrode.

Abstract: It has been found that a Ga-oxide-containing layer is substantially not etched in HF solution if the layer is a Ga-Gd-oxide with Gd:Ga atomic ratio of more than about 1:7.5, preferably more than 1:4 or even 1:2. This facilitates removal of a protective dielectric (typically SiO.sub.2) layer after an ohmic contact anneal, with the Ga-Gd-oxide gate oxide layer serving as etch stop and not being adversely affected by contact with the HF etchant. Gd-Ge-oxide also exhibits a composition-dependent etch rate in HCl:H.sub.2 O.

Abstract: A method of resistless gate metal etch in the formation of a field effect transistor is disclosed, which includes providing a first layer of a first semiconductor material having a surface. A second layer of a second semiconductor material is formed on the surface and resistlessly patterned to define a masked and an unmasked portions. The unmasked portion of the second layer is etched away to the first layer to enable gate formation.

Abstract: A method of fabricating an FET includes forming an active layer including a low dopant concentration layer, forming a recess in the active layer so that the bottom of the recess is present within the low dopant concentration semiconductor layer, forming side walls in the recess, and forming a gate electrode in the-recess using the side walls as masks. The gate length can be precisely reduced by the side walls. Further, even when the active layer is anisotropically etched to form the side walls, the low dopant concentration semiconductor layer is subjected to the etching. Therefore, a part of the active layer where a greater part of channel current flows is not adversely affected by the etching. Therefore, any variation in the thickness of the active layer does not vary the channel current of the transistor.

Abstract: A missile has a body with a substantially circular nose opening therein, and a ceramic radome sized to cover the nose opening. A compliant metallic circular transition element is disposed structurally between the radome and the body. The transition element includes an elongated compliant arm region and a crossbar region positioned adjacent to the radome such that a lower margin surface of the radome rests against an upper side of the crossbar region. A brazed butt joint is formed between the lower margin surface of the radome and the upper side of the crossbar region of the transition element. A second brazed lap joint is formed between the vehicle body and the elongated compliant arm of the transition element.

Abstract: In the case where ohmic electrodes are formed on a semiconductor wafer, first of all, an insulating layer is formed on the semiconductor wafer, then a resist layer is formed on the insulating layer. Next, apertures for forming electrodes are formed in first regions of the resist layer corresponding to regions where the electrodes are formed, while dummy apertures are also formed in a second region of the resist layer in a rest part other than the first regions. Thereafter, the insulating layer is etched using the resist layer as a mask. With the resist layer remaining, electrode material is accumulated on the surface of the semiconductor wafer, and thereafter, the resist layer is removed. As a result, electrodes with desirable ohmic characteristics are stably formed.

Abstract: A dependable ohmic contact with consistently low specific contact resistance (<1.times.10.sub.-6 .OMEGA.-cm.sup.2) to n-type GaAs (10) is produced by a three or four step procedure. The procedure, which is employed following implantation to form doped regions in the GaAs substrate for contacting thereto, comprises: (a) adsorbing or reacting sulfur or a sulfur-containing compound (26) with the GaAs surface (10') at locations where the contact metal (28) is to be deposited; (b) forming a metal contact layer (28) on the treated portions of the GaAs surface; (c) optionally forming a protective layer (30) over the metal contact; and (d) heating the assembly (metal and substrate) to form the final ohmic contact. The surface treatment provides a lower specific contact resistance of the ohmic contact. Elimination of gold in the ohmic contact further improves the contact, since intermetallic compounds formed between gold and aluminum interconnects ("purple plague") are avoided.

Abstract: A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (.beta.) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa.

Abstract: An ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics is disclosed. A non-single crystal InAs layer, Ni film, WSi film and W film are sequentially deposited on an n.sup.+ -type GaAs substrate by sputtering, etc. and subsequently patterned by lift-off, etc. to make a multi-layered structure for fabricating ohmic electrodes. The structure is then annealed first at, e.g. 300.degree. C. for 30 minutes and next at, e.g. 650.degree. C. for one second to fabricate an ohmic electrode.

Abstract: Molecular beam epitaxy (202) with growing layer thickness and doping control (206) by feedback of sensor signals such as spectrosceopic ellipsometer signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes and hetrojunction bipolar transistors with doped and undoped GaAs layers, AlGaAs and InGaAs.

Abstract: A method of fabricating a bipolar transistor includes successively growing a collector layer, a base layer, and a crystalline mask layer on a semiconductor substrate; forming an opening in the crystalline mask layer to expose a portion of the base layer; growing an emitter layer on the crystalline mask layer and on the base layer exposed in the opening of the mask layer; forming an emitter electrode on the emitter layer; removing part of the emitter layer using the emitter electrode as a mask; removing the crystalline mask layer; forming a first resist pattern for formation of base electrodes; forming base electrodes using the first resist pattern and the emitter electrode as masks; removing the first resist pattern; forming a second resist pattern for formation of collector electrodes covering base electrodes and the emitter electrode; using the second resist pattern as a mask, removing portions of the base layer and the collector layer; and forming collector electrodes in contact with the collector layer.

Abstract: A method of fabricating semiconductor devices with a passivated surface includes providing a contact layer on a substrate so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other and to the substrate and the contact layer, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually and selectively etched to define an electrode contact area and to expose the inter-electrode surface area. The exposed inter-electrode surface area is passivated, either subsequent to or during the etching of the first layer. A metal contact is formed in the electrode contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

Abstract: A submicron emitter heterojunction bipolar transistor and a method for fabricating the same is disclosed. The fabrication process includes lattice matched growth of subcollector, collector, base, emitter, and emitter cap layers in sequential order on a semi-insulating semiconductor substrate. An emitter cap mesa, an emitter/base/collector mesa and a subcollector mesa are formed. Dielectric platforms are formed extending the base/collector layers laterally. Sidewalls are formed on the sides of emitter cap mesa and the sides of the extended base/collector layers and undercuts are etched into the emitter layer and the upper portion of the subcollector layer. This forms an overhang on the emitter cap mesa with respect to the emitter layer and an overhang on the base/collector layers with respect to the upper portion of the subcollector layer.

Abstract: A solution of hydrogen peroxide ?H.sub.2 O.sub.2 !, citric acid ?HOC(CH.sub.2 COOH).sub.2 COOH.H.sub.2 O!, and a salt of citric acid such as potassium citrate ?HOC(CH.sub.2 COOK).sub.2 COOK.H.sub.2 O!, and hydrogen peroxide ?H.sub.2 O.sub.2 !, in a proper pH range, selectively etches GaAs-containing Group III-V compounds in the presence of other Group III-V compounds. As an illustration, Al.sub.y Ga.sub.1-y As is selectively etched in the presence of Al.sub.x Ga.sub.1-x As (0.ltoreq.y<0.2 & x>0.2) when the pH range of the etchant solution is between approximately 3 and 6. The etchant solution described herein may be utilized in the fabrication of, for example, high-frequency transistors exhibiting improved saturated current (I.sub.dss) and threshold voltage (V.sub.th) uniformity.