Oxidic Conductor (e.g., Indium Tin Oxide, Etc.) Patents (Class 438/608)
  • Patent number: 10103027
    Abstract: Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process is performed on a metal nitride layer in a film stack, thereby removing oxygen atoms disposed within layers of the film stack and, in some embodiments eliminating an oxygen-containing interfacial layer disposed within the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift. Further, the metal gate structure operates with an increased leakage current that is as little as one quarter the increase in leakage current associated with a similar metal gate structure formed via conventional techniques.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: October 16, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Johanes S. Swenberg, Wei Liu, Houda Graoui, Shashank Sharma
  • Patent number: 9301398
    Abstract: A transparent conductive film 1 includes: a substrate film 11 composed of a transparent resin; a high refractive index coat layer 12 formed on a surface of the substrate film 11, and having an optical refractive index higher than that of the substrate film 11; a low refractive index coat layer 13 formed on a surface of the high refractive index coat layer 12, and having an optical refractive index lower than that of the high refractive index coat layer 12; a moisture-proof underlying layer 14 formed on a surface of the low refractive index coat layer 13 and composed of silicon oxide; and a transparent wiring layer 15 patterned on a surface of the underlying layer 14 and composed of crystalline ITO having an optical refractive index higher than the underlying layer 14. The crystallite size of ITO in the transparent wiring layer 15 is 9 nm or less.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: March 29, 2016
    Assignee: KITAGAWA INDUSTRIES CO., LTD.
    Inventors: Yasuhiro Kawaguchi, Ken Furuta
  • Patent number: 9080239
    Abstract: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daewon Yang, Kangguo Cheng, Pavel Smetana, Richard S. Wise, Keith Kwong Hon Wong
  • Patent number: 9040982
    Abstract: An electrical device with light-responsive layers is disclosed. One or more electrically conducting stripes, each insulated from each other, are deposited on a smooth surface of a substrate. Then metal oxide layers, separated by a composite diffusion layer, are deposited. On top of the topmost metal oxide layer another set of elongated conductive strips are disposed in contact with the topmost metal oxide layer such that junctions are formed wherever the top and bottom conducting stripes cross. The resulting device is light responsive only when a certain sign of bias voltage is applied and may be used as a photodetector. An advantage that may be realized in the practice of some disclosed embodiments of the device is that this device may be formed without the use of conventional patterning, thereby significantly reducing manufacturing difficulty.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: May 26, 2015
    Assignee: Research Foundation of the City University of New York
    Inventor: Fred J. Cadieu
  • Publication number: 20150138494
    Abstract: The method of manufacturing a device substrate includes forming a surface modifying layer on a process substrate. The surface modifying layer has a different hydrophobicity from that of the process substrate. The process substrate is disposed on a carrier substrate. The surface modifying layer is disposed between the process substrate and the carrier substrate. A device is formed on the process substrate. The process substrate is separated from the carrier substrate.
    Type: Application
    Filed: June 10, 2014
    Publication date: May 21, 2015
    Inventors: TaeHwan KIM, Myeonghee Kim, Youngbae Kim, Jong Seong Kim, Myunghwan Park, Jonghwan Lee
  • Patent number: 9012251
    Abstract: Disclosed is a method for preventing a short circuit between metal wires in an organic light emitting diode display device. The method includes: forming an inorganic layer on a substrate; forming an opening in the inorganic layer for exposing a part of the substrate; forming a metal layer on the inorganic layer, the metal layer including two metal wires respectively positioned at two sides of the opening; forming an organic layer on the two metal wires of the metal layer; and forming an indium tin oxide layer on the organic layer. The present invention can ensure that the short circuit does not occur between the metal wires by forming the opening in the inorganic layer.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: April 21, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co. Ltd.
    Inventor: Kai-Yuan Ko
  • Patent number: 8980680
    Abstract: A method for fabricating a solar cell element, the method comprising a step (a) of preparing a laminate and a chamber, a step (b) of bringing the laminate into contact with the aqueous solution in such a manner that the second surface is immersed in the aqueous solution after the step (a); a step (c) of applying a voltage difference between an anode electrode and the laminate under an atmosphere of the inert gas to form a Zn layer on the second surface after the step (b); and a step (d) of exposing the Zn layer to oxygen so as to convert the Zn layer into a ZnO crystalline layer after the step (c).
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: March 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomoyuki Komori, Tetsuya Asano
  • Publication number: 20150072501
    Abstract: A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 12, 2015
    Inventor: Hiroyuki ODE
  • Patent number: 8969213
    Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
  • Publication number: 20150056798
    Abstract: Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.
    Type: Application
    Filed: October 3, 2014
    Publication date: February 26, 2015
    Inventors: Noel Rocklein, Durai Ramaswamy, Dale W. Collins, Swapnil Lengade, Srividya Krishnamurthy, Mark S. Korber
  • Patent number: 8956965
    Abstract: A method of manufacturing a display panel having a display part and a terminal part each formed on a different area on a TFT substrate, comprising: a step of forming the display part on the TFT substrate; a step of forming a conductive layer of a conductive metal oxide or a metal on an area where the terminal part is to be formed; a step of forming a chemical vapor deposition layer of an inorganic compound by a chemical vapor deposition method so that the chemical vapor deposition layer covers the display part and comes into contact at least with an upper surface of the conductive layer and so that the upper surface of the conductive layer alters; and a step of removing a portion of the chemical vapor deposition layer on the conductive layer.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: February 17, 2015
    Assignee: Panasonic Corporation
    Inventor: Takashi Osako
  • Patent number: 8945990
    Abstract: Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventors: Holger Torwesten, Manfred Mengel, Stefan Schmid, Soon Lock Goh, Swee Kah Lee
  • Patent number: 8946075
    Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Patent number: 8940633
    Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Patent number: 8933544
    Abstract: An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: January 13, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Yin Qian, Tiejun Dai, Howard E. Rhodes, Hongli Yang
  • Patent number: 8932914
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 13, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
  • Publication number: 20140349413
    Abstract: A method of manufacturing a semiconductor device may include forming a material layer on a substrate, performing a selective oxidation process to form a capping oxide layer on a first surface of the material layer, wherein a second surface of the material layer is not oxidized, and etching the material layer through the second surface to form a material pattern. An etch rate of the capping oxide layer is less than an etch rate of the material layer. A semiconductor device may include a lower electrode on a substrate, a data storage part on a top surface of the lower electrode, an upper electrode on the data storage part, and a capping oxide layer arranged on at least a portion of a top surface of the upper electrode. The capping oxide layer may include an oxide formed by oxidation of an upper surface of the upper electrode.
    Type: Application
    Filed: March 25, 2014
    Publication date: November 27, 2014
    Inventors: Sungyoon CHUNG, JINHYE BAE, HYUNGJOON KWON, JONGCHUL PARK, WONJUN LEE
  • Patent number: 8895428
    Abstract: Disclosed is a manufacture method of the thin film transistor array, comprising depositing a first transparent conductive layer and a first metal layer to perform patterning for forming a common electrode, a gate electrode and a transparent electrode array; depositing an insulating layer, an active layer, an ohmic contact layer and a second metal layer to perform patterning for forming a source and a drain; depositing a second transparent conductive layer to perform patterning for forming a source contact layer, a drain contact layer and a pixel electrode array connected to the drain contact layer. The present invention simplifies the manufacture process, saves the cost and time for the manufacture.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: November 25, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Shijian Qin
  • Patent number: 8895427
    Abstract: A zinc oxide transparent electroconductive oxide has been difficult to use as a substrate having a transparent electrode because the oxide, when configured as a thin film, because of increased resistivity due to air and/or moisture exposure. Though doping can inhibit increase of resistance to some extent, there has been difficulty in selecting a type and an amount of a doping substance and because doping causes high initial resistance. A substrate having a transparent electrode with stable resistivity against various environments is produced by a magnetron sputtering method using a target composed of a zinc oxide transparent electroconductive oxide containing 0.50 to 2.75% silicon dioxide by weight relative to the oxide.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: November 25, 2014
    Assignee: Kaneka Corporation
    Inventors: Takashi Kuchiyama, Kenji Yamamoto
  • Patent number: 8890195
    Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taisuke Sato, Toshiyuki Oka, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8889440
    Abstract: An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 18, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Yung-Chang Chen, Hsin-Hsien Wu, Ming Shing Lee, Huai-En Lai, Fu-Wen Liu, Andy Wu
  • Patent number: 8878212
    Abstract: A light emitting device includes a substrate, at least one electrode, a first contact layer, a second contact layer, a light emitting structure layer, and an electrode layer. The electrode is disposed through the substrate. The first contact layer is disposed on a top surface of the substrate and electrically connected to the electrode. The second contact layer is disposed on a bottom surface of the substrate and electrically connected to the electrode. The light emitting structure layer is disposed above the substrate at a distance from the substrate and electrically connected to the first contact layer. The light emitting structure layer includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The electrode layer is disposed on the light emitting structure layer.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: November 4, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Woo Sik Lim, Sung Kyoon Kim, Sung Ho Choo, Hee Young Beom
  • Patent number: 8877569
    Abstract: An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Hotaka Maruyama, Hiromichi Godo, Daisuke Kawae, Shunpei Yamazaki
  • Patent number: 8871617
    Abstract: In one aspect, methods of forming mixed metal thin films comprising at least two different metals are provided. In some embodiments, a mixed metal oxide thin film is formed by atomic layer deposition and subsequently reduced to a mixed metal thin film. Reduction may take place, for example, in a hydrogen atmosphere. The presence of two or more metals in the mixed metal oxide allows for reduction at a lower reduction temperature than the reduction temperature of the individual oxides of the metals in the mixed metal oxide film.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 28, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami J. Pore, Eva Tois
  • Patent number: 8871628
    Abstract: An electrode structure comprises a semiconductor junction comprising an n-type semiconductor layer and a p-type semiconductor layer; a hole exnihilation layer on the p-type semiconductor layer; and a transparent electrode layer on the hole exnihilation layer. The electrode structure further comprises a conductive layer between the hole exnihilation layer and the transparent electrode layer. In the electrode structure, one or more of the hole exnihilation layer, the conductive layer and the transparent electrode layer may be formed by an atomic layer deposition. In the electrode structure, a transparent electrode formed of a degenerated n-type oxide semiconductor does not come in direct contact with a p-type semiconductor, and thus, annihilation or recombination of holes generated in the p-type semiconductor can be reduced, which increases the carrier generation efficiency.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: October 28, 2014
    Assignee: Veeco ALD Inc.
    Inventor: Sang In Lee
  • Patent number: 8866137
    Abstract: A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: October 21, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Won Lee, Woo Geun Lee, Kap Soo Yoon, Ki-Won Kim, Hyun-Jung Lee, Hee-Jun Byeon, Ji-Soo Oh
  • Patent number: 8859332
    Abstract: The present invention relates to a liquid phase process for producing indium oxide-containing layers, in which a coating composition preparable from a mixture comprising at least one indium oxide precursor and at least one solvent and/or dispersion medium, in the sequence of points a) to d), a) is applied to a substrate, and b) the composition applied to the substrate is irradiated with electromagnetic radiation, c) optionally dried and d) converted thermally into an indium oxide-containing layer, where the indium oxide precursor is an indium halogen alkoxide of the generic formula InX(OR)2 where R is an alkyl radical and/or alkoxyalkyl radical and X is F, Cl, Br or I and the irradiation is carried out with electromagnetic radiation having significant fractions of radiation in the range of 170-210 nm and of 250-258 nm, to the indium oxide-containing layers producible with the process, and the use thereof.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 14, 2014
    Assignee: Evonik Degussa GmbH
    Inventors: Juergen Steiger, Duy Vu Pham, Heiko Thiem, Alexey Merkulov, Arne Hoppe
  • Patent number: 8835236
    Abstract: A method for manufacturing an oxide semiconductor thin film transistor (TFT) is provided, which includes the steps below. A source electrode and a drain electrode are provided. A patterned insulating layer is formed to partially cover the source electrode and the drain electrode, and expose a portion of the source electrode and a portion of the drain electrode. An oxide semiconductor layer is formed to contact the portion of the source electrode and the portion of the drain electrode. A gate electrode is provided. A gate dielectric layer positioned between the oxide semiconductor layer and the gate electrode is provided. An oxide semiconductor TFT is also provided herein.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 16, 2014
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Hsi-Ming Chang
  • Patent number: 8835247
    Abstract: A sensor array for detecting particles, the sensor array comprising a substrate having a plurality of holes, a plurality of electronic sensor chips each having a sensor active region being sensitive to the presence of particles to be detected, and an electric contacting structure adapted for electrically contacting the plurality of electronic sensor chips, wherein the plurality of electronic sensor chips and/or the electric contacting structure are connected to the substrate in such a manner that the plurality of holes in combination with the plurality of electronic sensor chips and/or the electric contacting structure form a plurality of wells with integrated particle sensors.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: September 16, 2014
    Assignee: NXP, B.V.
    Inventors: Michel De Langen, Ger Reuvers, Frans Meeuwsen
  • Publication number: 20140252425
    Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Patent number: 8772150
    Abstract: Disclosed herein is a method of forming a p-type zinc oxide thin film. A zinc oxide layer and an antimony oxide layer are alternately stacked one above another on a substrate, forming a superlattice layer. The superlattice layer is modified into a p-type zinc oxide thin film by annealing. Upon annealing, zinc atoms of the zinc oxide layer are diffused into the antimony oxide layer and antimony atoms of the antimony oxide layer are diffused into the zinc oxide layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: July 8, 2014
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Seong Ju Park, Yong Seok Choi, Jang Won Kang
  • Patent number: 8748879
    Abstract: A semiconductor device, a thin film transistor, and a method for producing the same capable of decreasing the management cost, and capable of decreasing the production steps to reduce the production cost are proposed. A method for producing a thin film transistor 2 provided with a semiconductor which is composed of a prescribed material and serves as an active layer 41 and a conductor which is composed of a material having the same composition as that of the prescribed material and serves as at least one of a source electrode 51, a drain electrode 53 and a pixel electrode 55, which includes the steps of simultaneously forming into a film an object to be processed and a conductor (a source electrode 51, a source wire 52, a drain electrode 53, a drain wire 54 and a pixel electrode 55) which are composed of the amorphous prescribed material, followed by simultaneous shaping, and crystallizing the object to be processed which has been shaped to allow it to be the active layer 41.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: June 10, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Kazuyoshi Inoue, Futoshi Utsuno, Masashi Kasami, Katsunori Honda
  • Patent number: 8741712
    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: June 3, 2014
    Assignees: Intermolecular, Inc., Elpidia Memory, Inc.
    Inventors: Tony P. Chiang, Wim Y. Deweerd, Sandra G Malhotra
  • Publication number: 20140138831
    Abstract: Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (?m) or less.
    Type: Application
    Filed: January 15, 2013
    Publication date: May 22, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Houssam W. Jomaa, Omar J. Bchir, Milind P. Shah, Manuel Aldrete, Chin-Kwan Kim
  • Patent number: 8728928
    Abstract: A method for producing a solar cell having a substrate, having an inner face, wherein said inner face is designed to receive a conductive element based on molybdenum, wherein the method comprises forming several layers based on molybdenum on the substrate, at least one of the layers being enriched in molybdenum oxide, wherein the layers are formed by a magnetron sputtering method, and wherein the layer enriched with molybdenum oxide is obtained by injecting oxygen, ozone or a mixture of gas containing oxygen in atomic form during the formation of the molybdenum-based conductive element.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: May 20, 2014
    Assignee: Saint-Gobain Glass France
    Inventors: Stephane Auvray, Nikolas Janke
  • Publication number: 20140084292
    Abstract: A method of connecting to a first metal layer in a semiconductor flow process. Disclosed embodiments connect to the first metal layer by etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer, depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole, and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: Apple Inc.
    Inventors: Ming-Chin Hung, Young Bae Park, Chun-Yao Huang, Shih Chang Chang, John Z. Zhong
  • Patent number: 8673760
    Abstract: One illustrative method disclosed herein includes forming a seed layer above a substrate that includes a conductive region, wherein the seed layer is comprised of a metal-containing material, forming a nucleation layer on the seed layer, wherein the nucleation layer is comprised of a transition metal oxide ceramic material, and performing a thermal treatment process at a temperature so as to generate a plurality of spaced-apart, vertically oriented alloy structures, wherein the alloy structures are comprised of at least one material from the seed layer and at least one material from the nucleation layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Manfred Heinrich Moert
  • Patent number: 8658887
    Abstract: Provided in this invention is a low-cost substrate provided with a transparent conductive film for photoelectric conversion device, which can improve performance of the photoelectric conversion device by enhanced light confinement effect achieved with effectively increased surface unevenness of the substrate. A method for manufacturing said substrate and a photoelectric conversion device using said substrate which can show improved performance are also provided. The substrate provided with the transparent conductive film for the photoelectric conversion device comprises a transparent insulating substrate and a transparent electrode layer containing at least zinc oxide deposited on the transparent insulating substrate, wherein the transparent electrode layer is composed of a double layer structure wherein first and second transparent conductive films are deposited in this order from a substrate side.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: February 25, 2014
    Assignee: Kaneka Corporation
    Inventor: Yuko Tawada
  • Patent number: 8624253
    Abstract: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion of a connecting wiring on an active matrix substrate is electrically connected to an FPC by an anisotropic conductive film. The connecting wiring is made of a lamination film of a metallic film and a transparent conductive film. In the connecting portion with the anisotropic conductive film, a side surface of the connecting wiring is covered with a protecting film made of an insulating material, thereby exposure to air of the metallic film can be avoided.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20130330920
    Abstract: A high-frequency, hydrogen-based radio-frequency (RF) plasma is used to reduce a metal oxide and other contaminant disposed in an aperture that is formed in an ultra-low k dielectric material. Because the frequency of the plasma is at least about 40 MHz and the primary gas in the plasma is hydrogen, metal oxide can be advantageously removed without damaging the dielectric material.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 12, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Guojun Liu, Xianmin Tang, Anantha Subramani, Wei W. Wang
  • Patent number: 8604335
    Abstract: A laminate for dye-sensitized solar cell comprising a plastic film of which the thermal shrinkage in the machine direction thereof when heat-treated at 200° C. for 10 minutes is from ?1.5 to +0.5%, and a transparent conductive layer provided on the film, which comprises essentially indium oxide with zinc oxide added thereto and has a surface resistivity of at most 40 ?/square, may give a highly-durable and flexible, dye-sensitized solar cells having high photovoltaic power generation efficiency.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: December 10, 2013
    Assignees: Teijin Dupont Films Japan Limited, Teijin Limited
    Inventors: Koji Kubo, Rei Nishio, Hiroshi Hara, Kei Mitzutani
  • Patent number: 8586392
    Abstract: A manufacturing method of a display device including a gate electrode film, a first electrode film, a second electrode film, and a conductive film connected to the first electrode film and formed of a conductive layer including a first conductive layer and a second conductive layer formed overlapping the first conductive layer. The method includes the steps of forming the first electrode film and the second electrode film, forming the conductive layer such that the conductive layer is connected to the first electrode film and the second electrode film, and forming the conductive film by removing regions other than predetermined regions of the conductive layer, wherein the conductive layer forming step includes the steps of forming the first conductive layer on the respective upper surfaces of the first electrode film and the second electrode film and forming the second conductive layer on the upper surface of the first conductive layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: November 19, 2013
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Jun Gotoh, Eisuke Hatakeyama, Kenji Anjo, Yoshitomo Ogishima
  • Patent number: 8580671
    Abstract: A method of manufacturing a semiconductor device of the present invention includes a first step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminum, zirconium, strontium, titanium, barium, tantalum, niobium, on a substrate having a metal thin film formed on the surface, at a first temperature allowing no oxidization of the metal thin film to occur, and allowing the metal oxide film to be set in an amorphous state; and a second step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminum, zirconium, strontium, titanium, barium, tantalum, niobium on the metal oxide film formed in the first step, up to a target film thickness, at a second temperature exceeding the first temperature.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Sadayoshi Horii, Yoshinori Imai, Mika Karasawa
  • Publication number: 20130264688
    Abstract: An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 10, 2013
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Yin Qian, Hsin-Chih Tai, Duli Mao, Tiejun Dai, Howard E. Rhodes, Hongli Yang
  • Patent number: 8530285
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
  • Publication number: 20130217180
    Abstract: Disclosed are new methods of fabricating metal oxide thin films and nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° C.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 22, 2013
    Applicants: POLYERA CORPORATION, NORTHWESTERN UNIVERSITY
    Inventors: NORTHWESTERN UNIVERSITY, POLYERA CORPORATION
  • Patent number: 8513118
    Abstract: It is intended to provide a production method that enables at least one of improvement in transparency, reduction in sheet resistance, homogenization in planar distribution of sheet resistance, and reduction in contact resistance related to a contact layer regarding a transparent conductive oxide film included in a compound semiconductor light-emitting device. A method for producing a compound semiconductor light-emitting device includes depositing on a substrate a compound semiconductor stacked-layer body including a light-emitting layer, depositing a transparent conductive oxide film on the compound semiconductor stacked-layer body, and annealing the transparent conductive oxide film and thereafter cooling the same in a vacuum atmosphere.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: August 20, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimi Tanimoto, Takanori Sonoda
  • Publication number: 20130196469
    Abstract: Disclosed are new methods of fabricating metal oxide thin films and nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° C.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 1, 2013
    Applicants: Polyera Corporation, Northwestern University
    Inventors: Northwestern University, Polyera Corporation
  • Publication number: 20130160844
    Abstract: This invention provides a thick-film composition for printing the front-side of a solar cell device having one or more insulating layers. The composition comprises a bismuth oxide comprising glass frit and antimony oxide as part of the glass frit or an additive. The invention further refers to a process for preparing a semiconductor device by use of the thick-film composition and an article, especially a solar cell comprising the semiconductor device. The solar cells show improved efficiency.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 27, 2013
    Applicant: HERAEUS PRECIOUS METALS GMBH & CO. KG
    Inventor: HERAEUS PRECIOUS METALS GMBH & CO.KG
  • Publication number: 20130130491
    Abstract: A method of manufacturing a display panel having a display part and a terminal part each formed on a different area on a TFT substrate, comprising: a step of forming the display part on the TFT substrate; a step of forming a conductive layer of a conductive metal oxide or a metal on an area where the terminal part is to be formed; a step of forming a chemical vapor deposition layer of an inorganic compound by a chemical vapor deposition method so that the chemical vapor deposition layer covers the display part and comes into contact at least with an upper surface of the conductive layer and so that the upper surface of the conductive layer alters; and a step of removing a portion of the chemical vapor deposition layer on the conductive layer.
    Type: Application
    Filed: January 4, 2013
    Publication date: May 23, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION