Oxidic Conductor (e.g., Indium Tin Oxide, Etc.) Patents (Class 438/608)
  • Publication number: 20110147938
    Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: Jin-Yeong KANG
  • Patent number: 7960746
    Abstract: A low resistance electrode and a compound semiconductor light emitting device including the same are provided. The low resistance electrode deposited on a p-type semiconductor layer of a compound semiconductor light emitting device including an n-type semiconductor layer, an active layer, and the p-type semiconductor layer, including: a reflective electrode which is disposed on the p-type semiconductor layer and reflects light being emitted from the active layer; and an agglomeration preventing electrode which is disposed on the reflective electrode layer in order to prevent an agglomeration of the reflective electrode layer during an annealing process.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: June 14, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Joon-seop Kwak, Tae-yeon Seong, Jae-hee Cho, June-o Song, Dong-seok Leem, Hyun-soo Kim
  • Patent number: 7956359
    Abstract: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion (182) of a connecting wiring (183) on an active matrix substrate is electrically connected to an FPC (191) by an anisotropic conductive film (195). The connecting wiring (183) is manufactured in the same process with a source/drain wiring of a TFT on the active matrix substrate, and is made of a lamination film of a metallic film and a transparent conductive film. In the connecting portion with the anisotropic conductive film (195), a side surface of the connecting wiring (183) is covered with a protecting film (173) made of an insulating material.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: June 7, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7955645
    Abstract: A semiconductor wafer (10) is structured such that fine structures (3), such as membranes, bridges or tongues, with a thickness d<<D are formed, wherein D designates the thickness of the semiconductor wafer (10). Then particles of a desired material are applied. A temporal or spatial temperature gradient is generated in the semiconductor wafer (10), e.g. by progressive heating. In such a heating process the fine structures heat up more quickly and become hotter than the remaining wafer because they have a smaller heat capacity per area and cannot carry off heat as quickly. In this manner, the fine structures can be heated to a temperature that allows a sintering of the particles. For coating the semiconductor wafer (10) is brought into a reactor (11). A precursor compound of a metal is provided and fed to the reactor (11), where a reaction takes place during which the metal is transformed to a final compound and is deposited in the form of particles on the semiconductor wafer (10).
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: June 7, 2011
    Assignee: Sensirion AG
    Inventors: Felix Mayer, Christoph Kleinlogel
  • Publication number: 20110097841
    Abstract: A photovoltaic device including a rear electrode which may also function as a rear reflector. In certain example embodiments of this invention, the rear electrode includes a metallic based reflective film that is oxidation graded, so as to be more oxided closer to a rear substrate (e.g., glass substrate) supporting the electrode than at a location further from the rear substrate. In other words, the rear electrode is oxidation graded so as to be less oxided closer to a semiconductor absorber of the photovoltaic device than at a location further from the semiconductor absorber in certain example embodiments. In certain example embodiments, the interior surface of the rear substrate may optionally be textured so that the rear electrode deposited thereon is also textured so as to provide desirable electrical and reflective characteristics. In certain example embodiments, the rear electrode may be of or include Mo and/or MoOx, and may be sputter-deposited using a combination of MoOx and Mo sputtering targets.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 28, 2011
    Applicant: Guardian Industries Corp.
    Inventors: Alexey Krasnov, Willem den Boer, Scott V. Thomsen, Leonard L. Boyer, JR.
  • Publication number: 20110097890
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted meta
    Type: Application
    Filed: January 3, 2011
    Publication date: April 28, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takamasa USUI, Tadayoshi WATANABE, Hayato NASU
  • Patent number: 7927996
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain tungsten and monolayers that contain indium are deposited onto a substrate and subsequently processed to form tungsten-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: April 19, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7923837
    Abstract: A microelectronic device includes a non-polymeric substrate, an organic interlayer, and a indium tin oxide layer formed on the organic interlayer; the indium tin oxide layer including an ablated feature within said indium tin oxide layer, wherein said indium tin oxide layer is formed by an indium tin oxide solution that is laser ablated prior to sintering. Applicant respectfully submits that the above amendments bring the Abstract into compliance with MPEP ยง608.01 (b). Accordingly, Applicant respectfully requests reconsideration and withdrawal of the objection to the abstract.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: April 12, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chinmay Betrabet, Curt Lee Nelson
  • Patent number: 7915062
    Abstract: A TFT array substrate includes a TFT having an ohmic contact film and a source electrode and a drain electrode formed on the ohmic contact film. It also includes a pixel electrode electrically connected with the drain electrode. The source electrode and the drain electrode are made of an Al alloy containing Ni as an additive.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: March 29, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinichi Yano, Tadaki Nakahori, Nobuaki Ishiga
  • Patent number: 7915152
    Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 29, 2011
    Assignee: Cree, Inc.
    Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
  • Publication number: 20110057314
    Abstract: The invention relates to conductive pastes including one or more acids, or acid-forming components for silicon semiconductor devices and photovoltaic cells.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 10, 2011
    Applicant: E. I. DU PONT DE NEMOURS AND COMPANY
    Inventor: Alan Frederick Carroll
  • Publication number: 20110033974
    Abstract: A method for fabricating a hollow nanotube structure is disclosed. The method includes the steps of providing a substrate, developing a plurality of nanowires on the substrate with a predetermined size on the seed layer at relatively low temperature by a hydro-thermal growth method, forming an outer covering layer on the surfaces of the nanowires, selectively etching an upper end of the outer coating layer to expose an upper end of the nanowires and removing the nanowires to remain the hollow outer coating layer to form a plurality of hollow nanotubes. The method can simplify the nanotube manufacturing process, increase the dimension precision of the nanotubes and enhance the photoelectric properties of micro-electro-mechanical elements.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Inventors: Shui-Jinn WANG, Der-Ming Kuo, Wei-Chih Isai, Chih-Ren Tseng
  • Publication number: 20110008955
    Abstract: A method of manufacturing a semiconductor device including alternately repeating a process of forming a first metal oxide film including a first metal element and a process of forming a second metal oxide film including a second metal element on a substrate accommodated in a processing chamber, so as to form a third metal oxide film including the first and second metal elements with a predetermined composition ratio on the substrate. One of the first and second metal elements of the third metal oxide film has a concentration higher than a concentration of the other, and one of the first and second metal oxide films including the higher-concentration metal element is formed in a chemical vapor deposition (CVD) mode or an atomic layer deposition (ALD) saturation mode, and the other of the first and second metal oxide films is formed in an ALD unsaturation mode.
    Type: Application
    Filed: June 24, 2010
    Publication date: January 13, 2011
    Applicants: HITACHI-KOKUSAI ELECTRIC INC., NEC ELECTRONICS CORP.
    Inventors: Sadayoshi HORII, Atsushi SANO, Masahito KITAMURA, Yoshitake KATO
  • Publication number: 20100323512
    Abstract: [Problems] There is provided a metal oxide film forming method capable of controlling a film thickness of a metal oxide even if the metal oxide is subject to a self-limited thickness. [Means for Solving the Problems] A metal oxide film forming method includes a process (1) of supplying a metal source gas to a surface of a base before a temperature of the base reaches a film formation temperature of a metal oxide film; and a process (2) of setting the temperature of the base to be equal to or higher than the film formation temperature and forming the metal oxide film on the base by making a reaction between the metal source gas supplied to the surface of the base and residual moisture on the surface of the base.
    Type: Application
    Filed: May 18, 2010
    Publication date: December 23, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kenji Matsumoto, Hidenori Miyoshi, Hitoshi Itoh, Hiroshi Sato
  • Publication number: 20100308462
    Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells. The thick film conductor compositions include one or more electrically functional powders and one or more glass frits dispersed in an organic medium. The thick film compositions may also include one or more additive(s). Exemplary additives may include metals, metal oxides or any compounds that can generate these metal oxides during firing.
    Type: Application
    Filed: June 8, 2009
    Publication date: December 9, 2010
    Applicant: E. I. DU PONT DE NEMOURS AND COMPANY
    Inventors: TAKUYA KONNO, BRIAN J. LAUGHLIN, HISASHI MATSUNO
  • Publication number: 20100300522
    Abstract: A method for fabricating a contact (240) for a solar cell (200). The method includes providing a solar cell substrate (210) with a surface that is covered or includes an antireflective coating (220). For example, the substrate (210) may be positioned adjacent or proximate to an outlet of an inkjet printer (712) or other deposition device. The method continues with forming a burn through layer (230) on the coating (220) by depositing a metal oxide precursor (e.g., using an inkjet or other non-contact printing method to print or apply a volume of liquid or solution containing the precursor). The method includes forming a contact layer (240) comprising silver over or on the burn through layer (230), and then annealing is performed to electrically connect the contact layer (240) to the surface of the solar cell substrate (210) through a portion of the burn through layer (230) and the coating (220).
    Type: Application
    Filed: November 3, 2008
    Publication date: December 2, 2010
    Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
    Inventors: David S. Ginley, Tatiana Kaydanova, Alexander Miedaner, Calvin J. Curtis, Marinus Franciscus Antonius Maria van Hest
  • Patent number: 7838410
    Abstract: A method of electrically connecting an element to wiring includes the steps of forming a conductive fixing member precursor layer at least on wiring provided on a base; and arranging an element having a connecting portion on the wiring such that the connecting portion contacts the conductive fixing member precursor layer, and then heating the conductive fixing member precursor layer to form a conductive fixing member latter, thereby fixing the connecting portion of the element to the wiring, with the conductive fixing member layer therebetween, wherein the conductive fixing member precursor layer is composed of a solution-tape conductive material.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: November 23, 2010
    Assignee: Sony Corporation
    Inventors: Naoki Hirao, Yasunobu Iwakoshi, Katsuhiro Tomoda, Huy Sam
  • Publication number: 20100282300
    Abstract: The present invention relates to a substrate notably designed to enter into the constitution of a solar cell, of which one face, called the inner face, is designed to receive a molybdenum-based conductive element. This substrate is characterized in that the conductive element is formed of several layers based on molybdenum, at least one of these layers being enriched with molybdenum oxide. The present invention also relates to solar cells employing such a substrate and a method for producing same.
    Type: Application
    Filed: October 8, 2008
    Publication date: November 11, 2010
    Applicant: SAINT-GOBAIN GLASS FRANCE
    Inventors: Stephane Auvray, Nikolas Janke
  • Patent number: 7825021
    Abstract: It is an object of the present invention to provide a method for manufacturing a highly reliable display device with a preferable yield. A method for manufacturing a display device according to the invention comprises the steps of: forming a first electrode including a conductive material added with a material which prevents crystallization; forming a layer containing an organic compound over the first electrode by heating the first electrode under a reduced pressure at temperatures of 350ยฐ C. or higher; and forming a second electrode over the layer containing an organic compound. It is preferable to perform the heat treatment at temperatures of 350ยฐ C. or higher, preferably, 375ยฐ C. or higher for 12 hours or longer. When the first electrode is formed by using indium tin oxide containing silicon oxide, a highly display device can be manufactured.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: November 2, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Kengo Akimoto, Hajime Tokunaga
  • Patent number: 7820525
    Abstract: A method for wafer-to-wafer bonding of a sensor readout circuitry separately fabricated with a silicon substrate to a photodiode device made of non-silicon materials grown from a separate substrate. In preferred embodiments the non-silicon materials are epitaxially grown on a silicon wafer. The bonding technique of preferred embodiments of the present invention utilizes lithographically pre-fabricated metallic interconnects to connect each of a number of pixel circuits on a readout circuit wafer to each of a corresponding number of pixel photodiodes on a photodiode wafer. The metallic interconnects are extremely small (with widths of about 2 to 4 microns) compared to prior art bump bonds with the solder balls of diameter typically larger than 20 microns. The present invention also provides alignment techniques to assure proper alignment of the interconnects during the bonding step.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: October 26, 2010
    Assignee: e-Phocus
    Inventor: Tzu-Chiang Hsieh
  • Publication number: 20100258166
    Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 14, 2010
    Applicant: E.I. DU PONT DE NEMOURS AND COMPANY
    Inventors: Brian J. Laughlin, Alan Frederick Carroll, Kenneth Warren Hang, Yueli Wang, Takuya Konno
  • Publication number: 20100258165
    Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 14, 2010
    Applicant: E.I. DU PONT DE NEMOURS AND COMPANY
    Inventors: Alan Frederick Carroll, Brian J. Laughlin, Kenneth Warren Hang, Yueli Wang
  • Publication number: 20100190331
    Abstract: A method for depositing a film onto a substrate is provided. The substrate is contained within a reactor vessel at a pressure of from about 0.1 millitorr to about 100 millitorr. The method comprises subjecting the substrate to a reaction cycle comprising i) supplying to the reactor vessel a gas precursor at a temperature of from about 20ยฐ C. to about 150ยฐ C. and a vapor pressure of from about 0.1 torr to about 100 torr, wherein the gas precursor comprises at least one organo-metallic compound; and ii) supplying to the reactor vessel a purge gas, an oxidizing gas, or combinations thereof.
    Type: Application
    Filed: September 15, 2009
    Publication date: July 29, 2010
    Inventors: Steven C. Selbrede, Martin Zucker, Vincent Venturo
  • Publication number: 20100159635
    Abstract: Methods for patterning a conductor through oxidation are provided. Devices fabricated using the method include organic transistors having a gate electrode and dielectric layer patterned by the method, source and drain electrodes, and an organic semiconducting layer.
    Type: Application
    Filed: December 24, 2008
    Publication date: June 24, 2010
    Applicant: WEYERHAEUSER COMPANY
    Inventor: Viorel Olariu
  • Publication number: 20100126565
    Abstract: To obtain low resistance and high adhesion at the same time in a solar cell electrode, a conductive paste is offered. A conductive paste for solar cell electrode contains conductive powder, organic medium and glass frit which is mixture of more than one kind of glass frit such as a mixture of glass frit containing at least PbO and glass frit containing at least Bi2O3.
    Type: Application
    Filed: November 19, 2009
    Publication date: May 27, 2010
    Applicant: E. I. DU PONT DE NEMOURS AND COMPANY
    Inventors: Norihiko Takeda, Takuya Konno
  • Patent number: 7713843
    Abstract: In the method of fabricating an optical semiconductor device, a semiconductor layer is formed on an InP region, and includes semiconductor films. A first etching mask is formed on the semiconductor layer. The semiconductor layer is etched through the first etching mask to form a semiconductor mesa and a first marking mesa, each mesa includes an active layer and an InP cladding layer, the InP cladding layer being provided on the active layer. The active layer is made of semiconductor material different from InP. An InP burying region is grown through the first etching mask on a side of the semiconductor mesa and a side of the first marking mesa to bury the semiconductor mesa and the first marking mesa. A second etching mask is formed on the InP burying region after removing the first etching mask, and has an opening located above the first marking mesa. InP in the InP burying region and the first marking mesa is etched through the second etching mask to form a second marking mesa.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: May 11, 2010
    Assignee: Sumitomo Electric Industries Ltd.
    Inventor: Masakazu Narita
  • Publication number: 20100105192
    Abstract: A method of manufacturing a semiconductor device includes: forming an oxide film having a predetermined film thickness on a substrate by repeating a process of forming a predetermined element-containing layer on the substrate by supplying source gas containing a predetermined element into a process vessel accommodating the substrate, and a process of changing the predetermined element-containing layer to an oxide layer by supplying oxygen-containing gas and hydrogen-containing gas into the process vessel that is set below atmospheric pressure, wherein the oxygen-containing gas is oxygen gas or ozone gas, the hydrogen-containing gas is hydrogen gas or deuterium gas, and the temperature of the substrate is in a range from 400ยฐ C. or more to 700ยฐ C. or less in the process of forming the oxide film.
    Type: Application
    Filed: October 28, 2009
    Publication date: April 29, 2010
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota
  • Patent number: 7691758
    Abstract: A method of forming an insulating film according to one embodiment of the present invention, which is a method of forming an insulating film for use in a semiconductor device, performs thermal oxidation of a tantalum nitride film at a temperature range of 200 to 400 degrees centigrade by a wet oxidation process, whereby a tantalum oxide film is formed as the insulating film.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: April 6, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takayuki Iwaki
  • Patent number: 7675075
    Abstract: An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure including a light emitting layer into a plurality of portions. The phosphor film (48) covers an upper surface of the array of the LEDs (6) and a part of every side surface of the array of LEDs (6). Here, the part extends from the upper surface to the light emitting layer.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: March 9, 2010
    Assignee: Panasonic Corporation
    Inventor: Hideo Nagai
  • Patent number: 7663239
    Abstract: In a semiconductor device including: an insulating film (6) formed over a substrate (1); a buried metal interconnect (10) formed in the insulating film (6); and a barrier metal film (A1) formed between the insulating film (6) and the metal interconnect (10), the barrier metal film (A1) includes a metal oxide film (7), a metal compound film (8) and a metal film (9) stacked in this order from a side in which the insulating film (6) exists to a side in which the metal interconnect (10) exists. Elastic modulus of the metal compound film (8) is larger than that of the metal oxide film (7).
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: February 16, 2010
    Assignee: Panasonic Corporation
    Inventors: Atsushi Ikeda, Hideo Nakagawa, Nobuo Aoi
  • Publication number: 20100029025
    Abstract: The present invention relates to a method for manufacturing a light-emitting device. At least one of a light-emitting film forming step, a conductive film forming step and an insulating film forming step is carried out while holding a substrate in a manner that an angle subtended by a surface of the substrate and the direction of gravity is within a range of from 0 to 30ยฐ.
    Type: Application
    Filed: October 9, 2009
    Publication date: February 4, 2010
    Inventors: Shunpei Yamazaki, Takashi Hamada, Satoshi Seo
  • Patent number: 7651876
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed thereon, an insulation layer disposed on the substrate and overlying the gate, a patterned semiconductor layer disposed on the insulation layer, a source and a drain disposed on the patterned semiconductor layer, a protective layer overlying the insulation layer, the source and the boundary of the drain to expose a portion of the drain, and a pixel electrode disposed on the substrate, overlying the protective layer overlying the boundary of the drain, electrically connected to the exposed drain.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: January 26, 2010
    Assignee: AU Optronics Corp.
    Inventors: Kuo-Lung Fang, Chih-Chun Yang, Han-Tu Lin
  • Patent number: 7628896
    Abstract: A transparent conductive oxide (TCO) based film is formed on a substrate. The film may be formed by sputter-depositing, so as to include both a primary dopant (e.g., Al) and a co-dopant (e.g., Ag). The benefit of using the co-dopant in depositing the TCO inclusive film may be two-fold: (a) it may prevent or reduce self-compensation of the primary dopant by a more proper positioning of the Fermi level, and/or (b) it may promote declustering of the primary dopant, thereby freeing up space in the metal sublattice and permitting more primary dopant to create electrically active centers so as to improve conductivity of the film. Accordingly, the use of the co-dopant permits the primary dopant to be more effective in enhancing conductivity of the TCO inclusive film, without significantly sacrificing visible transmission characteristics. An example TCO in certain embodiments is ZnAlOx:Ag.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: December 8, 2009
    Assignee: Guardian Industries Corp.
    Inventors: Alexey Krasnov, Yiwei Lu
  • Patent number: 7626202
    Abstract: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion (182) of a connecting wiring (183) on an active matrix substrate is electrically connected to an FPC (191) by an anisotropic conductive film (195). The connecting wiring (183) is manufactured in the same process with a source/drain wiring of a TFT on the active matrix substrate, and is made of a lamination film of a metallic film and a transparent conductive film. In the connecting portion with the anisotropic conductive film (195), a side surface of the connecting wiring (183) is covered with a protecting film (173) made of an insulating material.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: December 1, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20090280633
    Abstract: A method for simultaneous formation of a self-aligned contact of a core region and a local interconnect of a peripheral region of an integrated circuit includes etching a cap dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the cap dielectric layer, etching a dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the dielectric layer of the dielectric layer, etching a liner layer simultaneously on a shoulder of sidewall spacers associated with the hole and with the trench of the dielectric layer without etching the liner layer at a bottom area of the hole and the trench, performing an oxygen flushing to remove polymer residues, and etching simultaneously through the liner layer that lines the bottom area of the hole and the trench.
    Type: Application
    Filed: July 20, 2009
    Publication date: November 12, 2009
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: An Chyi Wei
  • Publication number: 20090269870
    Abstract: It is an object of the present invention to provide a semiconductor device, in particular, a light emitting element which can be easily manufactured with a wet method. One feature of the invention is a light emitting device including a transistor and a light emitting element. In the light emitting element, an organic layer, a light emitting layer, and a second electrode are sequentially formed over a first electrode, and the transistor is electrically connected to the light emitting element through a wiring. Here, the wiring contains aluminum, carbon, and titanium. The organic layer is formed by a wet method. The first electrode which is in contact with the organic layer is formed from indium tin oxide containing titanium oxide.
    Type: Application
    Filed: June 18, 2009
    Publication date: October 29, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO
  • Publication number: 20090269869
    Abstract: Provided are a multiple reflection layer electrode, a compound semiconductor light emitting device having the same and methods of fabricating the same. The multiple reflection layer electrode may include a reflection layer on a p-type semiconductor layer, an APL (agglomeration protecting layer) on the reflection layer so as to prevent or retard agglomeration of the reflection layer, and a diffusion barrier between the reflection layer and the APL so as to retard diffusion of the APL.
    Type: Application
    Filed: July 1, 2009
    Publication date: October 29, 2009
    Inventors: June-o SONG, Tae-yeon SEONG, Kyoung-kook KIM, Hyun-gi HONG, Kwang-ki CHOI, Hyun-soo KIM
  • Publication number: 20090239371
    Abstract: A semiconductor wafer (10) is structured such that fine structures (3), such as membranes, bridges or tongues, with a thickness d<<D are formed, wherein D designates the thickness of the semiconductor wafer (10). Then particles of a desired material are applied. A temporal or spatial temperature gradient is generated in the semiconductor wafer (10), e.g. by progressive heating. In such a heating process the fine structures heat up more quickly and become hotter than the remaining wafer because they have a smaller heat capacity per area and cannot carry off heat as quickly. In this manner, the fine structures can be heated to a temperature that allows a sintering of the particles. For coating the semiconductor wafer (10) is brought into a reactor (11). A precursor compound of a metal is provided and fed to the reactor (11), where a reaction takes place during which the metal is transformed to a final compound and is deposited in the form of particles on the semiconductor wafer (10).
    Type: Application
    Filed: November 23, 2005
    Publication date: September 24, 2009
    Inventors: Felix Mayer, Christoph Kleinlogel
  • Patent number: 7575963
    Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300ยฐ C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: August 18, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyang-Shik Kong, Myung-Koo Hur, Chi-Woo Kim
  • Publication number: 20090170304
    Abstract: A method of manufacturing a semiconductor device is provided, which can reduce the contact resistance of an ohmic electrode to a p-type nitride semiconductor layer and can achieve long-term stable operation. In forming, in an electrode forming step, a p-type ohmic electrode of a metal film by successive lamination of a Pd film which is a first p-type ohmic electrode and a Ta film which is a second p-type ohmic electrode on a p-type GaN contact layer, the metal film is formed to include an oxygen atom. In the presence of an oxygen atom in the metal film, then in a heat-treatment step, the p-type ohmic electrode of the metal film is heat-treated in an atmosphere that contains no oxygen atom-containing gas.
    Type: Application
    Filed: December 18, 2008
    Publication date: July 2, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoichiro Tarui, Kenichi Ohtsuka, Yosuke Suzuki, Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yasunori Tokuda, Tatsuo Omori
  • Publication number: 20090108449
    Abstract: A microelectronic device includes a non-polymeric substrate, an organic interlayer, and a indium tin oxide layer formed on the organic interlayer.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: Chinmay Betrabet, Curt Lee Nelson
  • Patent number: 7517783
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: April 14, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20090091033
    Abstract: A process of fabricating a metal oxide film includes depositing a multiphase, metal-based precursor film comprising the metal and an oxide of the metal on a substrate. The process further includes thermally growing a metal oxide film from the precursor film in a humid atmosphere for a predetermined period of time and at a predetermined temperature.
    Type: Application
    Filed: May 16, 2006
    Publication date: April 9, 2009
    Inventors: Wei Gao, Zheng-wei Li
  • Patent number: 7476607
    Abstract: An object of the present invention is to provide a photovoltaic cell that demonstrates a superior photoelectric conversion function. The present invention relates to a photovoltaic cell comprising a semiconductor electrode, an electrolyte and a counter electrode, wherein (1) the semiconductor electrode contains an oxide semiconductor layer having photocatalytic activity, (2) the oxide semiconductor layer contains secondary particles in which primary particles comprising a metal oxide are aggregated, (3) the average particle diameter of the primary particles is from 1 nm to 50 nm, and the average particle diameter of the secondary particles is from 100 nm to 10 ?m, and (4) the photovoltaic cell generates electromotive force by radiating light of a wavelength substantially equal to the average particle diameter of the secondary particles onto the semiconductor electrode.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: January 13, 2009
    Assignee: Panasonic Corporation
    Inventors: Yuka Yamada, Nobuyasu Suzuki, Yasunori Morinaga, Hidehiro Sasaki
  • Publication number: 20090008667
    Abstract: Oxidation treatment is performed to the surface of a substrate provided with a photocatalytic conductive film and an insulating film; treatment with a silane coupling agent is performed, so that a silane coupling agent film is formed and the surface of the substrate is modified to be liquid-repellent; and the surface of the substrate is irradiated with light of a wavelength (less than to equal to 390 nm) which has energy of greater than or equal to a band gap of a material for forming the photocatalytic conductive film, so that only the silane coupling agent film over the surface of the photocatalytic conductive film is decomposed and the surface of the photocatalytic conductive film can be modified to be lyophilic.
    Type: Application
    Filed: June 9, 2008
    Publication date: January 8, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Gen FUJII, Erika TAKAHASHI
  • Patent number: 7470607
    Abstract: This invention relates to novel, transparent oxide semiconductor thin film transistors (TFT's) and a process for making them.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: December 30, 2008
    Assignee: E.I. Du Pont De Nemours & Company
    Inventors: Peter Francis Carcia, Robert S. McLean
  • Patent number: 7432203
    Abstract: Semiconductor devices and methods of fabricating the same are disclosed. An illustrated semiconductor device fabricating method includes forming a titanium and titanium-nitride (Ti/TiN) metal layer on a lower oxide layer; forming an aluminum metal layer on the Ti/TiN metal layer; forming an indium tin oxide (ITO) layer on the aluminum metal layer; and patterning the ITO layer, the aluminum metal layer, and the Ti/TiN metal layer by photolithography to form a metal layer pattern and to expose a surface of the lower oxide layer, thereby facilitating a process of filling inter-wiring spaces occurring between adjacent lines of a metal layer pattern by producing a metal layer pattern having a reduced aspect ratio.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: October 7, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Suk Lee
  • Publication number: 20080233683
    Abstract: A process for producing a pre-plated leadframe that has enhanced adhesion by molding compound is provided, wherein a base leadframe material is first plated with multiple layers of metallic material. Thereafter, the plated base leadframe material is covered with a mask, so as to expose selected surfaces thereof at unmasked areas where enhanced adhesion of molding compound is desired. The said unmasked areas are plated with a layer of copper before removing the mask. Optionally, the layer of copper may further be oxidized to form a layer of specially controlled copper oxide.
    Type: Application
    Filed: March 23, 2007
    Publication date: September 25, 2008
    Inventors: Yiu Fai Kwan, Tat Chi Chan, Chun Ho Yau, Chi Chung Lee
  • Patent number: 7410893
    Abstract: A method for depositing a seed layer for a controllable electric pathway on a substrate includes selectively dispensing a seed material from an inkjet material dispenser onto said substrate.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: August 12, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Niranjan Thirukkovalur, Thomas J. Lindner
  • Patent number: 7405143
    Abstract: The present invention produces a seed layer for the deposition of copper for metallizing integrated circuits. A diffusion barrier is deposited upon the wafer. In one embodiment of the invention, a metal oxide layer is then formed on the diffusion barrier. The oxidized metal is then reduced to a conductive lower oxidation state or to its elemental form. That metal is then used as the seed layer for the growth of copper. In another embodiment, the surface of the barrier layer is repeatedly oxidized and reduced in order to reduce incubation time for the growth of a seed layer. A ruthenium seed layer is then deposited over the treated barrier layer.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: July 29, 2008
    Assignee: ASM International N.V.
    Inventors: Miika Leinikka, Juhana J. T. Kostamo