Abstract: An improved semiconductor device that reduces reverse bias junction leakage in a photodiode by using a junction isolation region to isolate the photodiode from a trench isolation region. The improved semiconductor device improves image quality for different applications such as stand-alone digital cameras and digital cameras embedded in other imaging devices such as cellular phones and personal digital assistants.

Abstract: Ultra thin back-illuminated photodiode array structures and fabrication methods. The photodiode arrays are back illuminated photodiode arrays having a substrate of a first conductivity type having first and second surfaces, the second surface having a layer of the first conductivity type having a greater conductivity than the substrate. The arrays also have a matrix of regions of a first conductivity type of a higher conductivity than the substrate extending from the first surface of the substrate to the layer of the first conductivity type having a greater conductivity than the substrate, a plurality of regions of the second conductivity type interspersed within the matrix of regions of the first conductivity type and not extending to the layer of the first conductivity type on the second surface of the substrate, and a plurality of contacts on the first surface for making electrical contact to the matrix of regions of the first conductivity type and the plurality of regions of the second conductivity type.

Abstract: A single junction interdigitated photodiode utilizes a stack of alternating highly doped first regions of a first conductivity type and highly doped second regions of a second conductivity type, which are formed below and contact the first regions, to collect photons. In addition, a highly doped sinker of a first conductivity type contacts each first region, and a highly doped sinker of a second conductivity type contacts each second region.

Abstract: A charge coupled device of the present invention includes a charge transfer region layer and a gate insulation film that are formed in the stated order on a semiconductor substrate, first gate electrodes formed at predetermined spaces on the gate insulation film, and second gate electrodes arranged between the first gate electrodes with at least silicon oxide films being interposed there between. Each silicon oxide film has constricted portions where the silicon oxide film is in contact with the gate insulation film, and electric insulation films are formed on the constricted portions so as to form sidewalls. This configuration decreases the charge transfer efficiency and increases a dielectric breakdown voltage between gate electrodes. Thus, a charge coupled device having high performance and high dielectric strength is provided.

Abstract: A method of forming a multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a photogate or photodiode structure. The multi-trench photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The multi-trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the multi-trench photosensor.

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transi

Abstract: A second substrate including a transparent substrate is bonded to a first substrate including a plurality of optical elements each of which has an optical section, with a light transmissive adhesive layer interposed, to seal the optical sections. The first substrate is then cut into the individual optical elements.

Abstract: A solid-state imaging device according to the present invention includes a semiconductor substrate; a photoelectric conversion portion formed on the semiconductor substrate; a gate insulating film formed on the semiconductor substrate and covering the photoelectric conversion portion; a vertical transfer portion for transferring a charge generated at the photoelectric conversion portion in a vertical direction; and a multilayer transfer gate electrode for transferring the charge of the vertical transfer portion. At least one layer of the multilayer transfer gate electrode is made of at least two impurity doped amorphous silicon films of different impurity concentration.

Abstract: A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.

Abstract: The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirements for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.

Abstract: An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.

Abstract: A method of testing/stressing a charge trapping device, such as a negative differential resistance (NDR) FET is disclosed. By operating/stressing a charge trap device during/after manufacture, a distribution of charge traps can be altered advantageously to improve performance.

Abstract: CMOS optical receiver and optical transmitters are described. The optical receiver is formed from a CMOS CCD which is modified to immediately output all information indicative of incoming light, i.e., with no transfer gate. The optical transmitter is formed of a modulation window device. Both the optical transmitter and optical receiver are located on-chip with a microprocessor and form the I/O for the microprocessor. Since the modified I/O is serial, a serial to parallel converter, and parallel to serial converter are provided.

Abstract: A driving method for a solid state image pickup device, having four or more transfer stages as one transfer unit, includes reading signal charge from the charge accumulation regions to the vertical charge transfer channels. The reading step includes (b-1) applying the barrier forming voltage to a first transfer electrode to form a barrier of at least one stage per the transfer unit; (b-2) applying the read pulse to a second transfer electrode to read signal charge from a corresponding charge accumulation region to a corresponding vertical charge transfer channel; and (b-3) applying a cancellation pulse to a third transfer electrode spaced by at least one transfer stage from the first transfer electrode, the cancellation pulse cancelling out a potential change in the charge accumulation region to be caused by the read pulse.

Abstract: A method of forming a microlens structure is provided along with a CCD array structure employing a microlens array.

Abstract: A pixel of a semiconductor-based image detector includes a photodetector, at least one switching device serially connected to the photodetector and a bypass device interposed between the photodetector and a power supply voltage. Accordingly, even though excess charges may be generated in the photodetector, the excess charges flow into the power supply through the bypass device. Blooming can thereby be reduced or suppressed.

Abstract: A pixel cell having two capacitors connected in series where each capacitor has a capacitance approximating that of the periphery capacitors and such that the effective capacitance of the series capacitors is smaller than that of each of the periphery capacitors. The series-connected capacitors are coupled to the floating diffusion (FD) region for receiving “surplus” charge from the FD region during saturation conditions.

Abstract: A semiconductor package with a photosensitive chip and a fabrication method thereof are provided. A substrate having a core is prepared. A solder mask layer is applied over a surface of the core and formed with an opening to expose a continuous peripheral portion on the surface of the core. At least one photosensitive chip is mounted on and electrically connected to the substrate. An encapsulation dam is formed on the continuous peripheral portion of the core and surrounds the chip. The dam includes a shoulder portion adjacent to and flush with the solder mask layer, and a protruded support portion surrounding the shoulder portion. A lid is attached to the support portion of the dam for sealing the dam such that the chip is received in a space defined by the substrate, the dam and the lid.

Abstract: Method of fabricating an optical semiconductor package and optical semiconductor package containing an integrated circuit chip having on a front face an optical sensor and electrical connection regions distributed around this sensor, in which a transparent patch (6) lies in front of the front face of the chip without covering the electrical connection regions of this chip, plates (2, 7) defining between them a cavity (10) in which the said chip and the said patch are stacked and which have annular assembly faces (2a, 7a), electrical connection pads (15) are placed between the said electrical connection regions and one face (12) of the said cavity, electrical connection tracks (14) are carried by a plate (7) and lie on the said face (12) of the cavity in order to be in contact with the said pads, an adhesive layer (18) flying between the said assembly faces (2a, 7a), the said tracks (14) protruding in order to pass between the assembly faces of the said plates with a view to external connections and the plate

Abstract: Spaces in a nanostructure can be filled with an organic material while in the solid state below Tm (without heating) by exposing the organic material to solvent vapor while on or mixed with the nanostructured material. The exposure to solvent vapor results in intimate contact between the organic material and the nanostructured material without having to expose them to possibly detrimental heat to melt in the organic material. Solution processing methods need only to be employed to create bulk films while organic material infiltration can take place in the solid state after depositing the film.

Abstract: An active pixel image sensor is formed on a P-type epitaxial layer on a P-type substrate. An active pixel array is in the P-type epitaxial layer. Each pixel includes an N-well functioning as a collection node, and a P-well adjacent the N-well. The P-well includes only NMOS transistors functioning as active elements. The in-pixel transistors cooperate with off-pixel PMOS transistors to form A-D converters.

Abstract: A solid-state imaging device includes a plurality of vertical charge transferring portions, and a horizontal charge transferring portion connected to at least one end of each of the vertical charge transferring portions.

Abstract: The interface between a first substrate and light-emitting diodes formed on the first substrate is selectively irradiated with an energy beam and transmits the energy beam through the first substrate, thereby selectively releasing the light-emitting diodes. The light-emitting diodes are then transferred onto a device holding layer included on a device holding substrate. Subsequently, the light-emitting diodes are transferred onto a second substrate. The irradiation of the interface with the energy beam enables the devices to be easily released from the first substrate.

Abstract: Disclosed is a method for fabricating a solid-state imaging device including a semiconductor substrate of a first conductivity type, a plurality of light-receiving sections provided at a distance in the surface region of the semiconductor substrate, and channel stop regions of a second conductivity type provided between the adjacent light-receiving sections in the surface region and in the internal region of the semiconductor substrate. The method includes the steps of forming a first photoresist layer having openings corresponding to positions at which the channel stop regions are formed; ion-implanting an impurity of a second conductivity type into the semiconductor substrate at a first energy through the first photoresist layer as a mask; forming a second photoresist layer having openings; and ion-implanting an impurity of a second conductivity type into the semiconductor substrate at a second energy through the second photoresist layer as a mask.

Abstract: There is provided an apparatus for forming a plurality of silicon-based thin films on a substrate using a plurality of deposited film forming vessels that can form silicon-based thin films of higher quality and excellent uniformity by applying a high frequency power of a first frequency selected from the range between 30 MHz and 500 MHz to a power-applying electrode in a deposited film forming vessel wherein the distance between the power-supplying electrode and the substrate is 10 mm±5 mm, and by supplying a high frequency power of a second frequency selected from the range between 10 MHz and 30 MHz to a power-supplying electrode in a deposited film forming vessel wherein the distance between the power-supplying electrode and the substrate is 20 mm±5 mm.

Abstract: The luminous efficiency of a nitride semiconductor device comprising a gallium nitride-based semiconductor layer formed on a dissimilar substrate is improved. An n-type layer formed on the substrate with a buffer layer interposed between them comprises a portion of recess-and-projection shape in section as viewed in the longitudinal direction. Active layers are formed on at least two side faces of the projection with the recess located between them. A p-type layer is formed within the recess. An insulating layer is formed on the top face of the projection, and on the bottom face of the recess. The n-type layer is provided with an n-electrode while the p-type layer is provided with a p-electrode contact layer. As viewed from the p-type layer formed within the recess in the gallium nitride-based semiconductor layer, the active layer and the n-type layer are located in an opposite relation to each other.

Abstract: An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

Abstract: A retrograde well structure for a CMOS imager that improves the quantum efficiency and signal-to-noise ratio of the imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. Also disclosed are methods for forming the retrograde well.

Abstract: An image sensor includes a plurality of unit pixels for sensing a light beam to generate an image data. Each of the unit pixels includes, a photoelectric element for sensing a light beam incident thereto and generating photoelectric charges, a transistor including a gate dielectric formed adjacent to the photoelectric element and a gate electrode formed on top of the gate dielectric and a capacitor structure including an insulating film formed on a portion of the photoelectric element and a bottom electrode, wherein the insulating film and the gate dielectric are made of a same material and the bottom electrode and the gate electrode are made of a same material.

Abstract: A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel, a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.

Abstract: A frame transfer-type solid imaging device is provided, which can be operated without reducing the transfer efficiency or the transfer charge quantity. A plurality of N-type regions 5 constituting photoelectric conversion regions and a plurality of P+-type regions 6 constituting channel stop regions are formed on a P-type silicon substrate 4, and a transparent electrode 1 is further formed through an insulating film 7 on the substrate 4. The thickness of the transparent electrode at a portion above the photoelectric conversion region is made thinner than the thickness of the other part of the transparent electrode 1, and an antireflection film 8 is formed above the photoelectric conversion region 2.

Abstract: The invention relates to very small-sized color image sensors.

Abstract: A semiconductor device such as a buried heterostructure semiconductor laser includes a semiconductor substrate supporting an active region comprised of a multiple quantum well active region and confinement layers having defined gratings and grating overgrowth regions to produce a laser device. The device also includes a current confinement layer including a sequence of doped n-p-n-p semiconductor layers to produce a n-p-n-p blocking structure and a semi-insulating semiconductor material deposited over the n-p-n-p blocking structure.

Abstract: An active pixel cell includes electronic shuttering capability. The cell can be “shuttered” to prevent additional charge accumulation. One mode transfers the current charge to a storage node that is blocked against accumulation of optical radiation. The charge is sampled from a floating node. Since the charge is stored, the node can be sampled at the beginning and the end of every cycle. Another aspect allows charge to spill out of the well whenever the charge amount gets higher than some amount, thereby providing anti blooming.

Abstract: In a distributed feedback type semiconductor layer diode including a semiconductor substrate, an optical guide layer formed on the semiconductor substrate, a diffraction grating having a phase shift region being formed between the semiconductor substrate and the optical guide layer, and an active layer formed on the optical guide layer, &kgr;L+A·&Dgr;&lgr;≧B where &kgr; is a coupling coefficient of the diffraction grating, L is a cavity length of the diode, &Dgr;&lgr; is a detuning amount denoted by &Dgr;&lgr;=&lgr;g−&lgr; where &lgr;g is a gain peak wavelength of the diode and &lgr; is an oscillation wavelength of the diode, A is a constant from 0.04 nm−1 to 0.06 nm−1, and B is a constant from 3.0 to 5.0.

Abstract: A multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a photogate or photodiode structure. The multi-trench photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The multi-trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the multi-trench photosensor.

Abstract: A transmittance overcoat with effectively planar top surface and specified optical and materials properties is applied above a microlens layer to extend the focal length and enhance the performance of long focal length microlenses for semiconductor array color imaging devices. The geometrical optics design factors and microelectronic fabrication sequence to achieve optimized long focal length microlens performance are disclosed. The principal advantages of the adaptive process taught in the present invention is shown to enable real-time compensation adjustments for process and material variations. The overcoat process enables simplified single-layer integrated microlens optics for lowcost, high volume manufacturing of CMOS and CCD color video cameras.

Abstract: A method of testing/stressing a charge trapping device, such as a negative differential resistance (NDR) FET is disclosed. By operating/stressing a charge trap device during/after manufacture, a distribution of charge traps can be altered advantageously to improve performance.

Abstract: There is provided a laminated type photoelectric converter whose sensitivity is enhanced uniformly. In the photoelectric converter in which a photoelectric conversion device is laminated above a signal transfer device, the sensitivity is enhanced by providing bends on a lower electrode of the photoelectric conversion device and by confining light uniformly.

Abstract: A method of producing nitride based heterostructure devices by using a quaternary layer comprised of AlInGaN. The quaternary layer may be used in conjunction with a ternary layer in varying thicknesses and compositions that independently adjust polarization charges and band offsets for device structure optimization by using strain compensation profiles. The profiles can be adjusted by altering profiles of molar fractions of In and Al.

Abstract: A color linear image sensor device has a shutter function for selectively draining charges stored in a photodetector circuit. The color linear image sensor device includes first, second, and third linear image sensors having different sensitivities with respect to incident light and arranged successively in sensitivity decreasing order from the outermost, and a shutter gate and a shutter drain for adjusting an amount of exposure to the linear image sensor which has the highest sensitivity to incident light.

Abstract: A process for producing a solid-state imaging device which includes the steps of forming a light-receiving portion of a pixel in a surface region on the substrate, forming above the light receiving portion an inter-layer dielectric having a depression in its surface, forming on the inter-layer dielectric a light transmitting film having in its surface a concave conforming to the depression, forming at the position that covers the concave on the light transmitting film a mask layer with a convexly curved surface, and etching the mask layer and the light transmitting film all together, thereby making the light transmitting film into a shape of convex lens with an upwardly curved surface.

Abstract: In a solid state image sensor, tranfer electrodes are formed by selectively etch-removing a single layer of conducting electrode material at a plurality of first regions which divide the single layer of conducting electrode material in a row direction for each one pixel. A patterned mask is formed to cover the first regions and the single layer of conducting electrode material but to expose the single layer of conducting electrode material at a second region above each of the photoelectric conversion sections, and the single layer of conducting electrode material is selectively etch-removed using the patterned mask as a mask. Thereafter, a first conductivity type impurity and a second conductivity type impurity are ion-implanted using the patterned mask and the single layer of conducting electrode material as a mask, to form the photoelectric conversion section at the second region.

Abstract: A solid-state image pickup device includes: a plurality of light receiving portions arranged in a matrix, and a vertical transfer register which is four-phase driven by first, second, third and fourth transfer electrodes of a three-layer structure. The vertical transfer register is provided for each of columns of said light receiving portions. The first and third transfer electrodes of the first layer are alternately arranged in a charge transfer direction, and the adjacent two of the first and third transfer electrodes extend in parallel to each other between the light receiving portions. With this solid-state image pickup device, the accumulated charge capacity of each transfer region composed of the adjacent transfer electrodes for two-phases is equalized and the area of the light receiving portion is increased irrespective of variations in processed dimension between the transfer electrodes.

Abstract: A pixel cell having two capacitors connected in series where each capacitor has a capacitance approximating that at of the periphery capacitors and such that the effective capacitance of the series capacitors is smaller than that of each of the periphery capacitors. The series-connected capacitors are coupled to the floating diffusion (FD) region for receiving “surplus” charge from the FD region during saturation conditions.

Abstract: Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.

Abstract: A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.

Abstract: A multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a photogate or photodiode structure. The multi-trench photosensor provides the photosensitive element With an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The multi-trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the multi-trench photosensor.

Abstract: A pinned photodiode is operated without a transfer gate. This is done by forming a pinned photodiode which has a selective connection to the substrate. When the connection is turned on, the photodiode is pinned to the substrate, and kept at a specified potential. When the connection is off, the photodiode is disconnected from the substrate and hence floats. In this way, the area above the photoreceptor can be used both for a reception area and for a charge transfer area.

Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.