Abstract: An inertial sensor includes a substrate, a sensor element provided on the substrate, a lid that covers the sensor element and is bonded to the substrate, and a plurality of terminals positioned outside the lid and electrically coupled to the sensor element, in which the plurality of terminals include an input terminal to which an electrical signal is input and a detection terminal for detecting a signal from the sensor element, and L1>L2, where L1 is a distance between the input terminal and the lid, and L2 is a distance between the detection terminal and the lid.

Abstract: A transistor amplifier package includes a base, one or more transistor dies on the base, first and second leads coupled to the one or more transistor dies and defining respective radio frequency (RF) signal paths, and an isolation structure on the base between the respective RF signal paths. The isolation structure includes first and second wire bonds. The first and second wire bonds may have a crossed configuration defining at least one cross point therebetween. Related wire bond-based isolation structures are also discussed.

Abstract: A height of a vertical wire interconnection bonded onto a substrate is measured by first capturing a top view of the vertical wire interconnection and identifying a position of a tip end of the vertical wire interconnection from the top view. A conductive probe is located over the tip end of the vertical wire interconnection, and is lowered towards the vertical wire interconnection until an electrical connection is made between the conductive probe and the tip end of the vertical wire interconnection. A contact height at which the electrical connection is made may thus be determined, wherein the contact height corresponds to the height of the vertical wire interconnection.

Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.

Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

Abstract: A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern. The semiconductor device also includes a first passivation layer over the conductive pattern; a second passivation layer over the first passivation layer; an interconnect structure disposed over the conductive pattern and in the first passivation layer and the second passivation layer; and an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern.

Abstract: Disclosed is a method for manufacturing an organic thin film pattern, an organic thin film pattern, an array substrate, and a display device. The method for manufacturing the organic thin film pattern includes the steps of forming a liquid droplet in a recessed portion of a thin film definition layer on a substrate, the liquid droplet being a solution containing an organic functional material, gelatinizing the liquid droplet, and performing a drying process on gelatinized liquid droplet to form an organic thin film pattern.

Abstract: The present disclosure is directed to a semiconductor die with multiple contact pads electrically coupled to a single lead via a single wire, and methods for fabricating the same. In one or more embodiments, multiple contact pads are electrically coupled to each other by a plurality of conductive layers stacked on top of each other. The uppermost conductive layer is then electrically coupled to a single lead via a single wire.

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

Abstract: A printed circuit board (PCB) is provided as follows. A first connection pad and a second connection pad are disposed on a first surface and a second surface of the base substrate layer, respectively. The first connection pad and the second connection pad each includes a first metal. A first pad cover layer covers a top surface of the first connection pad and includes an insulating metal oxide having a second metal different from the first metal.

Abstract: A light emitting device includes a resin package including: a first lead and a second lead, each including a top surface and a bottom surface, and a first resin portion located between the first lead and the second lead and extending in a first direction; a first light emitting element and a second light emitting element arrayed on the top surface of the first lead in the first direction, the first light emitting element and the second light emitting element each including at least a first side surface; and an encapsulant located on the top surface of the first lead and covering the first light emitting element and the second light emitting element. The first side surface of the first light emitting element and the first side surface of the second light emitting element partially face each other.

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.

Abstract: An array substrate includes a device array, a bonding pad, and at least one support structure. The bonding pad is located in a bonding area and is electrically connected to the device array. A horizontal distance between the at least one support structure and the bonding pad is between 5 ?m and 1000 ?m.

Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Abstract: A method of electroless gold plating includes a step of forming an underlying alloy layer on a base material and a step of forming a gold plate layer directly on the underlying alloy layer by electroless reduction plating using a cyanide-free gold plating bath. The underlying alloy layer is formed of an M1-M2-M3 alloy, where M1 is at least one element selected from Ni, Fe, Co, Cu, Zn, where Sn, M2 is at least one element selected from Pd, Re, Pt, Rh, Ag and where Ru, and M3 is at least one element selected from P and B.

Abstract: Disclosed is a low-profile microdisplay module that comprises a package substrate, a microdisplay chip disposed over a first surface of the package substrate, and a plurality of conductive vias. The plurality of conductive vias are electrically coupled to the microdisplay chip and disposed through the package substrate to a second surface of the package substrate, the second surface being opposite and parallel to the first surface. The microdisplay module further comprises a flexible flat circuit connector coupled to the plurality of conductive vias at the second surface of the package substrate.

Abstract: A production line for producing electronic modules including a printed-circuit board, at least one first-type component, and at least one second-type component, wherein the production line includes a unit for putting the first-type component in place, a general heating unit for melting a solder placed between the at least one first-type component and the circuit, a unit for putting the second-type component in place, and a local heating unit for melting a solder placed between the at least one second-type component and the circuit.

Abstract: A method for forming a stacked metal contact in electrical communication with aluminum wiring in a semiconductor wafer of an integrated circuit is disclosed. The method includes the steps of: forming at least one passivation layer on a surface of the semiconductor wafer of the integrated circuit, where an aluminum wiring is embedded; forming a patterned terminal via opening through the passivation layer to expose the aluminum wiring; removing a portion of the aluminum wiring from the patterned terminal via opening by chemical etching and forming a thin zinc film on an etched surface at the same time; forming a nickel film stacked on the zinc film; and; and forming a metal stack in the patterned terminal via opening and/or at least a portion of the passivation layer by chemical plating or metal plating.

Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire.

Abstract: Disclosed is a device for bonding a flexible PCB (Printed Circuit Board) to a camera module, the device according to an exemplary embodiment of the present disclosure comprising a thermo-compression unit configured to bond the camera module to the flexible PCB using an conductive film by applying heat and pressure to the conductive film between the camera module and the flexible PCB, an ultrasonic wave bonding unit configured to directly transmit ultrasonic wave vibration energy to the camera module to remove an oxide film on connection particles intrinsically formed inside the conducive film, and a controller configured to activate the ultrasonic wave bonding unit when a temperature of the conductive film rises to a predetermined temperature.

Abstract: Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit. The integrated circuit as well as components associated with the integrated circuit may be positioned below a surface plane of a printed circuit board in which the integrated circuit is located. The integrated circuit may include bond wires configured to electrically connect the integrated circuits to other components. The low profile assembly may include forming various layers over a substrate and later removing some of the layers.

Abstract: A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

Abstract: A method of making a package substrate having a copper bond pad and a location for receiving a semiconductor die having a remnant of one of a group consisting of HEDP and an HEDP derivative on a top surface of the copper bond pad. The semiconductor die is attached to the substrate. A wirebond connection is attached between the remnant and the semiconductor die.

Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process coats the component surfaces to facilitate the bonding of the bond pads. In another aspect, the present process coats the bond pads with shelled capsules to facilitate the bonding of the bond pads.

Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.

Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.

Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.

Abstract: Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.

Abstract: A method of fabricating a microelectronic package can include mounting a microelectronic element to a substrate with a joining material. The mounting can include bonding a front surface of the microelectronic element to a first surface of the substrate with a joining material, and joining contacts arranged within a contact-bearing region of the front surface of the microelectronic element with corresponding substrate contacts at the substrate first surface, the joining creating electrical contact between the microelectronic element and the substrate. The method can also include forming an underfill between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element, the underfill reinforcing the joints between the contacts and the substrate contacts, the joining material having a Young's modulus less than 75% of a Young's modulus of the underfill.

Abstract: A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire.

Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink.

Abstract: Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Abstract: A method and structure for encoding information on an integrated circuit chip. The method includes selecting a set of chip pads of the integrated circuit chip for encoding the information; encoding the information during a wirebonding process, the wirebonding process comprising forming ball bonds on chip pads of the integrated circuit chip and wedge bonds on leadframe fingers adjacent to one or more edges of the integrated circuit chip, the ball bonds and the wedge bonds connected by respective and integral wires; and wherein the information is encoded by varying one or more wirebonding parameters on each chip pad of the set of chip pads, the wirebonding parameters selected from the group consisting of the location of a ball bond, the diameter of a ball bond, both the location and diameter of a ball bond, the location of a wedge bond and combinations thereof.

Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.

Abstract: A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and second areas having a second thickness. The second thickness is greater than the first thickness. The first areas having the first thickness extend over a majority of the chip. The second areas having the second thickness are adjacent the wire bond pads.

Abstract: A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.

Abstract: A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices. The method also includes forming a first conductive layer on the semiconductor substrate, and forming a second conductive layer with smaller grain sizes by doping the first conductive layer. Further, the method includes forming an interconnection pad by patterning the second conductive layer, and forming a connection wire on the interconnection pad.

Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.

Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a coverlay layer on the substrate and the electrically conductive pattern, forming a partially cured, tacky adhesive layer on the coverlay layer, and forming openings in the coverlay layer and the partially cured, tacky adhesive layer aligned with the electrically conductive pattern. The method includes positioning an IC on the partially cured, tacky adhesive layer and thereafter curing the partially cured tacky adhesive layer to thereby simultaneously mechanically secure and electrically interconnect the IC to the substrate, the IC having bond pads on a surface thereof.

Abstract: A semiconductor device includes a semiconductor chip, a die pad including an obverse surface on which the semiconductor chip is bonded, a lead spaced apart from the die pad, a bonding wire electrically connecting the semiconductor chip and the lead to each other, and a resin package that seals the semiconductor chip and the bonding wire. The bonding wire includes a first bond portion press-bonded to the semiconductor chip by ball bonding, a second bond portion press bonded to the lead by stitch bonding, a landing portion extending from the second bond portion toward the die pad and formed in contact with an obverse surface of the lead, and a loop extending obliquely upward from the landing portion toward the semiconductor chip.

Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.

Abstract: A light-emitting device package includes: a package body on which a mount portion and a terminal portion are disposed; a light-emitting device chip that is mounted on the mount portion; and a bonding wire that electrically connects an electrode of the light-emitting device chip and the terminal portion. The bonding wire includes a rising portion that rises from the light-emitting device chip to a loop peak, and an extended portion that connects the loop peak and the terminal portion. A first kink portion, which is bent in a direction intersecting a direction in which the rising portion rises, is disposed on the rising portion.

Abstract: Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects.

Abstract: One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Abstract: A method and structure for encoding information on an integrated circuit chip. The method includes selecting a set of chip pads of the integrated circuit chip for encoding the information; encoding the information during a wirebonding process, the wirebonding process comprising forming ball bonds on chip pads of the integrated circuit chip and wedge bonds on leadframe fingers adjacent to one or more edges of the integrated circuit chip, the ball bonds and the wedge bonds connected by respective and integral wires; and wherein the information is encoded by varying one or more wirebonding parameters on each chip pad of the set of chip pads, the wirebonding parameters selected from the group consisting of the location of a ball bond, the diameter of a ball bond, both the location and diameter of a ball bond, the location of a wedge bond and combinations thereof.

Abstract: A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.

Abstract: After forming a pressure-bonded ball and a ball neck by bonding an initial ball to a pad, a capillary is moved upward, away from a lead, and then downward, thereby the ball neck is trodden on by a face portion that is on the lead side of the capillary. Subsequently, the capillary is moved upward and then toward the lead until the face portion of the capillary is positioned above the ball neck, thereby a wire is folded back toward the lead. Then, the capillary is moved downward such that a side of the wire is pressed by the capillary against the ball neck that has been trodden on. After the capillary is moved obliquely upward toward the lead and then looped toward the lead, the wire is pressure-bonded to the lead.