Including Fusion Of Conductor Patents (Class 438/615)
  • Patent number: 9048135
    Abstract: An integrated circuit device includes a Cu pillar and a solder layer overlying the Cu pillar. A Co-containing metallization layer is formed to cover the Cu pillar and the solder layer, and then a thermally reflow process is performed to form a solder bump and drive the Co element into the solder bump. Next, an oxidation process is performed to form a cobalt oxide layer on the sidewall surface of the Cu pillar.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: June 2, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Zheng-Yi Lim, Chung-Shi Liu
  • Patent number: 9040409
    Abstract: Embodiments of the present invention are directed to processes for making solar cells by simultaneously co-firing metal layers disposed both on a first and a second surface of a bifacial solar cell substrate. Embodiments of the invention may also provide a method forming a solar cell structure that utilize a reduced amount of a silver paste on a front surface of the solar cell substrate and a patterned aluminum metallization paste on a rear surface of the solar cell substrate to form a rear surface contact structure. Embodiments can be used to form passivated emitter and rear cells (PERC), passivated emitter rear locally diffused solar cells (PERL), passivated emitter, rear totally-diffused (PERT), “iPERC,” Crystalline Reduced-cost Aluminum Fire-Through (CRAFT), pCRAFT, nCRAFT or other high efficiency cell concepts.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 26, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prabhat Kumar, Michael P. Stewart, Kalyan Rapolu, Lin Zhang, Hari K. Ponnekanti
  • Publication number: 20150130020
    Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: CHAO-WEN SHIH, KAI-CHIANG WU, CHING-FENG YANG, MING-KAI LIU, SHIH-WEI LIANG, YEN-PING WANG
  • Publication number: 20150125998
    Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: You-Hua CHOU, Yi-Jen LAI, Chun-Jen CHEN, Perre KAO
  • Publication number: 20150123269
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 7, 2015
    Inventors: Hsien-Wei Chen, Jie Chen
  • Patent number: 9006096
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process coats the component surfaces to facilitate the bonding of the bond pads. In another aspect, the present process coats the bond pads with shelled capsules to facilitate the bonding of the bond pads.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: April 14, 2015
    Inventor: Jayna Sheets
  • Patent number: 8987130
    Abstract: An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Gregory M. Fritz, Eric P. Lewandowski
  • Patent number: 8987132
    Abstract: Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Paul A. Lauro, Jae-Woong Nah
  • Publication number: 20150061158
    Abstract: A method including forming a first solder bump on a chip, the first solder bump made of a first alloy, and forming a second solder bump on a chip, the second solder bump made of a second alloy, where the first alloy has a different alloy concentration and is different from the second alloy.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: International Business Machines Corporation
    Inventor: Sylvain Pharand
  • Patent number: 8962471
    Abstract: A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 ?m to 1.0 ?m. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: February 24, 2015
    Assignee: Tanaka Kikinzoku Kogyo K.K.
    Inventors: Toshinori Ogashiwa, Masayuki Miyairi
  • Patent number: 8962470
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Patent number: 8940550
    Abstract: Methods for preventing warpage of a laminate may include placing the laminate on a back plate and applying a magnetic force to the laminate to hold the laminate flat against the back plate. In some embodiments, the magnetic force may be applied by placing a first magnet above the laminate so that an attractive force generated between the first magnet and a ferromagnetic region of the back plate pulls the first magnet against the laminate, thereby holding the laminate flat against the back plate. In other embodiments, the magnetic force may be applied by placing a first magnet above the laminate and placing a second magnet above the first magnet so that a repulsive force generated between the first magnet and the magnet pushes the first magnet against the laminate, thereby holding the laminate flat against the back plate.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Benjamin V. Fasano, Shidong Li, Thomas Weiss
  • Patent number: 8928145
    Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Cyril Cabral, Jr., Kenneth P. Rodbell, Robert L. Wisnieff
  • Patent number: 8871551
    Abstract: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or resonator. The fabricating or manufacturing microelectromechanical systems of the present invention, and the systems manufactured thereby, employ wafer bonding encapsulation techniques.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: October 28, 2014
    Assignee: SiTime Corporation
    Inventors: Aaron Partridge, Markus Lutz, Pavan Gupta
  • Patent number: 8846521
    Abstract: A manufacturing method of an electronic component package, includes: forming electrode pads on a main surface of a first electronic component; forming first bonding wires shaped in loop so as to be electrically connected with the electrode pads and elongated upward from the electrode pads and such that both ends of the first bonding wires are on the electrode pad, respectively; forming a resin layer over the main surface of the first electronic component so as to embed the first bonding wires; removing the resin layer so as to expose ends of the first bonding wires from the resin layer and removing the end of each of the first bonding wires so that two wires are elongated from on each of the electrode pads; and forming a metallic layer on the surface of the resin layer after removing so that the first bonding wires are electrically connected with the metallic layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: September 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Sugizaki
  • Patent number: 8846519
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is more than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: September 30, 2014
    Assignee: Advanpack Solutions Pte Ltd.
    Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong
  • Patent number: 8835302
    Abstract: A method of fabricating a package substrate including preparing a substrate having at least one conductive pad, forming an insulating layer having an opening to expose the conductive pad on the substrate, forming a separation barrier layer on the conductive pad inside the opening to be higher than the upper surface of the insulating layer along the side walls thereof, forming a post terminal on the separation barrier layer, and forming a solder bump on the post terminal.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: September 16, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Gyu Lee, Dae Young Lee, Tae Joon Chung, Seon Jae Mun, Jin Won Choi
  • Patent number: 8836118
    Abstract: Electronic device packages and related methods are provided. The electronic device package includes a first substrate having a first contact portion disposed thereon, a bump having a first contact surface connected to the first contact portion and a second contact surface disposed opposite to the first contact surface, and a buffer spring pad portion between the first contact portion of the first substrate and the first contact surface of the bump. The buffer spring pad portion includes at least two different conductive material layers which are stacked.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Tae Min Kang
  • Publication number: 20140252611
    Abstract: An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 11, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Wen-Hsiung Lu, Ming-Da Cheng
  • Patent number: 8822326
    Abstract: Provided is a method for manufacturing an Sn alloy bump, wherein composition of the Sn alloy bump can be readily controlled. The method for manufacturing an Sn alloy bump formed of an alloy composed of Sn and other one or more types of metals has a step of forming an Sn layer on an electrode pad in a resist opening formed on a substrate by electrolytic plating; a step of laminating Sn and an alloy layer on the Sn layer by electrolytic plating; and a step of forming an Sn alloy bump by melting the Sn layer and the laminated alloy layer after removal of a resist.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: September 2, 2014
    Assignee: Mitsubishi Materials Corporation
    Inventors: Takeshi Hatta, Akihiro Masuda
  • Patent number: 8809119
    Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a leadframe having unprocessed leads; depositing an etch mask on a top surface of the unprocessed leads, the unprocessed leads having the etch mask and an unmasked portions of the top surface; connecting an integrated circuit die to the unprocessed leads; encapsulating with a package body the leadframe, the top surface of the unprocessed leads exposed from the package body; forming side-solderable leads including forming a groove in the unprocessed leads, the groove formed under a portion of the etch mask including forming an overhang of the etch mask over the groove; removing the etch mask; and depositing a plating on the side-solderable leads.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: August 19, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Henry Descalzo Bathan, Byung Tai Do
  • Patent number: 8802557
    Abstract: A method for forming a micro bump includes forming a first nano-particle layer on a substrate and forming a second nano-particle layer on the first nano-particle layer. The first and second nano-particle layers include a plurality of first nano particles and a plurality of second nano particles, respectively. The method further includes irradiating a laser beam onto the second nano-particle layer, where the laser beam penetrates through the second nano-particle layer and is at least partially absorbed by at least some of the first nano particles to generate heat. The first nano particles and the second nano particles have different absorption rates with respect to the laser beam.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: August 12, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Ruoh-Huey Uang, Yi-Ting Cheng
  • Publication number: 20140210076
    Abstract: A method of forming a hybridized device including forming a first component provided with metal bumps, and a second component provided with connection elements, attaching the bumps to the connection elements. The manufacturing of the second component includes forming, on a surface of a substrate, resistive elements at the locations provided for the connection elements; depositing an electric insulator layer at least on the resistive elements; and forming the connection elements, each comprising a metal well having an opening capable of receiving the corresponding metal bump of the first microelectronic component and at least partially filled with a fusible element, particularly indium or an alloy of tin and gold, or with a conductive ink, particularly based on silver or copper. Further, the attachment of the balls to the connection elements comprises applying an electric current through the resistive elements to heat the bumps.
    Type: Application
    Filed: March 26, 2014
    Publication date: July 31, 2014
    Applicant: Commissariat A L'Energie Atomique Et Aux Energies Alternatives
    Inventor: Abdelkader ALIANE
  • Patent number: 8791008
    Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 29, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen
  • Patent number: 8759972
    Abstract: A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu-OSP can be formed over the substrate.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: June 24, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Publication number: 20140167252
    Abstract: Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to promote package thickness scaling (e.g., reduce the overall package thickness). For example, the dip soldering process disclosed herein may enable ultra-thin wafer-level packages (WLP), ultra-thin wafer level quad-flat no-leads (WQFN) packages, or the like.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventor: Maxim Integrated Products, Inc.
  • Patent number: 8748306
    Abstract: A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Yang Lei, Hung-Jui Kuo, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 8735221
    Abstract: Provided are a stacked package, method of fabricating a stacked package, and method of mounting a stacked package. A method includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Wook Yoo, Sun-Kyoung Seo
  • Patent number: 8691685
    Abstract: In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions can be achieved through a reaction-preventative or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P).
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sung Kwon Kang, Da-Yuan Shih, Yoon-Chul Son
  • Publication number: 20140091457
    Abstract: An apparatus comprises a substrate including a surface and a plurality of bonding pads positioned on the surface. The apparatus also includes a material comprising a solder positioned on the bonding pads and extending a distance outward therefrom. A first of the bonding pads in a first location on the substrate surface includes the solder extending a first distance outward therefrom. A second of the bonding pads in a second location on the substrate surface includes the solder extending a second distance outward therefrom. The first distance is different than the second distance. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2012
    Publication date: April 3, 2014
    Inventors: Hongjin JIANG, Arun Kumar C. NALLANI, Wei TAN
  • Patent number: 8679964
    Abstract: In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P).
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sung Kwon Kang, Da-Yuan Shih, Yoon-Chul Son
  • Patent number: 8673762
    Abstract: A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Toshiya Akamatsu, Nobuhiro Imaizumi, Seiki Sakuyama, Keisuke Uenishi, Tetsuhiro Nakanishi
  • Publication number: 20140057392
    Abstract: A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill.
    Type: Application
    Filed: August 31, 2013
    Publication date: February 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Jae-Woong Nah, Da-Yuan Shih
  • Patent number: 8633103
    Abstract: In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer.
    Type: Grant
    Filed: June 13, 2010
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Hata, Masato Nakamura, Nobuhiro Kinoshita, Jumpei Konno, Chiko Yorita
  • Patent number: 8603911
    Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: December 10, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hui-Min Huang, Chun-Tang Lin, Chien-Wei Lee, Yen-Ping Wang
  • Publication number: 20130309862
    Abstract: Provided is a method for manufacturing an Sn alloy bump, wherein composition of the Sn alloy bump can be readily controlled. The method for manufacturing an Sn alloy bump formed of an alloy composed of Sn and other one or more types of metals has a step of forming an Sn layer on an electrode pad in a resist opening formed on a substrate by electrolytic plating; a step of laminating Sn and an alloy layer on the Sn layer by electrolytic plating; and a step of forming an Sn alloy bump by melting the Sn layer and the laminated alloy layer after removal of a resist.
    Type: Application
    Filed: January 16, 2012
    Publication date: November 21, 2013
    Inventors: Takeshi Hatta, Akihiro Masuda
  • Patent number: 8586467
    Abstract: In flip chip attach of electronic components, underfill is filled between the component and the substrate to alleviate, for example, thermal stress. In electronic component mounting using copper pillars conducted so far, filler contained in the underfill may cause separation in the process of heating and curing the resin. Disclosed is plating the surfaces of the copper pillars with solder. Mobilization of the filler charged in the underfill due to electric fields produced by local cells that are developed upon contact between dissimilar metals, is suppressed, and occurrence of crack at connection portions is obviated. Thus, connection reliability is increased.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 19, 2013
    Assignee: Namics Corporation
    Inventors: Osamu Suzuki, Seiichi Ishikawa, Haruyuki Yoshii
  • Patent number: 8574959
    Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: November 5, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 8563357
    Abstract: A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: October 22, 2013
    Assignee: Infineon Technologies AG
    Inventor: Chee Chian Lim
  • Patent number: 8558378
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.
    Type: Grant
    Filed: May 5, 2012
    Date of Patent: October 15, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Publication number: 20130241051
    Abstract: A method of fabricating a semiconductor comprises forming a plurality of stud bumps in a pattern having a geometrical shape on a surface of a substrate, the pattern defining a periphery of a bonding area on the surface of the substrate, and placing a solder material in the bonding area such that the solder material is surrounded by the stud bumps. The solder material is heated to a temperature where the solder material begins to flow within the bonding area. A bonding surface of a die is pressed onto the stud bumps with a sufficient pressure to crush the stud bumps a predetermined extent such that the solder material substantially evenly spreads between the stud bumps within the bonding area. The solder material is then solidified to form a final solder area that conforms to the geometrical shape of the pattern of stud bumps.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 19, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventor: Mark Eskridge
  • Publication number: 20130217224
    Abstract: A method for forming a micro bump includes forming a first nano-particle layer on a substrate and forming a second nano-particle layer on the first nano-particle layer. The first and second nano-particle layers include a plurality of first nano particles and a plurality of second nano particles, respectively. The method further includes irradiating a laser beam onto the second nano-particle layer, where the laser beam penetrates through the second nano-particle layer and is at least partially absorbed by at least some of the first nano particles to generate heat. The first nano particles and the second nano particles have different absorption rates with respect to the laser beam.
    Type: Application
    Filed: March 27, 2013
    Publication date: August 22, 2013
    Applicant: Industrial Technology Research Institute
    Inventor: Industrial Technology Research Institute
  • Patent number: 8492171
    Abstract: A method for rejoining an IC die, removed from an existing substrate, to a new substrate, is disclosed herein. In one embodiment, such a method includes grinding an existing substrate from an IC die to create a substantially planar surface exposing interconnects and surrounding underfill material. A new substrate is provided having electrically conductive pedestals protruding therefrom. The electrically conductive pedestals are positioned to align with the exposed interconnects and have a melting point substantially higher than the melting point of the interconnects. The method places the exposed interconnects in contact with the electrically conductive pedestals. The method then applies a reflow process to melt and electrically join the exposed interconnects with the electrically conductive pedestals. A structure produced by the method is also disclosed.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michel Deschenes, Marco Gauvin, Eric Giguère
  • Patent number: 8482104
    Abstract: A method for growth of indium-containing nitride films is described, particularly a method for fabricating a gallium, indium, and nitrogen containing material. On a substrate having a surface region a material having a first indium-rich concentration is formed, followed by a second thickness of material having a first indium-poor concentration. Then a third thickness of material having a second indium-rich concentration is added to form a sandwiched structure which is thermally processed to cause formation of well-crystallized, relaxed material within a vicinity of a surface region of the sandwich structure.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 9, 2013
    Assignee: Soraa, Inc.
    Inventors: Mark P. D'Evelyn, Christiane Poblenz, Michael R. Krames
  • Patent number: 8476762
    Abstract: A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: July 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • Patent number: 8450849
    Abstract: An electrical conductor is connected to a first microcircuit element having a first connector site axis and a second microcircuit having a second connector site axis. The first microcircuit and the second microcircuit are separated by and operatively associated with a first electrical insulator layer. The conductor and the first microcircuit element are separated by and operatively associated with a second electrical insulator layer. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric material. The microcircuit includes a UBM and solder connection to a FBEOL via opening. Sufficiently separating the first connector site axis and the second connector site axis so they are not concentric, decouples the UBM and solder connection to the FBEOL via opening. This eliminates or minimizes electromigration and the white bump problems. A process comprises manufacturing the microcircuit.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Minhua Lu, Eric D. Pefecto, David L. Questad, Sudipta K. Ray
  • Publication number: 20130119536
    Abstract: A method and a combination of studs, silicon chips, and solder bumps configured to restrict motion of a plurality of silicon chips. The combination includes: a plurality of studs, a plurality of silicon chips, a plurality of target solder bumps, where the plurality of solder bumps are melted between the plurality of silicon chips, where lateral positions of the plurality of studs are in accord with a pitch of the plurality of target solder bumps by using the pitch as a reference, where (i) lateral positions and lateral widths of studs of the plurality of studs located at a first silicon chip of the plurality of silicon chips and (ii) lateral positions and lateral widths of studs of the plurality of studs located at a second silicon chip of the plurality of silicon chips are restricted such that relative lateral motion on the respective silicon chips is restricted.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 16, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Patent number: RE44500
    Abstract: A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu-OSP can be formed over the substrate.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: September 17, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: RE44524
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: October 8, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: RE45932
    Abstract: A ball grid array semiconductor device has a wiring substrate (2), a semiconductor chip (6) disposed on one surface side of the wiring substrate, and a bump arrangement (5) as external terminals disposed on a surface side, opposite to the one surface side, of the wiring substrate. The semiconductor chip is mounted so that the center of the semiconductor chip is shifted from the center of the semiconductor device by one pitch or more of the bump arrangement, and the bump arrangement has a reinforcing structure (5-2) for a bump array located at a position farthest from the center of the semiconductor device in a shift direction of the semiconductor chip.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 15, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventor: Seiya Fujii