Contacting Diversely Doped Semiconductive Regions (e.g., P-type And N-type Regions, Etc.) Patents (Class 438/621)
  • Patent number: 9082786
    Abstract: A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: July 14, 2015
    Assignee: SANDISK 3D LLC
    Inventors: Kang-Jay Hsia, Calvin K. Li, Christopher John Petti
  • Patent number: 8987106
    Abstract: A semiconductor device manufacturing method includes forming a channel dope layer having a first electric conductive-type inside of a semiconductor substrate, the channel dope layer being formed in a region except for a drain impurity region where dopant impurities for forming a low-concentration drain region are introduced, and the channel dope layer being separated from the drain impurity region; forming a gate electrode on the semiconductor substrate via a gate insulating film; and forming a low-concentration source region inside of the semiconductor substrate on a first side of the gate electrode, and forming a low-concentration drain region in the drain impurity region of the semiconductor substrate on a second side of the gate electrode, by introducing second electric conductive dopant impurities inside of the semiconductor substrate with the gate electrode as a mask.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: March 24, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masashi Shima
  • Patent number: 8957434
    Abstract: According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer and a second insulating layer. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side electrode is provided on the second surface in a region including the light emitting layer. The n-side electrode is provided on the second surface in a region not including the light emitting layer. The p-side interconnect layer includes a p-side external terminal exposed from the second insulating layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface. The n-side interconnect layer includes an n-side external terminal exposed from the second insulating layer at the third surface.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Sugizaki, Akihiro Kojima, Yosuke Akimoto, Hidefumi Yasuda, Nozomu Takahashi, Kazuhito Higuchi, Susumu Obata, Hideo Tamura
  • Patent number: 8946075
    Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Patent number: 8940633
    Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Patent number: 8846522
    Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Raymond Nicholas Vrtis, Dingjun Wu, Mark Leonard O'Neill, Mark Daniel Bitner, Jean Louise Vincent, Eugene Joseph Karwacki, Jr., Aaron Scott Lukas
  • Patent number: 8809184
    Abstract: One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 19, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jin Cho, Jongwook Kye, Harry J. Levinson
  • Patent number: 8728891
    Abstract: Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: May 20, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl
  • Publication number: 20140117514
    Abstract: A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
    Type: Application
    Filed: December 24, 2013
    Publication date: May 1, 2014
    Applicant: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Calvin K. Li, Christopher John Petti
  • Patent number: 8669582
    Abstract: Disclosed is a light emitting device a light transmissive substrate, a light emitting structure disposed on the light transmissive substrate, comprising a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, a conductive layer disposed on the second conductive type semiconductor layer, a first electrode part disposed on the conductive layer, with at least predetermined region in contact with the first conductive type semiconductor layer, passing through the conductive layer, the second conductive type semiconductor layer and the active, and a first insulation layer disposed between the conductive layer and the first electrode part, between the second conductive type semiconductor layer and the first electrode part and between the active layer and the first electrode part.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Min Gyu Na, Sung Kyoon Kim, Myeong Soo Kim
  • Patent number: 8633105
    Abstract: A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: January 21, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Calvin Li, Christopher Petti
  • Patent number: 8633591
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Patent number: 8551818
    Abstract: A method of manufacturing an electronic device includes the steps of: forming a sacrifice layer made of at least one of an alkali metal oxide and an alkali earth metal oxide in a part of a first substrate; forming a supporting layer covering the sacrifice layer; forming an electronic device on the sacrifice layer with the supporting layer in between; exposing at least a part of a side face of the sacrifice layer by removing a part of the supporting layer; forming a support body between the electronic device and the supporting layer, and a surface of the first substrate; removing the sacrifice layer; breaking the support body and transferring the electronic device onto a second substrate by bringing the electronic device into close contact with an adhesion layer provided on a surface of the second substrate; removing a fragment of the support body belonging to the electronic device; removing at least an exposed region in the adhesion layer not covered with the electronic device; and forming a fixing layer on a
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: October 8, 2013
    Assignee: Sony Corporation
    Inventor: Masanobu Tanaka
  • Publication number: 20130256801
    Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: David YEN, Sung-Chieh LIN, Kuoyuan (Peter) HSU
  • Patent number: 8507375
    Abstract: An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: August 13, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: André P. Labonté, Richard S. Wise
  • Patent number: 8450216
    Abstract: An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lee-Wee Teo, Ming Zhu, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Patent number: 8435876
    Abstract: A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 7, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongchul Park, Jong-Kyu Kim, Ki-jin Park, Sangsup Jeong
  • Publication number: 20130095651
    Abstract: Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.
    Type: Application
    Filed: December 4, 2012
    Publication date: April 18, 2013
    Applicant: Cadeka Microcircuits, LLC
    Inventor: Cadeka Microcircuits, LLC
  • Patent number: 8409949
    Abstract: Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: April 2, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Arigane, Digh Hisamoto, Yasuhiro Shimamoto, Toshiyuki Mine
  • Patent number: 8389399
    Abstract: A method of forming a memory cell is provided, the method including forming a first pillar-shaped element comprising a first semiconductor material, forming a first mold comprising an opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: March 5, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Calvin Li, Christopher Petti
  • Patent number: 8378496
    Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: February 19, 2013
    Assignee: austriamicrosystems AG
    Inventors: Franz Schrank, Martin Schrems, Jochen Kraft
  • Patent number: 8354340
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: January 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Patent number: 8319264
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line contact hole obtained by etching the semiconductor substrate; a bit line contact plug having a smaller width than that of the bit line contact hole; and a bit line connected to the upper portion of the bit line contact plug, thereby preventing a short of the bit line contact plug and the storage node contact plug to improve characteristics of the semiconductor device.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: November 27, 2012
    Assignee: SK Hynix Inc.
    Inventor: Seung Bum Kim
  • Patent number: 8278721
    Abstract: The invention provides a method for forming a contact plug, comprising: forming a gate, a sidewall spacer, a sacrificial sidewall spacer, a source region and a drain region on a substrate, wherein the sidewall spacer is formed around the gate, the sacrificial sidewall spacer is formed over the sidewall spacer, and the source region and the drain region are formed within the substrate and on respective sides of the gate; forming an interlayer dielectric layer, with the gate, the sidewall spacer and the sacrificial sidewall spacer being exposed; removing the sacrificial sidewall spacer to form a contact space, the sacrificial sidewall spacer material being different from that of the gate, the sidewall spacer and the interlayer dielectric layer; forming a conducting layer to fill the contact space; and cutting off the conducting layer, to form at least two conductors connected to the source region and the drain region respectively.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: October 2, 2012
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang
  • Patent number: 8247286
    Abstract: One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: August 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Ryul Chang
  • Patent number: 8158473
    Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti(titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to form a barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Yukari Imai
  • Publication number: 20120080769
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.
    Type: Application
    Filed: October 1, 2010
    Publication date: April 5, 2012
    Inventors: Umesh Sharma, Harry Yue Gee, Der Min Liou, David D. Marreiro, Sudhama C. Shastri
  • Patent number: 8097535
    Abstract: The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element (424) between a first and a second metal structure.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: January 17, 2012
    Assignee: NXP B.V.
    Inventors: Kevin Cooper, Srdjan Kordic
  • Patent number: 8048689
    Abstract: Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: November 1, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Liang Wang, Michael R. Bruce
  • Patent number: 8017471
    Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Phillip F. Chapman, David S. Collins, Steven H. Voldman
  • Patent number: 8004087
    Abstract: A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the multilayered wiring is composed of an alloy having copper as a principal component. The concentration of at least one metallic element contained in the alloy as an added component in vias of the dual damascene wiring is determined according to the differences in the width of the wiring of an upper layer where the vias are connected. Specifically, a larger wiring width in the upper layer corresponds to a higher concentration of at least one metallic element within the connected vias. Accordingly, increases in the resistance of the wiring are minimized, the incidence of stress-induced voids is reduced, and reliability can be improved.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: August 23, 2011
    Assignee: NEC Corporation
    Inventors: Mari Amano, Munehiro Tada, Naoya Furutake, Yoshihiro Hayashi
  • Patent number: 7884002
    Abstract: A method of fabricating a self-aligned Schottky junction (29) in respect of a semiconductor device. After gate etching and spacer formation, a recess defining the junction regions is formed in the Silicon substrate (10) and a SiGe layer (22) is selectively grown therein. A dielectric layer (24) is then provided over the gate (14) and the SiGe layer (22), a contact etch is performed to form contact holes (26) and the SiGe material (22) is then removed to create cavities (28) in the junction regions. Finally the cavities (28) are filled with metal to form the junction (29). Thus, a process is provided for self-aligned fabrication of a Schottky junction having relatively low resistivity, wherein the shape and position of the junction can be well controlled.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: February 8, 2011
    Assignee: NXP B.V.
    Inventor: Markus Muller
  • Patent number: 7863180
    Abstract: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Edward Crandal Cooney, III, Peter James Lindgren, Dorreen Jane Ossenkop, Anthony Kendall Stamper
  • Patent number: 7829449
    Abstract: An electronic integrated circuit is fabricated by forming on a substrate, of which a part is composed of absorbing material, a portion made of a sacrificial material. The sacrificial material includes cobalt, nickel, titanium, tantalum, tungsten, molybdenum, gallium, indium, silver, gold, iron and/or chromium. A rigid portion is then formed in fixed contact with the substrate, on one side of the portion of sacrificial material opposite to the part of the substrate composed of absorbing material. The circuit is heated such that the sacrificial material is absorbed into the part of the substrate composed of absorbing material. A substantially empty volume is thus created in place of the portion of sacrificial material. The volume that is substantially empty can replace a dielectric material situated between the electrodes of a capacitor.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: November 9, 2010
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Phillips Electronics N.V.
    Inventors: Christophe Regnier, Aurelie Humbert
  • Patent number: 7825398
    Abstract: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion and the base portion having respective outer surfaces and the pillar portion having a width less than that of the base portion. A memory element is on a top surface of the pillar portion of the bottom electrode, and a top electrode is on the memory element. A dielectric spacer contacts the outer surface of the pillar portion, the outer surface of the base portion of the bottom electrode self-aligned with an outer surface of the dielectric spacer.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: November 2, 2010
    Assignees: Macronix International Co., Ltd., Qimonda A.G.
    Inventors: Thomas D. Happ, Yi-Chou Chen, Jan Boris Philipp, Hsiang-Lan Lung
  • Patent number: 7804158
    Abstract: An electronic device includes a substrate, an active circuit, and a shielding structure. The active circuit is formed on the substrate. The shielding structure is disposed surrounding the active circuit, and includes a first heavy ion-doped region, first metal stack, second heavy ion-doped region, second metal stack and top metal. The first heavy ion-doped is formed in the substrate and located at a first side of the active circuit. The first metal stack is formed on the first heavy ion-doped region of the substrate, wherein the first metal stack is connected to a ground voltage. The second heavy ion-doped region is formed in the substrate and located at a second side of the active circuit. The second metal stack is formed on the second heavy ion-doped region of the substrate. The top metal is formed on the first metal stack and second metal stack and passing over the active circuit.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: September 28, 2010
    Assignee: MaxRise Inc.
    Inventor: Hwey-Ching Chien
  • Patent number: 7781802
    Abstract: As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N? silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both of the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer are hetero-joined to the semiconductor base, and are ohmically connected to the anode electrode.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: August 24, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Shigeharu Yamagami, Masakatsu Hoshi, Yoshio Shimoida, Tetsuya Hayashi, Hideaki Tanaka
  • Patent number: 7749890
    Abstract: A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Keith Kwong Hon Wong, Chih-Chao Yang, Haining S. Yang
  • Patent number: 7745323
    Abstract: Disclosed herein is a metal interconnection structure of a semiconductor device, comprising lower metal interconnection layers disposed on a semiconductor substrate, a buffer layer made of a metal oxide disposed thereon, an intermetallic dielectric layer made of a low-k material disposed on the buffer layer of the metal oxide, and an upper metal interconnection layer disposed on the intermetallic dielectric layer and electrically connected through the intermetallic dielectric layer and buffer layer to the lower metal interconnection layers.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: June 29, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong-Su Park, Su Ho Kim
  • Patent number: 7700418
    Abstract: Disclosed herein is a method for production of a thin-film semiconductor device which includes, a first step to form a gate electrode on a substrate, a second step to form a gate insulating film of silicon oxynitride on the substrate in such a way as to cover the gate electrode, a third step to form a semiconductor thin film on the gate insulating film, and a fourth step to perform heat treatment in an oxygen-containing oxidizing atmosphere for modification through oxygen binding with oxygen-deficient parts in the silicon oxynitride film constituting the gate insulating film.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: April 20, 2010
    Assignee: Sony Corporation
    Inventor: Masafumi Kunii
  • Patent number: 7655563
    Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: February 2, 2010
    Assignee: Infineon Technologies AG
    Inventors: Gabriela Brase, Martin Ostermayr, Erwin Ruderer
  • Patent number: 7629247
    Abstract: A method of forming a three-dimensional, non-volatile memory array utilizing damascene fabrication techniques is disclosed. A bottom set of conductors is formed and a set of first pillar shaped elements of heavily doped semiconductor material as formed thereon. A mold is formed of insulating material having pillar shaped openings self-aligned with the first pillar shaped elements and a second semiconductor is deposited over the mold to form second pillar shaped elements aligned with the first pillar shaped elements. The pillar elements formed may be further processed by forming another mold of insulating material having trench openings aligned with the pillar shaped elements and then filling the trenches with conductive material to form conductors coupled to the pillar shaped elements.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: December 8, 2009
    Assignee: Sandisk 3D LLC
    Inventors: Kang-Jay Hsia, Calvin Li, Christopher Petti
  • Patent number: 7595232
    Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: September 29, 2009
    Assignee: International Business Machines Corporation
    Inventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
  • Patent number: 7579270
    Abstract: It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device with preferable yield. In the invention, two-step etching is performed when selectively removing an interlayer insulating film with at least two layers constituting a semiconductor device, and forming an opening. One feature of the invention is that at least either one of a first gas (a first etching gas) and a second gas (a second etching gas) used at the time of the two-step etching is added with an inert gas.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: August 25, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomohiko Sato, Shigeharu Monoe, Shinya Sasagawa
  • Patent number: 7572723
    Abstract: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: August 11, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Varughese Mathew, Eddie Acosta, Ritwik Chatterjee, Sam S. Garcia
  • Patent number: 7566651
    Abstract: A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Keith Kwong Hon Wong, Chih-Chao Yang, Haining S Yang
  • Patent number: 7541277
    Abstract: A method for forming a dielectric cap layer over an interconnect layer formed by a back-end-of-the-line (BEOL) interconnect process, the interconnect process including: lithography, reactive ion etching (RIE), metal filling of BEOL conductors, and chemical-mechanical polishing (CMP), wherein a sacrificial material resides between conductors of the interconnect layer, and wherein the dielectric cap layer is made porous through an oxidation process.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: June 2, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kevin Shawn Petrarca, John Charles Petrus, Karl W. Barth, Kaushik A. Kumar
  • Publication number: 20090020823
    Abstract: A semiconductor device of the present invention includes a first transistor, a first stress-inducing film, a first insulating film, and a second insulating film. The first transistor is formed in a first active region of a semiconductor substrate, and includes a first gate electrode. The first stress-inducing film is formed so as to cover the first gate electrode, and applies a stress to the channel region of the first transistor. The first insulating film is formed on the first stress-inducing film and has a planarized upper surface. The second insulating film is formed on the first insulating film.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 22, 2009
    Inventor: Tomohiro Fujita
  • Publication number: 20080293238
    Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Inventors: Kern-Huat Ang, Po-Jen Wang
  • Patent number: 7445958
    Abstract: A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: November 4, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori